|Publication number||USRE38010 E1|
|Application number||US 09/305,328|
|Publication date||Feb 25, 2003|
|Filing date||May 4, 1999|
|Priority date||Feb 22, 1993|
|Also published as||US5633881|
|Publication number||09305328, 305328, US RE38010 E1, US RE38010E1, US-E1-RE38010, USRE38010 E1, USRE38010E1|
|Inventors||Ephraim Zehavi, Jack K. Wolf|
|Original Assignee||Qualcomm, Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (24), Non-Patent Citations (5), Referenced by (2), Classifications (21), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 08/023,788, filed on Feb. 22, 1993 now abandoned.
I. Field of the Invention
The present invention relates to data communications. More particularly, the present invention relates to a novel and improved method and apparatus for encoding and decoding trellis modulated data based upon punctured convolutional codes.
II. Description of the Related Art
The field of data communications is concerned with raising the data throughput of a transmission system with a limited signal to noise ratio (SNR). The use of error correcting circuitry such as the Viterbi decoder allows system tradeoffs to be made with smaller SNRs or higher data rates to be used with the same bit error rate (BER). The decrease in the SNR needed is generally referred to as coding gain. Coding gain may be determined from bit error performance curves. In a graph of bit error performance curves, the BER of uncoded and various coded data is charted against Eb/No, where Eb is the energy per bit and No is the one sided Gaussian White Noise power spectral density. The coding gain at any point along a bit error performance curve for a particular BER level is determined by subtracting the coded Eb/No from the uncoded Eb/No. In the paper “Viterbi Decoding for Satellite and Space Communication”, by J. A. Heller and I. M. Jacobs, IEEE Transactions on Communication Technology, Vol. COM-19, pgs. 835-848, October 1971, extensive results of simulations on various decoder apparatus were reported.
The coding rate and constraint length are used to define the Viterbi decoder. The coding rate (m/n) corresponds to the number of coding symbols produced (n) for a given number of input bit (m). The coding rate of ½ has become one of the most popular rates, although other code rates are also generally used. One class of codes with m≠1 are called punctured codes and are produced by discarding or erasing symbols from the rate 1/n code. The constraint length (K) is related to the length of the conventional encoder used in the encoding of the data. A constraint length of K=7 is typical in convolutional coding schemes. The convolutional encoder can be thought of as a Finite Impulse Response (FIR) filter with binary coefficients and length K−1. This filter produces a symbol stream with 2K−1 possible states.
The basic principal of the Viterbi algorithm is to take a convolutionally encoded data stream that has been transmitted over a noisy channel and use the properties of the convolutional code to determine the transmitted bit stream. The Viterbi algorithm is a computationally efficient method of updating the conditional probabilities of all 2K−1 states and finding the most probable bit sequence transmitted. In order to compute this probability, all the conditional probabilities of 2K−1 states for each bit must be computed. For a rate ½ code, the resulting decision from each of these computations is stored as a single bit in a path memory.
A chainback operation, an inverse of the encoding operation, is performed in which the p·2K−1 decision bits are used to select an output bit, where p is the path memory depth. After many states the most probable path will be selected with a high degree of certainty. The path memory depth must be sufficiently long to allow this probability to approach 1. For a rate ½ code, an exemplary path memory depth is about (5·K), or 35 states. For a rate ⅞ punctured code the optimal depth increases to 96 states.
Constraint lengths of K less than 5 are too small to provide any substantial coding gain, while systems with K greater than 7 are typically too complex to implement as a parallel architecture on a single VLSI device. As the constraint length increases, the number of interconnections in a fully parallel computation section increases as a function of (2K−1·L), where L is the number of bits of precision in the state metric computations. Therefore, where K is greater than 7, serial computation devices are generally used which employ large external random access memories (RAMs).
In the paper “Channel Coding with Multilevel/Phase Signal” by G. Ungerboeck, IEEE Transactions on Information Theory, Vol. IT-28, pgs. 55-67, January 1982, a trellis coded modulation (TCM) was described. In Ungerboeck it was shown that within a given spectral bandwidth, it is possible to achieve an Asymptotic Coding Gain of up to 6 dB by employing a rate (n−1)/n convolutional code and doubling the signal set. Unfortunately, for each modulation technique and for each bit rate, the maximal coding again is achieved by a different convolutional code. Further disclosed were the results of a search for all convolutional codes for several rates and modulation techniques, and the best codes presented.
In the paper “A Pragmatic Approach to Trellis-Coded Modulation” by A. J. Viterbi, J. K. Wolf, E. Zehavi and R. Padovani, IEEE Communications Magazine, pgs. 11-19, July 1989, a pragmatic approach to trellis coded modulation (PTCM) was disclosed. The underlying concept therein is that a somewhat lower coding gain is achievable by a PTCM based on the “industry standard” rate ½, K=7 convolutional code. Although a lower coding gain is realized, it is very close to the coding gain of Ungerboeck at BERs of interest.
Trellis coding is an attractive coding technique since it possesses an aspect which other coding techniques lack. The power of trellis coding lies in the fact that even though no apparent coding operation is performed on some of the bit(s) of the input data, the decoder is able to provide error correction on all bits. Generally the use of TCM techniques to achieve efficient use of power-bandwidth resources has been limited to low speed applications in digital signal processor implementations. The use of PTCM techniques enable VLSI implementations of an encoder/decoder capable of operating at high rates. A decoder using PTCM techniques is capable of handling different modulation techniques, such as M-ary phase-shift keying (M-ary PSK) including Binary PSK (BPSK), Quadrature PSK (QPSK), 8-PSK, and 16-PSK.
In the paper, “Development of Variable-Rate Viterbi Decoder and Its Performance Characteristics,” Sixth International Conference on Digital Satellite Communications, Phoenix Ariz., September 1983, Y. Yasuda, Y. Hirata, K. Nakamura and S. Otani discuss a method whereby a class of high rate binary convolutional codes can be constructed from a single lower rate binary convolutional code. The advantage of punctured codes for binary transmission is that the encoders and decoders for the entire class of codes can be constructed easily by modifying the single encoder and decoder for the rate ½ binary convolutional code from which the high rate punctured code was derived. The current invention will be concerned primarily with rate (m−1)/m binary convolutional codes (m a positive integer greater than or equal to 3) formed from puncturing a particular rate ½ convolutional code which has become a de-facto standard of the communications industry. This code has constraint length 7 and generator polynomials G1((D)=1+D2+D3+D5+D6 and G2(D)=1+D+D2+D3+D6. Indeed, many commercial VLSI convolutional encoder and decoder chips (including a device marketed under Part No. Q1875 by QUALCOMM Incorporated of San Diego, Calif.) contain encoders and decoders for punctured binary codes using this de-facto standard rate ½ code.
It is therefore an object of the present invention to provide a novel method and circuitry for encoding and decoding trellis data using punctured rate ½ convolutional encoders.
The present invention is a novel and improved method and apparatus for encoding and decoding trellis modulated data based upon punctured rate ½ convolutional codes. In accordance with the present invention, a trellis encoder and decoder are disclosed in which a circuit is provided that encodes and decodes based upon punctured rate ½ convolutional encoding.
In the present invention, a transmitter encodes a bit stream, parallel or serial, according to a k/n encoding format provided by a punctured rate ½ encoder. For each set of k input bits n output symbols are provided by the first encoder. The n output symbols are then provided to a parallel n to parallel p converter that in effect gates the data symbols to provide sets of data of p symbols each. If n is divisible by p, the converter acts as a buffer to provide p symbols in each set. Otherwise the converter will wait for the next group of n symbols before providing the last group of p symbols from the current n symbols.
Each set of symbols is provided to an interleaver comprised of p−1 parallel delay elements that can be implemented as digital delays or delay lines having delays of predetermined duration. The purpose of the interleaving proces is to increase the diversity in the data in such a way that if a modulated symbol is lost in transmission the error may be recoverable with the use of error correcting algorithms in the decoder. The output of the delays and the one undelayed symbol are then provided to an m-ary modulator that provides a modulation in accordance to the received bits.
In the receiver, a decoder presents the received signal to a demodulator that converts the modulation values to sets of p symbols. These sets of symbols are then provided to a deinterleaver that has p−1 delay elements that can be implemented as digital delays or delay lines. The three deinterleaved symbols are provided to three separate metric calculators that calculate from the received symbols metrics that define quantities proportional to the likelihood of alternative received hypotheses. The metrics are provided to a parallel p to parallel n converter that provides the metric values of data as n metrics to a rate ½ punctured decoder that operates with the aid of the Viterbi algorithm to provide a corrected estimate of the transmitted bit sequence.
The features, objects, and advantages of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:
FIG. 1 is a block diagram of a trellis encoder for a rate ½ encoder punctured for a rate k/n;
FIG. 2 is a block diagram of a trellis decoder for decoding data encoded by a rate ½ encoder punctured for a rate k/n;
FIG. 3 is a diagram illustrating the spatial relationships in octal modulated signal space.
Referring to FIG. 1, an encoding circuit is disclosed for encoding digital data preferably by m-ary PSK modulation and transmission. Although the example illustrated in FIG. 1 is configured for 8 PSK modulation, other m-ary modulation schemes are readily derived therefrom.
In FIG. 1 a bit stream is provided to encoder 1 which is configured as a rate ½ convolutional encoder punctured to a rate k/n. For each k bits 2k symbols (k symbol pairs) are generated. For only n-k of the generated symbol pairs are both outputs provided from encoder 1. For the remaining 2k-n pairs of generated symbols only one member of each pair is output from encoder 1.
The n output symbols (C1-Cn) are provided to a parallel n to parallel p converter 2, where as illustrated in FIG. 1, p=3. Converter 2 gates the data symbols (C1-Cn) to provide sets of data with p symbols in each set. For 8 PSK modulation (2P-ary modulation where p=3), if n is divisible by p the converter acts as a buffer to provide three-tuples, i.e. sets of three symbols, for all of the current n symbols. Otherwise the converter will wait for the next group of n symbols before providing the last three-tuple from the current n symbols. Similarly for 16 PSK modulation (2P-ary modulation where p=4) if n is divisible by p the converter acts as a buffer to provide quadruples, i.e. sets of four symbols, for all of the current n symbols. Otherwise the converter will wait for the next group of n symbols before providing the last quadruple from the current n symbols.
Each set of symbol data is provided to interleaver 3 comprised of p−1 delay elements. For the case of 8 PSK modulation, two delay elements are provided so as to delay two symbols of each three-tuple. As illustrated in FIG. 1 the symbol a provided on line a is provided undelayed to modulator or modem 6 and as such may be provided directly from converter 2 to modem 6. Delay elements 4 and 5 respectively delays to the symbols b and c respectively provided on lines b and c. The duration of the delay induced by delay element 5 is twice that of delay element 4. For higher orders of PSK modulation the delays may also be on the same incremental order with the longest delay being p−1 times the shortest delay. The duration of the delay of delay element 4 depends on the code in use, and in general is longer than the length of any codeword that has Hamming distance dfree+1 or less.
The purpose of the interleaving process is to increase the diversity of the transmitted signal. For example if a symbol is received weak or corrupted the interleaving process will disperse the effects of the lost signal among p nonconsecutive symbols. This will allow the Viterbi decoder to recover the correct data. A group of 3 bits (a,b,c) at the output of the interleaver is mapped by modem 6 into the 8-PSK signal set preferably, although not necessarily, according to a to modified Gray code mapping scheme. The mapped signal points are digitally pulse shaped by modem 6 for transmission over the channel.
Referring to FIG. 2, the received modulated data r is received by demodulator or modem 10 and converted to sets of p symbols. The sets of p symbols are provided to deinterleaver 11 comprised of p−1 delay elements. For the 8 PSK example modem 10 converts the received signal into three-tuples of symbols and provides each three-tuple to deinterleaver 11 which in this example is comprised of the two delay elements 12 and 13. In this case the symbol a is provided to delay element 13, with the symbol b provided to delay element 12. Delay element 13 provides a delay in the symbol a corresponding on the order of the delay provided to symbol c (delay element 5) in transmission encoding. Similarly delay element 12 provides a delay in the symbol b corresponding on the order of the delay provided to symbol b (delay element 4) in transmission encoding. Thus interleaver 11 realigns the symbol set as provided to interleaver 3 for transmission. The output of deinterleaver 11 is provided to p metric calculators. It is again noted that since the symbol c is undelayed it may be provided directly from modem 10 to a metric calculator. For the 8 PSK example the three-tuples are provided to three metric calculators 14, 15 and 16. For this 8 PSK system the receiver uses the following metrics.
where ∥r−μ(x,y,z)μ2 is the Euclidean distance between the received signal r and the signal point μ(x,y,z). Similar metrics may be computed for systems using other m-ary modulation.
Each of metric calculators 14 (metrics m(r,a)), 15 (metrics (m(r,b)) and 16 (metrics m(r,c)) generates two metrics associated with the hypotheses that a=0 or a=1. Note that all the signal points with a value a=0 are in one subset and all the signal points with a value a=1 are in another subset as shown in FIG. 3.
The metrics are provided to a parallel p to parallel n buffer 17 that stores the metrics that arrive in p sets and provides n sets of metrics to Viterbi decoder 18. Decoder 18 is configured as a rate ½ punctured decoder for rate k/n decoding. The rate ½ punctured decoder for rate k/n provides from the received metrics in accordance with the history of received data a corrected estimate of the input bits.
The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. The various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8369435 *||Feb 1, 2010||Feb 5, 2013||Intersil Americas Inc.||Frame structure for a QAM system|
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|U.S. Classification||714/756, 714/786, 375/308|
|International Classification||H03M13/25, H04L1/00|
|Cooperative Classification||H03M13/25, H04L1/0054, H04L1/0059, H03M13/256, H03M13/3961, H04L1/006, H04L1/0068, H03M13/6362|
|European Classification||H04L1/00B7C, H03M13/39M, H03M13/63R2, H03M13/25T, H04L1/00B7C1, H04L1/00B5L, H03M13/25, H04L1/00B7R1|
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Year of fee payment: 12