USRE38166E1 - Circuit and method for reading a memory cell that can store multiple bits of data - Google Patents
Circuit and method for reading a memory cell that can store multiple bits of data Download PDFInfo
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- USRE38166E1 USRE38166E1 US09/410,164 US41016499A USRE38166E US RE38166 E1 USRE38166 E1 US RE38166E1 US 41016499 A US41016499 A US 41016499A US RE38166 E USRE38166 E US RE38166E
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5632—Multilevel reading using successive approximation
Definitions
- the present invention relates to a sensing circuit for serial dichotomic sensing of multiple-levels non-volatile memory cells.
- a memory device with memory cells capable of storing two or even four bits has a storage capacity two or, respectively, four times higher than that of a memory device with the same chip size but with memory cells capable of storing only one bit each.
- Non-volatile memory cells i.e., memory cells which retain their programming state even in the absence of power
- MOS field-effect transistors data can be programmed in non-volatile memory cells by changing the threshold voltage of the MOS field-effect transistors: in the case of ROMs this is done during their fabrication, while in the case of EPROMs, EEPROMs and Flash EEPROMs, the change in the threshold voltage is achieved by properly biasing the MOS field effect transistors to cause an injection of charges in a floating gate.
- a fixed voltage VG is applied to the control gate of the MOS transistor: the programming state of the memory cell can thus be determined by detecting the position of the threshold voltage of the MOS transistor with respect to said fixed gate voltage.
- a memory cell can show two different programming states (logic levels), corresponding to two different threshold voltage values; hereinafter, such a cell will be called a “two-level memory cell.”
- the reading of the memory cells is performed by a so-called “sensing circuit,” which delivers a voltage signal having two distinct possible values, corresponding to the two logic levels.
- the discrimination of the m different programming levels can be performed by means of a either a voltage-mode sensing technique or a current-mode sensing technique.
- the allowed threshold voltage range of the memory cell is divided, on the basis of the electric and physical characteristics of the memory cells, into m sub-intervals, each corresponding to one of the different m levels to be discriminated.
- the memory cell is then programmed in a desired one of the m different levels by properly adjusting its threshold voltage, so that when the memory cell is biased in the prescribed sensing conditions, it sinks a current corresponding to the desired programming level.
- Parallel-mode sensing is for example described in A. Bleiker, H. Melchior, “A Four-State EEPROM Using Floating-Gate Memory Cells,” IEEE Journal of Solid State Circuits, vol. SC-22, No. 3, July 1987, pp. 460-463.
- This technique is the natural extension of the conventional technique used for two-level memory cells, and provides for generating m ⁇ 1 distinct predetermined references (current references for the current-mode approach, or voltage references for the voltage-mode approach), and for performing m ⁇ 1 simultaneous comparisons of such m ⁇ 1 distinct voltage or current references with a current (or a voltage) derived from the memory cell to be read.
- the advantages of the parallel-mode sensing technique are its high speed and the independence of the sensing time from the programming state of the memory cell; a disadvantage is the large area required by the sensing circuit, since m ⁇ 1 distinct comparison circuits are necessary to perform the m ⁇ 1 simultaneous comparisons.
- serial-mode sensing requires just one reference (current or voltage), which can be varied according to a prescribed law. This single reference is used to perform a series of successive comparisons, and is varied to approximate the analog current or voltage derived from the memory cell to be read.
- a serial-mode sensing circuit is simple to implement, and requires only a small area.
- the first methodology also called “sequential,” described for example in M. Horiguchi et at., “An Experimental Large-Capacity Semiconductor File Memory Using 16-Levels/Cell Storage,” IEEE Journal of Solid State Circuits, vol. SC-23, No. 1, February 1988, pp. 27-32, consists of a succession of comparisons (at most m ⁇ 1 ) between a fixed quantity (voltage or current) and a variable quantity (voltage or current) which is sequentially varied starting from an initial value.
- the fixed quantity can be the current sunk by the memory cell to be read (subject to a prescribed biasing condition), while the variable quantity can be a current supplied by a digitally-driven generator.
- the (constant) current sunk by the memory cell to be read is compared with a reference current which takes successively increasing (or decreasing) discrete values starting from a minimum (or maximum) value; said discrete values are ideally chosen in such a way as to fall between the different current values corresponding to the m programming levels of the memory cell, so that the result of a comparison is negative (or positive) as long as the reference current is lower (or higher) than the cell's current.
- the series of successive comparisons stops after the first positive (or negative) result; the last value of the reference current represents the current of the memory cell, except for a constant term associated with the position of the reference current value with respect to the programming levels of the memory cell.
- the time required to read a memory cell with the serial sequential method is not uniform, but depends on the particular programming level of the memory cell and on the starting value of the reference voltage or current (the sensing time depends on the distance between the programming level of the cell to be read and the starting value of the reference voltage or current): from a minimum of one to a maximum of m ⁇ 1 comparison steps are necessary to determine the programming state of an m-level memory cell.
- the sensing time soon becomes excessive with an increase in the number of bits stored in a single memory cell.
- the second serial-mode sensing methodology also called “dichotomic,” is described in the co-pending European Patent Application No. 95830023.8 filed on January 27, 1995 in the name of the same applicant.
- This methodology consists of a successive approximations search that, starting from an initial value for the reference current, finds the value of the memory cell current after a succession of iterations. At each step of the iterative search, the (constant) memory cell current is compared with the variable reference current, whose value is chosen according to a dichotomic or “binary search” algorithm.
- the initial interval of possible memory cell current values is divided in two parts: depending on the result of the comparison, the successive dichotomy will be applied to only that part of the initial interval wherein the memory cell current falls; the iterative search is recursively repeated until the value of the memory cell current is determined.
- the sensing circuit comprises a variable reference current generator controlled by a successive approximation register supplied with an output signal of a current comparator; the successive approximation register comprises a sequential network that, starting from a predetermined initial state, evolves through a succession of states, each one corresponding to one step of the serial dichotomic search.
- the circuit implementation of the sensing circuit strongly depends on the structure of the variable reference current generator: this in fact affects the structure of the current comparator and of the successive approximation register.
- variable reference current generator comprises m ⁇ 1 distinct current generators which are activated in a mutually exclusive way; each one of the m ⁇ 1 current generator corresponds to one of m ⁇ 1 values which can be taken by the reference current (absolute current generators technique).
- each current generator is formed by a reference memory cell identical to the memory cell to be read.
- the reference memory cells are programmed in m ⁇ 1 distinct states which, however, do not coincide with any of the m programming levels of the memory cells to be read, since the reference current values shall fall between the cell current values; in this case, the current comparator can be balanced (i.e., the currents to be compared are supplied to the inputs of the comparator in a 1:1 ratio).
- the reference memory cells can be programmed in m ⁇ 1 distinct programming levels which coincide with the programming levels of the memory cell to be read.
- the reference current is given by the sum of an offset current plus a current equal to one of the possible values of the memory cell current.
- FIG. 1 schematically shows a multiple-level non-volatile memory cell under sensing conditions, and a reference current generator used to sense the memory cell according to a serial dichotomic sensing method
- FIG. 2 diagrammatically shows the distribution of currents sunk by a four-level memory cell in its four different programming conditions, and the distribution of reference currents used to sense the memory cell according to the serial dichotomic sensing method;
- FIGS. 3 and 4 diagrammatically show the steps of the serial dichotomic sensing method for two different programming conditions of the memory cell
- FIG. 5 schematically shows a sensing circuit for sensing multiple-level non-volatile memory cells according to the present invention
- FIG. 6 schematically shows a variable reference current generator for the sensing circuit of FIG. 5;
- FIG. 7 is a circuit diagram of a Successive Approximation Register (SAR) of the circuit of FIG. 5, suitable for sensing four-level memory cells;
- SAR Successive Approximation Register
- FIG. 8 is a circuit diagram of a current comparator of the sensing circuit of FIG. 5;
- FIG. 9 is a truth table of the SAR of FIG. 7;
- FIG. 10 is a state-transition diagram of the SAR of FIG. 7.
- FIG. 11 is a time diagram of some signals of the SAR of FIG. 5 .
- a memory cell MC to be read is biased with a fixed, prescribed control gate voltage VG (FIG. 1 ).
- the memory cell MC shown in FIG. 1 is a floating-gate MOS field effect transistor, such as an EPROM, EEPROM or Flash EEPROM memory cell. Nevertheless, the memory cell could be a simple MOSFET with threshold voltage adjusted during fabrication, as in the case of a ROM memory cell.
- a current generator G is also shown supplying a reference current IR; IR is not constant, but can take values belonging to a discrete set, as will now be explained.
- the comparison tells that the cell current IC is higher than I 1 : a priori, it could be equal to IC 2 or IC 3 .
- the programming condition of the memory cell MC has thus been determined in only two steps.
- the programming condition of the memory cell MC has been determined in two steps.
- the number of steps required to determine the programming condition of the memory cell MC is uniform, i.e., it does not depend on the programming condition itself, and it is always equal to two in the example illustrated in FIGS. 2-4. It is straightforward to show that the programming condition of a sixteen-level memory cell is determined in four steps.
- FIG. 5 schematically shows a sensing circuit according to the present invention.
- the circuit substantially comprises a digitally-driven variable reference current generator G for generating a variable reference current IR, a current comparator 1 for comparing the reference current IR with a current IC sunk by a memory cell MC to be read, and a Successive Approximation Register (“SAR”) 2 .
- G digitally-driven variable reference current generator
- SAR Successive Approximation Register
- the current comparator 1 has an inverting input connected to the drain electrode of a memory cell MC to be sensed, and a non-inverting input connected to the variable reference current generator G; the comparator 1 has an output signal CMP which is supplied to the SAR 2 .
- the SAR 2 is further supplied with a preset signal PR and with a clock signal CK (timing signal), and supplies a group CNT of control signals (in digital format) to the variable reference current generator G; the SAR 2 also generates a group OUT of output signals carrying in digital format the programming state of the sensed memory cell MC.
- the reference current generator G comprises three distinct current generators IR 0 , IR 1 , and Ioff.
- Ioff is an offset current generator, generating a constant current, and is permanently connected to the non-inverting input of the current comparator 1 .
- IR 0 and IR 1 are instead connectable to the non-inverting input of the current comparator 1 by means of respective switches SW 0 and SW 1 , activated by respective control signals Q 0 and Q 1 of the group CNT.
- Ioff is equal to the reference current I 0 shown in FIG. 2, i.e., it is equal to (IC 1 +IC 0 )/2, here IC 1 /2, because in the case IC 0 , the minimum memory cell current, is zero.
- the values of IR 0 and IR 1 are respectively equal to IC 1 and IC 2 , i.e., to the currents sunk by a memory cell MC in two particular programming states.
- the current generators IR 0 and IR 1 are implemented by means of two reference memory cells, identical to the memory cell MC to be read, programmed in two of the four possible programming states of the memory cells MC, more precisely in the states corresponding to the memory cell current values IC 1 and IC 2 , respectively.
- variable reference current IR can take the following values:
- These values are central with respect to the memory cell current values IC 0 -IC 3 , and are obtained by an additive process, adding a constant offset to the values IC 1 and IC 2 .
- the reference current values can be adjusted by simply varying the value of the offset current generator Ioff.
- the current comparator 1 can be balanced (i.e., the currents to be compared are supplied to the inputs of the comparator in a 1:1 ratio).
- a balanced comparator is better than an unbalanced one from the point of view of the circuit and layout symmetry.
- a balanced comparator has a better common-mode rejection ratio, a better controlled switching characteristic, and lower mismatch errors.
- the characteristics of the current comparator 1 depend on the number of programming levels to be discriminated.
- the input sensitivity i.e., the minimum current difference which can be detected by the comparator
- the difference between the currents of two adjacent programming states taking into account the spreading &values due to process tolerances.
- FIG. 8 A suitable current comparator structure is shown in FIG. 8 .
- the circuit comprises two load MOSFETs DL and DR (P-channel type) performing a current/voltage conversion of the memory cell current IC and of the reference current IR, respectively.
- the drain voltages 4 and 5 of MOSFETs DL and DR control the gates of two cross-connected MOSFETs MS 1 and MR 1 (P-channel type) forming a latch.
- the source electrodes of MS 1 and MR 1 can be connected to a power supply line VDD through two respective P-channel MOSFETs T 3 and T 4 which are commonly driven by a signal CKS derived from the clock signal CK (CKS can for example be the logic complement of CK).
- the drain electrodes of MS 1 and MR 1 can be short-circuited to each other by the activation of an N-channel MOSFET TE driven by the signal CKS.
- the drain electrode of MR 1 forms the comparator output CMP.
- Experimental tests have shown that this circuit is quite fast even if a power supply VDD of 3 V is used, and has an input sensitivity of about 10 uA. These characteristics make the shown comparator structure particularly suitable for the sensing of four-levels memory cells.
- the SAR 2 comprises a sequential network (or state-machine) implementing the successive approximation search algorithm.
- the state of the sequential network at a given step of the successive approximation search depends on its state at the present step, and on the result of the comparison between the cell current IC and the reference current IR at the preceding step.
- the sequential network activates in the correct sequence the switches SW 0 , SW 1 , depending on the results of the comparisons.
- FIG. 7 is a circuit diagram of the sequential network of the SAR 2 in the case of a sensing circuit for four-level memory cells.
- the sequential network comprises two Delay-type (“D-type”) flip-flops FF 0 , FF 1 .
- Each flip-flop FF 0 , FF 1 has a clock input CK and a preset input PR; the clock inputs CK and the preset inputs PR of the flip-flops FF 0 , FF 1 are commonly connected to the clock signal CK and to the preset signal PR, respectively; more precisely, FFO receives the logical complement of PR (as indicated by the inverting dot at the input PR of FFO).
- Each flip-flop has a data input D 0 , D 1 , a “true” data output Q 0 , Q 1 , and a “complemented” data output Q 0 N, Q 1 N which is the logic complement of Q 0 , Q 1 ; as known to anyone skilled in the art, in a D-type flip-flop the true data output after a clock pulse takes the logic value of the data input during said clock pulse.
- the data input DO of the first flip-flop FF 0 is supplied with the complemented data output Q 0 N of the first flip-flop FF 0 .
- the data input D 1 of the second flip-flop FF 1 is supplied with an output of a NOR gate 5 whose inputs are represented by the signal CMP and by the complemented data output Q 0 N of the first flip-flop FF 0 .
- the true data outputs Q 0 , Q 1 of the flip-flops FF 0 , FF 1 form the group of digital control signals CNT for the variable reference current generator G in FIG. 6 .
- the switches SW 0 , SW 1 close when the respective control signal Q 0 , Q 1 is a logic “1”, otherwise the switches SW 0 , SW 1 are open.
- the signal CMP complemented by an inverter 3 , forms a least significant bit OUT 0 of a two-bits output code OUT 0 , OUT 1 ; the true data output Q 1 of flip-flop FF 1 forms a most significant bit OUT 1 of the two-bits output code OUT 0 , OUT 1 .
- OUT 0 and OUT 1 represent the group of signals OUT shown in FIG. 5 .
- the sensing of a two-levels memory cell MC is carded out in two steps.
- the valid output data OUT 0 , OUT 1 are available at t 0 +( ⁇ fraction (3/2) ⁇ )T (where T is the period of the clock signal CK), i.e., before the end of the second clock pulse.
- the SAR 2 of the sensing circuit of the present invention is much simpler than that described in the already-cited European Patent Application No. 95830023.8: since in the variable reference current generator G one of the three current generators (Ioff) is permanently connected to the current comparator, only two control signals Q 0 and Q 1 (in the case of a four-level memory cell) are necessary to control the reference current generator G (in general, for an m-level memory cell, m ⁇ 2 control signals are necessary). Furthermore, in the case of four-level memory cells, the output digital code OUT is obtained directly from the sequential network that implements the dichotomic search algorithm, no combinatorial network being necessary.
- variable reference current generator G should comprise an offset current generator Ioff with value equal to (IC 0 +IC 1 )/2 (IC 0 and IC 1 being the two lowest currents of an m-level memory cell), and m ⁇ 2 distinct current generators with values equal to IC 1 , IC 2 , . . . , ICm ⁇ 2.
Abstract
Description
Claims (41)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US09/410,164 USRE38166E1 (en) | 1995-03-23 | 1999-09-30 | Circuit and method for reading a memory cell that can store multiple bits of data |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP95830110 | 1995-03-23 | ||
EP95830110A EP0734024B1 (en) | 1995-03-23 | 1995-03-23 | Sensing circuit for serial dichotomic sensing of multiple-levels non-volatile memory cells |
US08/592,939 US5673221A (en) | 1995-03-23 | 1996-01-29 | Circuit and method for reading a memory cell that can store multiple bits of data |
US09/410,164 USRE38166E1 (en) | 1995-03-23 | 1999-09-30 | Circuit and method for reading a memory cell that can store multiple bits of data |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US08/592,939 Reissue US5673221A (en) | 1995-03-23 | 1996-01-29 | Circuit and method for reading a memory cell that can store multiple bits of data |
Publications (1)
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USRE38166E1 true USRE38166E1 (en) | 2003-07-01 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US08/592,939 Ceased US5673221A (en) | 1995-03-23 | 1996-01-29 | Circuit and method for reading a memory cell that can store multiple bits of data |
US09/410,164 Expired - Lifetime USRE38166E1 (en) | 1995-03-23 | 1999-09-30 | Circuit and method for reading a memory cell that can store multiple bits of data |
Family Applications Before (1)
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US08/592,939 Ceased US5673221A (en) | 1995-03-23 | 1996-01-29 | Circuit and method for reading a memory cell that can store multiple bits of data |
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US (2) | US5673221A (en) |
EP (1) | EP0734024B1 (en) |
JP (1) | JP2857649B2 (en) |
DE (1) | DE69514783T2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060140010A1 (en) * | 2004-12-29 | 2006-06-29 | Lorenzo Bedarida | Method and system for reducing soft-writing in a multi-level flash memory |
US20070277141A1 (en) * | 2003-05-21 | 2007-11-29 | Tobias Buehler | Integrated Circuit Arrangement, and Method for Programming an Integrated Circuit Arrangement |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69626631T2 (en) * | 1996-06-05 | 2003-11-06 | St Microelectronics Srl | Page mode memory with multi-level memory cells |
KR100226769B1 (en) * | 1996-11-19 | 1999-10-15 | 김영환 | Data sensing device of multi bit-per-cell and method of the same |
US6307406B1 (en) | 1998-09-25 | 2001-10-23 | Lucent Technologies, Inc. | Current comparator for current mode circuits |
JP3366264B2 (en) * | 1998-09-28 | 2003-01-14 | エヌイーシーマイクロシステム株式会社 | Nonvolatile memory, memory inspection method |
CA2277717C (en) | 1999-07-12 | 2006-12-05 | Mosaid Technologies Incorporated | Circuit and method for multiple match detection in content addressable memories |
US7079422B1 (en) | 2000-04-25 | 2006-07-18 | Samsung Electronics Co., Ltd. | Periodic refresh operations for non-volatile multiple-bit-per-cell memory |
US6856568B1 (en) | 2000-04-25 | 2005-02-15 | Multi Level Memory Technology | Refresh operations that change address mappings in a non-volatile memory |
US6396744B1 (en) | 2000-04-25 | 2002-05-28 | Multi Level Memory Technology | Flash memory with dynamic refresh |
US6940772B1 (en) | 2002-03-18 | 2005-09-06 | T-Ram, Inc | Reference cells for TCCT based memory cells |
US7123508B1 (en) | 2002-03-18 | 2006-10-17 | T-Ram, Inc. | Reference cells for TCCT based memory cells |
EP1416496A1 (en) * | 2002-11-04 | 2004-05-06 | Dialog Semiconductor GmbH | Multiple level ram device |
JP4130634B2 (en) * | 2004-01-20 | 2008-08-06 | 松下電器産業株式会社 | Semiconductor device |
US7196946B2 (en) * | 2005-04-05 | 2007-03-27 | Sandisk Corporation | Compensating for coupling in non-volatile storage |
US7196928B2 (en) * | 2005-04-05 | 2007-03-27 | Sandisk Corporation | Compensating for coupling during read operations of non-volatile memory |
US7187585B2 (en) * | 2005-04-05 | 2007-03-06 | Sandisk Corporation | Read operation for non-volatile storage that includes compensation for coupling |
US7948803B2 (en) | 2006-03-16 | 2011-05-24 | Freescale Semiconductor, Inc. | Non-volatile memory device and a programmable voltage reference for a non-volatile memory device |
JP2009529755A (en) * | 2006-03-16 | 2009-08-20 | フリースケール セミコンダクター インコーポレイテッド | Bit line current generator for nonvolatile memory array and nonvolatile memory array |
US7952937B2 (en) | 2006-03-16 | 2011-05-31 | Freescale Semiconductor, Inc. | Wordline driver for a non-volatile memory device, a non-volatile memory device and method |
ITTO20070109A1 (en) * | 2007-02-14 | 2008-08-15 | St Microelectronics Srl | CIRCUIT AND READING METHOD FOR A NON-VOLATILE MEMORY DEVICE BASED ON THE ADAPTATIVE GENERATION OF AN ELECTRIC REFERENCE SIZE |
US8255623B2 (en) * | 2007-09-24 | 2012-08-28 | Nvidia Corporation | Ordered storage structure providing enhanced access to stored items |
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1995
- 1995-03-23 EP EP95830110A patent/EP0734024B1/en not_active Expired - Lifetime
- 1995-03-23 DE DE69514783T patent/DE69514783T2/en not_active Expired - Fee Related
-
1996
- 1996-01-29 US US08/592,939 patent/US5673221A/en not_active Ceased
- 1996-03-22 JP JP6671096A patent/JP2857649B2/en not_active Expired - Lifetime
-
1999
- 1999-09-30 US US09/410,164 patent/USRE38166E1/en not_active Expired - Lifetime
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Cited By (3)
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---|---|---|---|---|
US20070277141A1 (en) * | 2003-05-21 | 2007-11-29 | Tobias Buehler | Integrated Circuit Arrangement, and Method for Programming an Integrated Circuit Arrangement |
US7724167B2 (en) * | 2003-05-21 | 2010-05-25 | Austriamicrosystems Ag | Integrated circuit arrangement, and method for programming an integrated circuit arrangement |
US20060140010A1 (en) * | 2004-12-29 | 2006-06-29 | Lorenzo Bedarida | Method and system for reducing soft-writing in a multi-level flash memory |
Also Published As
Publication number | Publication date |
---|---|
JPH08339692A (en) | 1996-12-24 |
US5673221A (en) | 1997-09-30 |
EP0734024A1 (en) | 1996-09-25 |
EP0734024B1 (en) | 2000-01-26 |
JP2857649B2 (en) | 1999-02-17 |
DE69514783T2 (en) | 2000-06-08 |
DE69514783D1 (en) | 2000-03-02 |
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