|Publication number||USRE38685 E1|
|Application number||US 10/164,354|
|Publication date||Jan 11, 2005|
|Filing date||Jun 5, 2002|
|Priority date||Aug 24, 1998|
|Also published as||US6072729|
|Publication number||10164354, 164354, US RE38685 E1, US RE38685E1, US-E1-RE38685, USRE38685 E1, USRE38685E1|
|Inventors||Stephen L. Casper|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Referenced by (15), Classifications (18), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates generally to integrated circuits and, more particularly, to a data-output driver circuit having an improved slew-rate characteristic.
Today's engineers often design electronic systems so that they will function properly when a component from one manufacturer is replaced with a like component from another manufacturer. For example, most personal computers will function properly with a Pentium® processor from Intel or a K6® processor from Advanced Micro Devices (AMD). This interchangeability of components provides many advantages. For example, because more than one manufacturer can source a particular component, competition among manufacturers is increased, thus lowering the cost per component. Furthermore, if one manufacturer runs out of a particular component, the system manufacturer can obtain like components from another manufacturer and thus avoid a production delay. Additionally, for systems such as personal computers, such interchangeability provides greater flexibility to a customer by allowing him to select components that meet his quality, performance, and cost expectations.
To allow component interchangeability, a system designer often specifies the operating characteristics and parameters that a component must meet in order to function in a particular system. Thus, if a manufacturer wants to design a component of the system, then it must design the component to meet these system specifications.
Table 1 at the end of the specification is a section of Intel's PC-100 specification for Synchronous Dynamic Random Access Memories (SDRAMs) designed for use on Intel's computer boards. Specifically, this section specifies the acceptable ranges of the rise- and fall-time slew rates (Volts/nanosecond) into 50-ohm and 50 picofarad (pf) loads, respectively, and the push (switching current high) and pull (switching current low) drive currents for an SDRAM's data output drivers. These drivers, which are called DQ drivers, are the circuits that drive the data onto the data bus during a read cycle. Unfortunately, conventional DQ drivers often cannot meet all the requirements of the PC-100 specification.
Unfortunately, although the DQ driver 10 meets most of the PC-100 specifications in Table 1, it may not meet all of them. In operation, the boost circuit 14 controls the pull-up transistor 16 such that the driver 10 does generate the rising slew rates within the specified ranges when a 50-ohm load and a 50 pf load are respectively connected between the output terminal 11 and VSS. The driver 10 also meets the push drive-current specification, which means that the transistor 16 sources current within the specified range when the output terminal 11 is at 1.65 V. But unfortunately, although the transistor 20 drives the transistor 24 such that driver 10 meets the pull drive-current specification, the driver 10 may not meet one of the 50-ohm and 50 pf falling slew-rate specifications as discussed below.
An embodiment of the driver 10 that meets one but misses the other falling slew-rate specification will now be discussed with reference to
The problem with this embodiment of the driver 10 is that the gain of the transistor 20, which is set high enough for the driver 10 to meet the 50 pf falling slew-rate specification, causes the driver 10 to exceed the 50-ohm falling slew-rate specification. Unfortunately, reducing the gain of the transistor 20 so that the driver 10 meets the 50-ohm falling slew-rate specification causes the driver 10 to undershoot the 50 pf falling slew-rate specification.
In one aspect of the invention, a drive circuit includes drive input and output terminals, a supply terminal, a drive transistor, and a drive-control circuit. The drive transistor includes a control terminal, a first transistor terminal coupled to the drive output terminal, and a second transistor terminal coupled to the supply terminal. The drive-control circuit has an input terminal coupled to the drive input terminal and has an output terminal coupled to the control terminal of the drive transistor. The drive-control circuit generates on the control terminal of the drive transistor a signal level that changes at a first rate during a first time period and changes at a second, higher rate during a second time period following the first time period.
One can adjust the first and second rates and the first and second time periods such that the drive circuit meets both the 50-ohm and 50 pf falling slew rates specified in the PC-100 specification.
More specifically, the drive-control circuit 32 includes a first drive-control stage 36, which during a first time period generates a first portion of the control signal having a first slope characteristic on the gate of the transistor 24 via a line 38. The circuit 32 also includes a second drive-control stage 40, which generates a second portion of the control signal having a second slope characteristic on the line 38 during a second time period that follows the first time period. Additionally, a switch 42 may be included to cut off power to a portion of the second stage 40 when the input data signal transitions to logic 1. This significantly speeds up the turn-off time of the second stage 40. In one embodiment, the switch 42 is a PMOS transistor.
In one embodiment, the first stage 36 is an inverter that includes a PMOS pull-up transistor 44 and an NMOS pull-down transistor 46. The transistor 44 is sized such that during the first time period when DATA IN is logic 0, the transistor 44 causes a control voltage on the line 38 to rise according to a first rate characteristic. The second stage 40 includes a second inverter 48, which includes a PMOS pull-up transistor 50 and an NMOS pull-down transistor 52, and a PMOS transistor 54 having its gate coupled to the output of the inverter 48. During the second time period when DATA IN is logic 0, the inverter 48 controls the transistor 54 such that it causes the control voltage on the line 38 to rise according to a second rate characteristic, which in one embodiment is steeper than the first rate characteristic. As stated above, by properly adjusting the first and second rate characteristics during the respective first and second time periods, the drive-control circuit 32 controls the transistor 24 such that the drive circuit 30 meets the PC-100 50 pf and 50-ohm falling slew-rate specifications. For example, in one embodiment as discussed below, setting the gain of the transistor 54 to be two or more times the gain of the transistor 44 allows the drive circuit 30 to meet all of the PC-100 specifications.
In operation, referring to
Still referring to
It is noted that
In light of the above description, the general theory of operation of the circuit 30 of
The physical characteristics of the driver 30, such as the sizes of the transistors, may change depending upon the manufacturing process and the values of VDD and VSS to be used. However, one can vary PRT, POT, PTRIP, T1, and T2 by varying the gains of the transistors 44 and 54 and the trip point of the inverter 48 such that no matter what manufacturing process is used, the circuit 30 still fully meets the requirements of the PC-100 specification in Table 1.
A data input/output (I/O) circuit 146 includes a plurality of input buffers 148. During a write cycle, the buffers 148 receive and store data from the DATA bus, and the read/write circuits 142a and 142b provide the stored data to the memory banks 140a and 140b, respectively. The data I/O circuit 146 also includes a plurality of output drivers 150, typically one for each line of the DATA bus. These drivers 150 each include a drive circuit 30 of FIG. 4. During a read cycle, the read/write circuits 142a and 142b provide data from the memory banks 140a and 140b, respectively, to the drivers 150, which in turn provide this data to the DATA bus.
A refresh counter 152 stores the address of the row of memory cells to be refreshed either during a conventional auto-refresh mode or self-refresh mode. After the row is refreshed, a refresh controller 154 updates the address in the refresh counter 152, typically by either incrementing or decrementing the contents of the refresh counter 152 by one. Although shown separately, the refresh controller 154 may be part of the control logic 134 in other embodiments of the memory circuit 130.
The memory circuit 130 may also include an optional charge pump 156, which steps up the power-supply voltage VDD to the boost voltage VBOOST, which is used by the boost circuit 14 of
From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
SDRAM DO BUFFER OUTPUT
1, 2, 3
1, 2, 3
1. Output rise and fall time must be guaranteed across VDD, process and temperature range.
2. rise time specification based on 0 pf plus 50 ohms to VSS, use these values to design to.
3. Fall time specification based on 0 pf plus 50 ohms to VDD, use these values to design to.
4. Measured into 50 pf only, use these values to characterize to.
5. All measurements done with respect to VSS.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7262637||Mar 22, 2005||Aug 28, 2007||Micron Technology, Inc.||Output buffer and method having a supply voltage insensitive slew rate|
|US7528624||Jul 26, 2007||May 5, 2009||Micron Technology, Inc.||Output buffer and method having a supply voltage insensitive slew rate|
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|US7902875||Nov 3, 2006||Mar 8, 2011||Micron Technology, Inc.||Output slew rate control|
|US8138794||Mar 20, 2012||Micron Technology, Inc.||Output slew rate control|
|US8698520||Mar 12, 2012||Apr 15, 2014||Micron Technology, Inc.||Output slew rate control|
|US9231572||Apr 15, 2014||Jan 5, 2016||Micron Technology, Inc.||Output slew rate control|
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|US20080122510 *||Nov 3, 2006||May 29, 2008||Micron Technology, Inc.||Output slew rate control|
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|US20090201046 *||Apr 22, 2009||Aug 13, 2009||Dong Pan||Output buffer and method having a supply voltage insensitive slew rate|
|US20110148493 *||Jun 23, 2011||Micron Technology, Inc.||Output slew rate control|
|U.S. Classification||365/158, 257/295, 365/45, 365/170|
|International Classification||G11C7/10, G11C11/00, G11C29/02|
|Cooperative Classification||G11C29/50012, G11C7/1069, G11C29/02, G11C29/022, G11C7/1051, G11C2207/2254|
|European Classification||G11C29/02B, G11C29/50C, G11C7/10R9, G11C29/02, G11C7/10R|
|Sep 21, 2007||FPAY||Fee payment|
Year of fee payment: 8
|Sep 19, 2011||FPAY||Fee payment|
Year of fee payment: 12