|Publication number||USRE38734 E1|
|Application number||US 10/259,859|
|Publication date||May 17, 2005|
|Filing date||Sep 30, 2002|
|Priority date||Jan 17, 1996|
|Also published as||EP0785627A2, EP0785627A3, US5777506|
|Publication number||10259859, 259859, US RE38734 E1, US RE38734E1, US-E1-RE38734, USRE38734 E1, USRE38734E1|
|Inventors||Kazuhiro Kurachi, Masanori Yamamoto|
|Original Assignee||Mitsubishi Denki Kabushiki Kaisha|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Non-Patent Citations (1), Classifications (19), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a semiconductor switching apparatus used for e.g., a power converter, and to a method of controlling a semiconductor switching element.
2. Description of the Background Art
To suppress the rate of rise of voltage (dVAKP/dt) and peak value of the anode-cathode voltage VAKP, a snubber circuit is generally used. The snubber circuit herein has a configuration where a snubber capacitor CS and a snubber diode DS are connected in parallel to the GTO 3P, and a snubber resistor RS is connected in parallel to the snubber diode DS in order to discharge the electric charges accumulated in the snubber capacitor CS at a turn-off.
An inductance 1P suppresses the rate of rise of anode current (dIAP/dt) which flows when the GTO 3P is turned on to not more than 1000 A/μs, and a circulating diode 2P connected in parallel to the inductance 1P circulates energy generated in the inductance 1P when the GTO 3P is turned off.
Furthermore, an inductance LS is a total inductance of the snubber circuit.
The rate of rise of the anode-cathode voltage (dVAKP/dt) constantly changes after the spike voltage VDSP is generated. The anode current IAP continues to flow after time dP3 and this is referred to as a “tail current”. The tail current reaches the maximum at time tP4. The tail current and the anode-cathode voltage VAKP produce further power dissipation. The anode-cathode voltage VAKP reaches a peak voltage at time tP5. After that, the anode-cathode voltage VAKP reaches a power voltage (or main line voltage) VDD.
To suppress the rate of rise of voltage (dVAKP/dt), the above-discussed snubber capacitor CS is required. The snubber capacitor CS has a capacitance value IAP/(dVAKP/dt) which is generally selected so as to satisfy the relation dVAKP/dt≦f 1000 V/μs (the dVAKP/dt is calculated by the following equation: dVAKP/dt≈IAP/CS).
FIGS., 18 and 19 show a GTO element (or GTO device) 20P, an internal inductance 4PL of the gate driver 4P, an external gate lead (gate drawing line) 21P and an external cathode lead (cathode drawing line) 22P both of which are formed of coaxial shield leads or twisted lead lines. A gate terminal 25P of the GTO element 20P and an end of the external gate lead 21P are joined to a metal joining member (or terminal) 23P by soldering to be fixed with each other. Similarly, a cathode terminal 26P of the GTO element 20P and an end of the external cathode lead 22P are joined to a metal joining member 24P by soldering to be fixed with each other. Thus, both the terminals 25P and 26P are connected to the gate driver 4P through the leads 21P and 22P, respectively.
Stacked electrodes 27Pa and 27Pb apply pressure onto the GTO element 20P.
A semiconductor substrate (or wafer) 28P is provided with segments of the GTO, a gate electrode 29Pa made of Al (Aluminum) is formed on an outermost peripheral portion of an upper surface of the semiconductor substrate 28P, and a cathode electrode 29Pb is formed inside the gate electrode 29Pa on the upper surface, correspondingly to the segment. A cathode strain relieving plate (or metal plate) 30P and a cathode post electrode 31P are stacked in this order on an upper surface of the cathode electrode 29Pb provided on the upper surface of the semiconductor substrate 28P. An anode strain relieving plate 32P and an anode post electrode 33P are stacked in this order on a surface of an anode electrode (not shown) provided on a bottom surface of the semiconductor substrate 28P (opposite to the cathode electrode 29Pb).
A ring-shaped gate electrode 34P is in contact with an upper surface of the gate electrode 29Pa on the semiconductor substrate 28P, and a belleville spring 35P pushes the ring-shaped gate electrode 34P against the gate electrode 29Pa through an annular insulator 36P. An insulating sheet 37P is provided to isolate the ring-shaped gate electrode 34P from the cathode strain relieving plate 30P and the post electrode 31P. A gate lead 38P has one end which is fitted into the ring-shaped gate electrode 34P by brazing or welding and the other end which is electrically connected to the gate terminal 25P. A first flange 39P has one end which is fitted into the cathode post electrode 31P and the other end which serves as a cathode terminal 26P, and a second flange 40P has one end which is fitted into the anode post electrode 33P. An insulating tube (or ceramic) 41P has an opening whose internal surface is provided with the gate terminal 25P, and a projection 42P. End portions 43Pa and 43Pb of the insulating tube 41P are protruded through its upper and lower surfaces to be fitted airtightly to the first and second flanges 39P and 40P respectively, thereby ensuring a closed structure of the GTO element 20P.
The above-discussed background-art semiconductor switching apparatus has the following two problems.
(1) As shown in
(2) The second problem is caused by the snubber circuit, in particular, the snubber capacitor. Specifically discussing, the electric charges which are charged up in the snubber capacitor CS (see
Thus, when the GTO 3P is connected to the snubber resistor which has the above capacitance of power consumption, the power generated by the snubber resistor is out of the power to be transmitted as a loss to degrade the efficiency, and further the necessity for the cooling device arises. That is a hindrance to simplification and size-reduction of the whole apparatus.
The present invention is directed to a semiconductor switching apparatus. According to a first aspect of the present invention, the semiconductor switching apparatus comprises: a semiconductor switching element having first, second and third electrodes, for carrying a main current which flows into the first electrode, from the first electrode direct to the second electrode when brought into an on-state in response to a turn-on control current applied to the third electrode; and driving control means connected between the third and second electrodes, for producing the turn-on control current and applying it to the third electrode, in which the main current is entirely commutated to the driving control means through the first to third electrodes in a direction reverse to the turn-on control current at a turn-off.
Preferably, a turn-off gain is determined not more than 1 at the turn-off, which is represented by the absolute value of the ratio of the main current to a current which flows in the direction reverse to the turn-on control current.
Preferably, an inductance existing in a path from the third electrode through the driving control means and the second electrode to the third electrode is determined a value required to obtain the turn-off gain of not more than 1.
In a second aspect of the present invention, a semiconductor switching apparatus comprises: a semiconductor switching element; and an interconnection path for transmitting a turn-on control current necessary to turn the semiconductor switching element on, in which the interconnection path is disposed so that a main current flowing into the semiconductor switching element in an on-state is entirely commutated to the interconnection path at a turn-off.
The present invention is also directed to a method of controlling a semiconductor switching element which has first, second and third electrodes. According to a third aspect of the present invention, the method comprises steps of: providing a driving circuit for generating a turn-on control current for turning on the semiconductor switching element; applying said turn-on control current to the third electrode to bring the semiconductor switching element into an on-state; and commutating a main current flowing into the first electrode entirely towards the second electrode through the driving circuit in a direction reverse to the turn-on control current to turn the semiconductor switching element off.
The first object of the present invention is to prevent the dissipation from locally concentrating on part of semiconductor switching elements within the semiconductor wafer. That avoids the failure of the device, to thereby enhance the reliability of the apparatus.
The second object of the present invention is to prevent or markedly suppress the dissipation caused by the snubber circuit in the background art. That ensures size-reduction, simplification, cost-reduction and high efficiency of the apparatus.
The third object of the present invention is to eliminate the necessity for a circuit to suppress a rise in the voltage between the first and second electrodes, such as a snubber circuit. That ensures size-reduction of the apparatus and high efficiency.
The fourth object of the present invention is to propose a new and practical turnoff method of the semiconductor switching element.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
A semiconductor switching apparatus or a semiconductor switching element is applied for various types of power converters, such as a power converter on traction, an SVG (Static Var Generator) and an industrial power converter.
The point of the proposed new method of controlling the semiconductor switching element (or switching device) lies in that a main current flowing in the semiconductor switching element in an on-state is entirely commutated to a driving circuit, to thereby bring the semiconductor switching element into a turn-off state.
A gate turn-off thyristor (hereinafter referred to as “GTO”) will be discussed as an example of the semiconductor switching element. In this case, the first, second and third electrodes of the GTO correspond to an anode electrode, a cathode electrode and a gate electrode, respectively. The semiconductor switching element is not limited to the GTO of a quadruple layered structure, but may be a transistor of a triple layered structure. In the case of a transistor, the first, second and third electrodes correspond to a collector electrode, an emitter electrode and a base electrode in an NPN transistor and correspond to an emitter electrode, a collector electrode and a base electrode in a PNP transistor.
<The First Preferred Embodiment>
The gate driver 4 produces a turn-on control current IG for turning the GTO 3 on and applies the current IG to the gate electrode 3G through an interconnection path or a line L1. In response to that, the GTO 3 is turned on. Further,
On the other hand, an inductance 1 suppress the rate of rise (dIAKP/dt) of the main current IA which flows when the GTO 3 is turned on, and a circulating diode 2 circulates energy generated in the inductance 1 when the GTO 3 is turned off.
A peak voltage suppressing circuit 5 is connected between the node 11 of the anode electrode 3A and a node 12 of the cathode electrode 3K in parallel to the GTO 3 and suppresses only a peak voltage when the GTO 3 is turned off. The circuit 5 has a function of holding or clamping the voltage VAK to a prescribed voltage value which is determined according to a voltage blocking capability of the GTO 3 at its turn-off for a prescribed period.
Although a gate reverse current IGQ has been shunted from the main current IA and flows into the gate driver 4 in the background art, the main current IA is entirely carried (or commutated) to the node 12 through the gate driver 4 as the gate reverse current IGQ at a turn-off, with the absolute value of the rate of rise of the gate reverse current dIGQ/dt determined as large as possible (ideally, |dIGQ/dt| is infinity ∞), in the present invention. In other words, with the turn-off gain G (=IA/IGQ) represented by the absolute value of the ratio of the main current IA to the gate reverse current IGQ is determined not more than 1 (G≦1) at 1 (G=1 ), the main current IA is entirely commutated in a direction reverse to the turn-on control current IG through the gate driver 4 to the node 12, to turn the GTO 3 off. Then, the cathode current IK flowing direct from the anode electrode 3A towards the cathode electrode 3K inside the GTO 3 immediately stops flowing. In this meaning, the present invention achieves “commutation of the main current IA”, not “shunt of the main current IA”.
The rate of rise of gate current dIGQ/dt can be changed in response to the relation between the power supply voltage value VGD of the driving power supply 4a of the gate driver 4 and the inductance value of a loop R1. Accordingly, if the rate of rise |dIGQ/dt| is determined extremely large as near infinity ∞ as possible by appropriately setting the values of the driving power supply (main power supply) 4a and the loop R1, the main current IA can be entirely commutated towards the gate driver 4 in extremely short time.
On the other hand, it is not easy to achieve commutation of the gate reverse current IGQ by the gate driver 4 alone because of limitation of the possible power supply voltage VGD of the gate driver 4. It is practically possible, however, to determine the internal inductance value of the loop R1 so as to achieve the required absolute value of the rate of rise dIGQ/dt for the gate turn-off gain G of not more than 1, by setting the driving power supply voltage VGD to a practically possible value.
Then, it is required to reduce the value of the internal floating inductance in the loop or path R1 consisting of the line L1 from the gate electrode 3G to the gate driver 4, the gate driver 4, and a line L2 from the gate driver 4 to the cathode electrode 3K through the node 13 to achieve the desired value for the gate turn-off gain G of not more than 1.
Furthermore, the gate driver 4 should be so determined (or designed) as to have a capacitance enough to carry the gate reverse current IGQ not less than the main current IA.
For example, when the power supply voltage VGD of the main power supply 4a of the gate driver 4 is determined 20 V and the absolute value of the rate of rise of gate current |dIGQ/dt| is determined 8000 A/μs, it is desirable that the inductance value of the loop R1 should be not more than 2.5 nH and the internal inductance value of the gate driver 4 should be not more than 1 nH.
In the above-discussed gate driver circuit 4, when a control signal 62 is externally applied, a noise-ut circuit 59 cuts noise components out of the control signal 62, and a turn-on signal generation circuit 60 and a turn-off signal generation circuit 61, receiving the noise-cut control signal, generate a turn-on signal 63 and a turn-off signal 64 and supply the corresponding driving circuits 56 and 57 with the signals 63 and 64, respectively.
Operations of the driving circuits 56 and 57 which receive the signals 63 and 64 respectively are as follows. At time t01, the driving circuit 56 generates a signal which can drive the transistor Tr1 and supplies the base of transistor Tr1 with the signal. Since the capacitors C1 and C2 are charged by the secondary power supplies 51 and 53 respectively at this time, the turn-on high gate current IG1 is carried from the capacitor C1 to the GTO 3 through the transistor Tr1. At time t02, the driving circuit 56 stops supplying the base current of the transistor Tr1, and in turn generates a base current which can drive the transistor Tr2 and supplies the transistor Tr2 with the base current. The transistor Tr1 is thereby turned off and the transistor Tr2 is instead turned on. The turn-on stationary gate current IG2 is carried from the capacitor C1 to the GTO 3 through the transistor Tr2.
At time t1, the driving circuit 56 stops supplying the base current of the transistor Tr2, and the driving circuit 57 generates a base current which can turn the transistor Tr3 on in response to the signal 64 and supplies the base of transistor Tr3 with the base current. The transistor Tr2 is thereby turned off and the transistor Tr3 is instead turned on. The electric charges accumulated in the capacitors C2 are discharged through the transistor Tr3, and accordingly the turn-off gate current IGQ flows from the gate of the GTO 3 to the node 13 of the cathode electrode 3K of the GTO 3 through the transistor Tr3. The turn-off gate current IQ becomes the value equivalent to the absolute value of the main current IA or more in extremely short time, and in contrast the cathode current is reduced to 0 in extremely short time.
To achieve the rate of rise dIGQ/dt for the turn-off gain G of not more than 1, it is required to reduce the inductance value of the whole loop R1 including the interconnection paths of the gate driver 4, as discussed above. That is desirably achieved by improvements of system parts constituting the interconnection of the GTO elements and the package structure.
The background-art GTO 3P has the package structure as shown in
Through a study of the package structure of the GTO elements from the above viewpoint and improvements thereof, the present invention provides a pressure-contact type semiconductor device having a structure as discussed below.
A cathode strain relieving plate (or cathode metal plate) 30 and a cathode post electrode 31 are stacked (or assembled) in this order on an upper surface of the cathode electrode 29b provided on the upper surface of the semiconductor substrate 28. An anode strain relieving plate 32 and an anode post electrode 33 are stacked in this order on a surface of an anode electrode (not shown) provided on a bottom surface of the semiconductor substrate 28 (opposite to the cathode electrode 29b). A ring-shaped gate electrode 34 is in contact with an upper surface of the gate electrode 29a on the semiconductor substrate 28, and a ring-shaped gate terminal 38 is formed of an annular metal plate, having an inner peripheral plane 25 which is located in contact with the ring-shaped gate electrode 34 so as to be slidable thereover. A belleville spring or wave spring 35 which is an elastic body pushes the ring-shaped gate terminal 38 and the ring-shaped gate electrode 34 against the gate electrode 29a through an annular insulator 36. An insulating sheet (insulating body) 37 is provided to isolate the ring-shaped gate electrode 34 from the cathode strain relieving plate 30 and the post electrode 31. A first flange 26 has one end fitted into the cathode post electrode 31, and a second flange 40 has one end fitted into the anode post electrode 33. An insulating tube 41 made of ceramic and the like is separated into upper and lower portions with the ring-shaped gate terminal 38 interposed therebetween and has a projection 42. An outer peripheral portion 23 of the ring-shaped gate terminal 38 is projected outside the insulating tube (or ceramic) 41 and provided with a plurality of mounting holes 21 at predetermined spaces inside an outer end 38E of the ring-shaped gate terminal 38. An end portion 43a of the insulating tube 41 protruded through its upper surface is fitted airtightly to the other end 26E of the first flange 26 and another end portion 43b of the insulating tube 41 protruded through its lower surface is fitted airtightly to the other end of the second flange 40, thereby ensuring a closed package structure of the GTO element 20. Furthermore, inert gas is substituted for the inside of the GTO element 20.
The substrate 70 has two circuit pattern substrates which are opposed to each other with the insulator interposed therebetween. Specifically, the substrate 70 has a gate lead substrate 72, a cathode lead substrate 73 and an insulator 74 for making isolation between the substrates 72 and 73. Such multilayered substrate structure allows reduction of the internal inductance of the gate driver 4. The GTO element 20 is connected to the gate driver body 4C with screws 75 and 76, or by welding, caulking and the like.
As discussed above, the airtight package (20) of the GTO 3 has the ring-shaped or disk-shaped gate electrode 38 extending from a side of the semiconductor substrate on which the internal gate electrode 29a is formed towards the gate driver body 4C, and can be connected to the gate driver 4 by joining and fitting the outer peripheral portion of the ring-shaped gate electrode 38 direct to the substrate 70 which extends from the gate driver body 4C through the mounting holes 21A. Thus, this connection between the GTO 3 and the gate driver 4 needs no lead line. Therefore, all of the problems in the background-art structure are resolved. Specifically discussing, the inductance and resistance produced by joints between the internal gate lead portion of the GTO element and the gate and cathode terminals are substantially reduced by using the above gate lead whose drawing portion is of disk-like structure, and voltage drop of the inductance and resistance by the joint between the external gate lead line and the gate driver is substantially reduced by connecting the disk-like gate lead portion or the whole gate electrode 38 direct to the gate current conducting substrate 70. Moreover, the problem of the inductance of the external gate lead line which conventionally accounts for 90% of all the inductance of the loop R1 is resolved in the present invention since no gate lead line is used.
Thus, it becomes possible to reduce the internal inductance of the GTO element 20 (3) and the internal inductance of the gate driver 4. In addition to the improvements, with the above invented connection between the GTO element 20 and gate driver 4 (see FIG. 7), the rate of rise dIGQ/dt for the turn-off of the GTO 3 under the condition that the turn-off gain G≦1 is practically achieved.
Furthermore, the gate current may be drawn in two or four diagonal directions, or more directions, by using a substrate 70A as shown in the plan view of FIG. 8.
An operation of the semiconductor switching apparatus having the above circuit configuration and mechanism will be discussed, referring to
A current difference ΔIGQ of
When the NPN transistor 81 of
When a voltage blocking function (or voltage blocking capability) of the PNP transistor 80 begins to recover (at time T3), the anode-cathode voltage VAK of
The peak voltage (or surge voltage) VP of
As discussed above, the GTO 3 is turned off, with the rate of rise dIGQ/dt of
In contrast, no cathode current flows and the main current IA is entirely commutated into the path towards the gate driver 4 at the turn-off in the present invention, as shown in FIG. 13. With However, during the initial stage of the communication with generation of the recovery current, the absolute value of the gate reverse current IGQ is equivalent to the sum of the absolute value of the main current IA and the absolute value of the recovery current, and therefore the relation |IGQ|≧|IA| holds (|IGQP|<|IA| in the background art).
Thus, in the present invention, the relation |the anode current IA≦ =| the gate reverse current IGQ| is true while the GTO 3 is in a turn-off mode. With the new gate commutation system, since the cathode current IK=0 when the GTO 3 is turned off, and specifically, no cathode current flows in the cathode side inside the GTO 3, it is possible to absolutely prevent the current crowding from occurring locally in the cathode side, which has been a cause of turn-off failure. Therefore, there is less possibility of breakdown of the apparatus due to the turn-off failure in the present invention, and substantially high reliability of the apparatus is achieved. That is the core of the present invention and this advantageous effect is not achieved by combination of background-art techniques disclosed in the above documents.
In addition to that, since the peak voltage suppressing circuit 5 which suppresses the rise in the anode-cathode voltage VAK and cuts the surge voltage is provided to cut the spike voltage, no spike voltage is developed. That eliminates the necessity for the snubber capacitor CS which has been conventionally required to discharge the electric charges which arc accumulated at the turn-off. Thus, since the snubber circuit which has been an essential of the background art is not needed, it is possible to achieve size-reduction, simplification, cost-reduction and which efficiency of the apparatus.
<The Second Preferred Embodiment>
Operations of the semiconductor switching apparatus 10A having the above configuration and the GTO 3 will be discussed, referring to the observed waveforms of FIG. 15.
The operation of the GTO 3 in this case is the same as that of the first preferred embodiment, except an operation of suppressing the peak voltage of the anode-cathode voltage VAK. The observed waveforms of
The above operation will be discussed, referring to FIG. 15. Until the anode-cathode voltage VAK reaches the power supply voltage VDD, the capacitor 8 does not work, and the rate of rise dIGQ/dt in this period (t2−t1) depends on the capability of the GTO 3 (at this time, the main current IA is entirely commutated towards the gate driver 4). When the anode-cathode voltage VAK reaches the power supply voltage VDD and the anode current IA starts falling (at time t2), the main current flowing into the node 11 starts flowing towards the capacitor 8 through the diode 6, i.e., into the bypass line BL. At this time, spike voltage VDSP is generated by the rate of rise di/dt of the bypass current i which flows into the bypass line BL and a floating inductance (Ln) in a closed circuit, or a first loop R2, consisting of the GTO 3, the diode 6 and the capacitor 8. This is the spike voltage VDSP as shown in
Furthermore, the overcharged electric charges absorbed in the capacitor 8 are discharged through the resistor 7 towards the power supply 9 until the next turn-off. On the other hand, the voltage, or electric charges which remain in the capacitor 8 even when the GTO 3 is turned on are blocked discharging by the diode 6. Therefore, the capacitor 8 is always charged with a voltage equivalent to or higher than the power supply voltage VDD.
Furthermore, the peak voltage VP from time t4 to t5 is based on the electric energy produced by a floating inductance (or main inductance) LA2 and the capacitance value of the capacitor 8.
Thus, as to the energy accumulated in the peak voltage suppressing circuit or the capacitor 8 of the protective circuit in the semiconductor switching apparatus 10A, only the overcharged electric charges are discharged, in contrast to the background art where the electric charges in the snubber capacitor are entirely discharged to become 0 by the snubber resistor, and therefore the present invention makes it possible to substantially reduce the dissipation of the snubber circuit which has been a problem in the background art. Furthermore, in the semiconductor switching apparatus 10A, the protective circuit is simply configured of the same materials as those used for the snubber circuit in the background art, specifically by connecting the wire of resistor used for the background-art snubber resistor as the interconnection path R4 of the present invention direct to the node 14 of the power supply 9. Thus, advantageously, the semiconductor switching apparatus is practically achieved with high probability since it utilizes the background-art snubber circuit to sufficiently reduce the dissipation Naturally, the semiconductor switching apparatus 10A can completely block the breakdown of the GTO 3 at the turn-off, like the semiconductor switching apparatus 10 of FIG. 1.
While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5237225 *||Nov 29, 1991||Aug 17, 1993||Asea Brown Boveri Ltd.||Switching arrangement for an rf gto|
|US5493247 *||Oct 30, 1992||Feb 20, 1996||Asea Brown Boveri Ltd.||Gate circuit for hard driven GTO|
|1||Conference Record of the 1986 IEEE Industry Applications Society Annual Meeting Part I Papers Presented at the Twenty-First Annual Meeting, Radisson Hotel, Denver, CO Sep. 28-Oct. 3, Sponsored by the IEEE Industry Applications Society.|
|U.S. Classification||327/440, 327/438, 327/582|
|International Classification||H02M1/06, H01L29/744, H03K17/0814, H03K17/16, H03K17/0812, H03K17/732, H01L29/74, H03K17/72|
|Cooperative Classification||H03K17/732, H03K17/16, H03K17/08124, H03K17/08144|
|European Classification||H03K17/0812C, H03K17/16, H03K17/0814C, H03K17/732|
|Dec 16, 2005||FPAY||Fee payment|
Year of fee payment: 8
|Dec 9, 2009||FPAY||Fee payment|
Year of fee payment: 12