|Publication number||USRE38820 E1|
|Application number||US 09/285,303|
|Publication date||Oct 11, 2005|
|Filing date||Jul 2, 1998|
|Priority date||Dec 21, 1994|
|Also published as||US5533018|
|Publication number||09285303, 285303, US RE38820 E1, US RE38820E1, US-E1-RE38820, USRE38820 E1, USRE38820E1|
|Inventors||Gregory L. DeJager, Erik R. Swenson|
|Original Assignee||Negotiated Data Solutions Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (99), Non-Patent Citations (36), Referenced by (3), Classifications (15), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The microfiche appendix, which is a part of the present disclosure, entails one sheet of microfiche having a total of ninety-two (92) frames. The microfiche appendix contains RTL code and schematics of a specific embodiment of an integrated circuit in accordance with the present invention. A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent files or records, but otherwise reserves all copyright rights whatsoever.
This invention relates to isochronous networks.
Ethernet is a well known network protocol. See the IEEE specification 802.3 (the subject matter of which is incorporated herein by reference) for further background information on Ethernet. Ethernet is well suited for transferring large packets of information at spaced intervals. Information may, for example, be accumulated into a large packet and then sent in a relatively large packet from one Ethernet node to another Ethernet node. Ethernet can therefore be said to be a “bursty” network protocol.
Some types of information, such as the information in a typical telephone conversation, do not lend themselves to being accumulated over time and then being transmitted as a single large packet. In a telephone conversation, speech information should be passed from speaker to listener without significant delay because the listener may use that speech information to formulate a response. Accordingly, there is not time for large packets of information to be accumulated. Frequent transmissions of small packets of information over the network is required. Ethernet is not well suited to this “nonbursty” type of information transfer.
There are, however, communication protocols (called isochronous protocols) which are suited for communication of such “nonbursty” information. Circuit switching and time division multiplexing (TDM) techniques are employed to divide a communication medium into a number of consecutive frames, each frame including a number of time slots. A first telephone conversation may, for example, be allocated a first slot of each frame whereas a second telephone conversation may be allocated a second slot of each frame. Because telephone information for each conversation is received each frame, the “nonbursty” information of the telephone conversations is communicated without significant delay.
Isochronous networks may also be made to carry “bursty” information. Telephone companies use an information framing protocol known as “HDLC” to frame information (“bursty” and/or “nonbursty”) for isochronous communication over a standard digital telephone line (an example of which is Primary Rate ISDN or “PRI”). HDLC is part of a more encompassing protocol called “X.25” See the document ISO/IEC 3309, 1991 (the subject matter of which is incorporated herein by reference) for additional information on the HDLC protocol.
“Bursty” information such as video information and large computer files, on the other hand, passes over another structure. A first Ethernet network 8 having a plurality of workstations and a file server and an Ethernet hub is coupled to a second Ethernet network 9 via two Ethernet lines 10, 11 and an Ethernet hub/router 12. The file server of a network may, for example, store video data which can be accessed and displayed by the workstations of the network. Lines 10 and 11 are logically two different Ethernet lines. Hub/router 12 is coupled to the central office/exchange 6 via an isochronous link 13 such as a PRI line. Information is passed over link 13 using the HDLC protocol. The dots on selected workstations indicate video cameras.
A video camera of a workstation in the first Ethernet network can therefore capture video information and store that information in the file server of the first Ethernet network 8. A workstation in the second Ethernet network 9 can then access that information over Ethernet lines 10 and 11 via hub/router 12 and display that information. A workstation can also receive HDLC packaged “bursty” information (such as the yellow pages in graphic form) from the central office/exchange 6 via isochronous link 13.
There exists, however, another information packaging protocol known as asynchronous transfer mode (hereinafter “ATM”). See the document “ATM User-Network Interface Specification”, Version 3.0 (the subject matter of which is incorporated herein by reference) for additional information on the ATM protocol. Although it is envisioned that ATM will eventually replace HDLC, it is likely that significant numbers of ATM and HDLC data communication services will coexist for a significant period of time. It would therefore be desirable to provide network node hardware capable of both ATM and HDLC communication. Furthermore, a user using the structure of
An integrated circuit has an isochronous network port for receiving isochronous information from an isochronous network. To allow the integrated circuit to receive information packaged in accordance with two different packaging protocols (for example, HDLC and ATM), the integrated circuit includes a first protocol packet framer/deframer circuit for deframing information packaged in accordance with a first packaging protocol (for example, HDLC) and a second protocol packet framer/deframer circuit for deframing information packaged in accordance with a second packaging protocol (for example, ATM). A circuit switch is provided to steer incoming information to the appropriate packet framer/deframer circuit depending on which slot of the network frame carried the information.
In some embodiments, the information received from the network is stored in an external memory after being deframed. A buffer manager circuit may be provided on the integrated circuit to manage a circular inbound ring buffer of information in the external memory. A device, such as a CPU, residing on a host bus coupled to the integrated circuit may then read the information stored in the circular ring buffer via a parallel bus port of the integrated circuit. An arbiter circuit on the integrated circuit determines whether information from the framer/deframer circuit will be written to the external memory or whether the device on the host bus will read information from the external memory. In some embodiments, the integrated circuit includes a slot mapping memory which contains a map of which packet framer/deframer should be used for which slot. The slot mapping memory can be programmed from the host bus of the integrated circuit via the parallel bus port.
If information from the host bus is to be transmitted over the network, the information is written into the external buffer memory via the parallel bus port and the buffer memory port. The information is then framed by the appropriate packet framer/deframer circuit and is supplied to the isochronous network port of the integrated circuit via the circuit switch. The buffer manager circuit of the integrated circuit determines how the information is written into an outbound buffer of the external memory from the host parallel bus port and how that information is later read out of the outbound buffer and supplied to the packet framer/deframer circuit. The arbiter determines whether information received from the parallel bus port will be written into the external memory or whether information from the external memory will be supplied to the packet framer/deframer circuit for framing and transmission on the isochronous bus.
Other associated structures and methods are also disclosed.
An isochronous network specified by IEEE 802.9a (herein after referred to as “isoENET”) provides for transmission of both “nonbursty” and “bursty” information over a single Ethernet-compatible network. See the documents U.S. patent application Ser. No. 07/970,329 entitled “Frame-Based Transmission of Data”; IEEE specification 802.9a; and “IsoEnet Transforms LANs And WANs Into Interactive Multimedia Tools”, National Semiconductor Corporation, by Brian Edem et al., 1992 (the subject matter of all three documents is incorporated herein by reference) for further information on the IsoENET isochronous network.
In an isoENET network, the information being transmitted is broken up into a plurality of frames of information by a plurality of synchronization pulses. In addition to dedicated. Ethernet bandwidth, each frame contains 96 slots (also called “B-channels”). To transfer “bursty” information, multiple of these slots are filled with the bursty information. Several consecutive frames may be largely dedicated to the transfer of a burst of information whereas subsequent frames (after the burst) may carry no “bursty” information. To transfer “nonbursty” information, on the other hand, one slot of each successive frame may carry a small amount of “nonbursty” information. Accordingly, information from both a telephone and a workstation can be transferred over an isochronous network which is compatible with Ethernet.
Network 106 is an isoENET network which is capable of isochronous information transfer and is also compatible with the installed base of Ethernet networks. IsoENET network 106 includes four workstations 107-110, a telephone 111, and an isoENET hub 112. Because isoENET is capable of transmitting “nonbursty” telephone conversation information, telephone 111 is coupled to the isoENET network via workstation 107.
Video information (for example, MPEG encoded video) for display by the workstations of the two networks is stored in this example in a video server 113. Programs for use by the workstations of the two networks are stored in this example in a file server 114. The servers 113 and 114 are coupled to the two networks 100 and 106 via high speed 155 Mbps (megabits per second) fiber optic links 115-118 and an ATM switch 119. Accordingly, video information may be packaged in ATM format and transmitted from the video server 113 in “bursty” fashion over 155 Mbps link 118, 155 Mbps link 116, and isoENET line 107A to workstation 107.
A directory server 120 which supplies information in HDLC format may be provided by a telephone company. Directory server 120 is coupled to a central office/exchange 121 via a PRI line 122. The central office/exchange 121 is coupled to the ATM switch via a 155 Mbps link 123. Accordingly, information (such as yellow page graphic information) may be packaged in HDLC format and transmitted from the directory server 120 in “bursty” fashion over PRI line 122, 155 Mbps link 123, 155 Mbps link 116, and isoENET line 107A to workstation 107. Workstation 107 therefore is an isoENET node capable of communicating using both ATM and HDLC protocols. The structure of workstation 107 is described in further detail later.
Because network 100 is a standard Ethernet network which does not support “nonbursty” telephone conversation information, a telephone 124 associated with workstation 101 is not coupled to a workstation of network 100 but rather is coupled to a PBX 125 via a PBX line 126. Because network 106 is an isoENET network, telephone 111 transmits and receives “nonbursty” telephone conversation information via PBX-like line 127, isoENET line 107A, and PRI line 128. PBX 125 is coupled to the central office/exchange 121 via multiple PRI lines 129.
IsoENET line 107A of
To allow workstation 107 (see
Assume for illustrative purposes that isoENET frames are to be received from wires 205 of
After this initialization of the slot mapping memory 407, a channel counter (not shown) of circuit switch multiplexer/demultiplexer block 302 provides addresses to the receive portion of the slot mapping memory 407. Initially, the channel counter outputs a value which addresses the first memory location of the receive portion of memory 407. Because the first memory location of memory 407 was initialized to contain data which causes multiplexer/demultiplexer circuit 406 and HDLC packet framer/deframer circuit 404 to perform packet deframing, the first slot of the isoENET frame is deframed by HDLC packet framer/deframer circuit 404. After the information from the first slot is received, the channel counter is incremented. At the start of the second slot, the receive portion of memory 407 is read using the incremented count value output from the channel counter for the memory address. Because the second memory location of memory 407 was initialized to contain data which causes multiplexer/demultiplexer circuit 406 and ATM packet framer/deframer circuit 405 to perform packet deframing, the second slot of the isoENET frame is deframed by ATM packet framer/deframer circuit 405. After the information from the second slot is received, the channel counter is again incremented. Deframing of each successive slot of the isoENET frame proceeds in like fashion. The channel counter is reset by the rising edge of the frame synchronization signal received on wires 205 at the end of the frame. As an incoming packet is deframed, it is stored in a dedicated location in buffer 210.
When information is being written into buffer RAM 210 from one of the packet framer/deframer circuits, a buffer manager in block 408 of the integrated circuit determines where in memory 210 that information is written so that a separate receive ring buffer is maintained in memory 210 for each packet framer/deframer. The location and size of each ring buffer is set from the ISA bus by writing control registers in block 408. Four control registers are associated with each packet framer/deframer circuit: a control register defining the beginning location of the ring buffer in physical memory 210, a control register defining the ending location of the ring buffer in physical memory 210, a control register defining where in memory 210 the next incoming packet is to be written, and a control register defining where in memory 210 the oldest packet unread by the CPU is located. After an entire packet has been received and deframed by the appropriate packet framer/deframer circuit, the CPU is signalled via the ISA bus 201 that packet reception is complete. The CPU can then commence in the transfer of the packet data stored in buffer 210 to system memory via the ISA bus 201.
The block 408 actually includes two independent buffer managers. Each buffer manager is coupled to an associated packet framer/deframer circuit. Two HDLC packet framer/deframer circuits 403 and 404 are provided in the specific embodiment in order to support a specific video conferencing method. The present invention is not, however, limited to require two packet framer/deframers for the same protocol.
In some embodiments, block 408 also includes circuitry for managing a “receive cell buffer” in memory 210. The receive cell buffer can be used as a receptacle for ATM cells (a “cell” is an ATM construct and is 53 bytes of ATM information). When an ATM cell is received that is not part of a packet of information being written into a receive ring buffer, the ATM cell may be stored in the receive cell buffer. These stored ATM cells can then be accessed later via the ISA bus 201. Such ATM cells may, for example, be intermittently transmitted ATM cells which indicate the status of a conference call when the conversation of the conference call itself is being written into a receive ring buffer in memory 210. The receive cell buffer makes use of hardware in an ATM packet framer/deframer circuit which identifies cells from raw incoming data but does not utilize the higher level deframing hardware which identifies, packets of cells.
IsoBuffer integrated circuit 209 also includes a constant bit rate (CBR) buffer manager block 410 which manages raw unframed or nondeframed streams of data. The CBR buffer manager 410 keeps track of where a stream of raw data is being written into memory 210 by tracking frames (frames usually are transmitted at a 8 kHz rate) rather than by tracking the beginning and ending of packets. Given the number of bytes in a frame, and the starting location in memory 210, CBR buffer manager 410 can determine from the number of frames received the location at which raw nondeframed information is being written into memory 210. Nondeframed data in memory 210 may be deframed later in software by a CPU coupled to ISA bus 201. This constant bit rate buffer feature may be used to support a high level protocol which is not supported in hardware on integrated circuit 209 by a dedicated packet framer/deframer circuit.
Arbiter 409 determines which of the ISA bus 201, the buffer managers in block 408, or the CBR buffer manager 410 will have access to the buffer RAM 210. Any number of arbiter circuits can be used for this purpose. In one embodiment, each of the blocks 408, 410 and an ISA bus interface 411 provides a request signal on its own dedicated request line to the arbiter 409.
The microfiche appendix contains RTL code and schematics describing a specific embodiment of an integrated circuit which is described in block diagram form by
Although the invention is described in connection with certain illustrative embodiments for instructional purposes, the invention is not limited thereto. In some embodiments, the buffer memory is disposed on the same integrated circuit as the packet framer/deframer circuits and the circuit switch multiplexer/demultiplexer. Buses other than the ISA bus can be supported including the PCI bus and the Apple NuBUS. Accordingly, modifications, adaptations, and combinations of various aspects of the specific embodiments can be practiced without departing from the scope of the invention as set forth in the following claims.
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|17||"IsoEnet Transforms LANs and WANs Into Interactive Multimedia Tools," Brian Edem et al., Computer Technology Review, Winter 1992, 3 pgs. "ISO/IEC 3309" International Standard, ref. No. ISO/IEC 3309; 1991 (E), 1991, 7 pgs.|
|18||"Local Area Network Databook" published by National Semiconductor, pp. 1-3 to 1-9, 1-242 to 1-248, 5-3 to 5-7.|
|19||"National Proposes Isochronous Ethernet," Electronic News, vol. 38, No. 1940, p. 19, Nov. 30, 1992.|
|20||"PCMCIA Socket Services Interface Specification," Draft 2.00b, bearing the date Jul. 17, 1992.|
|21||"Token-Ring Network Architecture Reference," pp. 5-1 through 5-28 and pp. 5-10 and 5-17.|
|22||"VersaNet(TM) An Ethernet Extension for Isochronous Communications," bearing the date Aug. 14, 1992 is a paper sent to National Semiconductor Corp. from Condor Systems, Inc. of San Jose, CA on Aug. 18, 1992.|
|23||A disclosure of a communication system was presented at the IEEE 802.9, Standards Meeting on Nov. 8-12, 1992. The pages entitled: "Multi-Media Applications are Ready".|
|24||DP83950EB at IEEE 802.3, Multi-Port Repeater Evaluation Kit, Local Area Network Databook, National Semiconductor Corp., pp. 75-87, 1992 Edition.|
|25||DP839XX Isochronous Ethernet Physical Layer Iso-PHY(TM), Revision 2.1, bearing the date Dec. 1992 and DP839XX Isochronous Time Slot Exchanger, Revision 1.0, bearing the date Dec. 13, 1992, were disclosed to IBM and Ericsson.|
|26||DP839XX Isochronous Ethernet Physical Layer Iso-PHY(TM), Revision 3.0, bearing the date Dec. 1992 and Isochronous Time Slot Exchanger (IsoTSX(TM) Workbook, Revision 1.2, bearing the date Feb. 16, 1993, was disclosed to Luxcom, Inc. of Fremont, California.|
|27||Gallagher, C.A., "IEEE 802.9: A Multi-Service Lan Interface," Second IEEE National Conference on Telecommunications, Apr. 1989, York GB, pp. 173-178.|
|28||HMUX ERS "FDDI-II Hybrid Multiplexor (HMUX)," Rev. 2.4, Mar. 25, 1991.|
|29||IBM-On or about Nov. 1, 1991, IBM Corporation provided a "Task Order and appendix". A copy of pp. 6 and 7 of the Task Order and appendix titled, Isoethernet Project Local Cluster Controller Version 1.2.|
|30||Irube et al., "Integrated Information and Communication System for Business Networks," Hitachi Review 40(3):241-247, 1991.|
|31||Martini et al., "Real-Time Traffic in FDDI-II, Packet Switching vs. Circuit Switching," IEEE Infocom 1991, vol. 3, Apr. 1991, Bal Harbour, U.S., pp. 1413-1420.|
|32||Ross, F.E. et al., FDDI-A Lan Among Mans, Computer Communications Review, vol. 20, No. 3, Jul. 1990, New York, U.S., pp. 16-31.|
|33||Shimizu, H. et al., "IVDLAN Standardization and Development," IEICE Transactions, vol. E74, No. 9, Sep. 1991, Tokyo, JP, pp. 2696-2702.|
|34||*||U.S. Appl. No. 07/969,916 filed Nov. 1992 to Edem et al.|
|35||Wirbel, Loring, "Scheme for Fast Ethernet Proposed," appears to be a newspaper article; date of article is uncertain, but is believed to be prior to Mar. 1993.|
|36||Wong, David., "Second Generation 10Base T Silicon Solutions," IRE Wescon Convention Record, vol. 35, Nov. 1991, No. Hollywood, Ca. pp. 238-242.|
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|U.S. Classification||370/352, 370/395.5|
|International Classification||H04Q11/04, H04L29/06, H04L29/08, H04L12/56|
|Cooperative Classification||H04L69/324, H04L69/18, H04L29/06, H04Q11/0478, H04L2012/5652, H04L2012/5616, H04L2012/5615|
|European Classification||H04Q11/04S2, H04L29/06|
|Jan 12, 2005||AS||Assignment|
|Dec 21, 2007||FPAY||Fee payment|
Year of fee payment: 12
|Jun 27, 2013||AS||Assignment|
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