|Publication number||USRE38890 E1|
|Application number||US 09/457,848|
|Publication date||Nov 22, 2005|
|Filing date||Dec 9, 1999|
|Priority date||Feb 2, 1994|
|Also published as||CA2139972A1, CA2139972C, CN1119759A, CN1154907C, DE69515539D1, DE69515539T2, EP0666684A2, EP0666684A3, EP0666684B1, US5696941|
|Publication number||09457848, 457848, US RE38890 E1, US RE38890E1, US-E1-RE38890, USRE38890 E1, USRE38890E1|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Classifications (19), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a data converting device for converting input data such as image data or voice data according to a user's request, and more particularly, to a data converting device for converting data by employing a multitude of look-up-tables (LUTs) composed of converting data corresponding to input data.
In the conventional image output apparatus such as a color printer or facsimile, when image quality is compensated for brightness, contrast or tint by employing LUTs, an LUT for compensating each image characteristic, defined by each compensation mode, has to be stored in a discrete ROM. For example, when image quality is compensated by three kinds of compensation modes, three memory devices are needed for storing three kinds of LUTs.
When input data 101 is input periodically, first latch 11 latches input data 101 and outputs the latched data to first ROM 12 in accordance with clock signal 110. Output data 102 from first latch 11 serves as a lower address of first ROM 12. First condition data 107 determines a converting level with respect to the LUT stored in first ROM 12 and serves as an upper address of first ROM 12. That is, an address for accessing first ROM 12 consists of a lower address, i.e., output data 102 of first latch 11, and an upper address, i.e., first condition data 107. Data 103 output from first ROM 12 is data which is converted by a first LUT according to input data 101 and first condition data 107.
A first delay 17 delays clock signal 110 by a time period equal to the time delay between the input and output of first ROM 12 and generates the delayed clock signal 111 to be output to second latch 13. Second latch 13 connected to an output of first ROM 12 outputs to second ROM 14 the latched data 103 output from first ROM 12 according to the delayed clock signal 111. An address for accessing second ROM 14 consists of a lower address, i.e., output data 104 of second latch 13, and an upper address, i.e., second condition data 108. Data 105 output from second ROM 14 is data which is secondly converted by a second LUT according to second condition data 108 and data 104 which is firstly converted by the first LUT.
Second delay 18, third latch 15 and third ROM 16 operate as described above. Then, the data 113 thirdly converted by a third LUT of third ROM 16 according to the secondly converted data 106 and third condition data 109 is finally output.
The relationship between first, second and third condition data 107, 108 and 109 and the LUTs stored in first, second and third ROMs 12, 14 and 16 can be explained as follows. First condition data 107 determines a conversion level with respect to the converting mode of the first LUT and is generally given by a user. For example, if input data is 8-bit image data, the first LUT stored in first ROM 12 is for controlling the brightness level of an image, and the brightness level can be controlled by four steps, the number of input data is 28=256, that is, from 0 to 255. The first LUT consists of 256 byte (256×8 bits) data by steps, and the first condition data consists of 2-bit data for representing the four steps.
As described above, the conventional data converting device connects in series a number of ROMs equal to the number of the required LUTs and sequentially reads LUT data stored in each ROM, to thereby perform a data conversion. In general, a plurality of devices included in the peripheral control circuitry of ROMs can be miniaturized into a single chip such as an application specific integrated circuit (ASIC), but ROMs for storing LUTs are not included in an ASIC, in consideration of any necessary modification of ROM contents.
Accordingly, device miniaturization is restricted and the volume of the required hardware and manufacturing cost are increased since memory devices are needed in accordance with the number of LUTs according to the kinds of converting modes.
Accordingly, it is an object of the present invention to provide a data converting device for storing a multitude of LUTs in a single memory device to convert data.
To accomplish the above object, there is provided a data converting device for generating, with reference to two or more LUTs sequentially, a converted output data corresponding to input data and converting level selected by each LUT, the data converting device comprising:
The above objects and other advantages of the present invention will become more apparent by describing in detail a preferred embodiment thereof with reference to the attached drawings in which:
The entire memory capacity of a memory device is divided into blocks corresponding to the number of LUTs required for the kinds of converting modes, and a memory capacity of each divided block is divided into sub-blocks corresponding to the number of conversion levels of the corresponding LUT. Converting data is stored in the divided blocks and sub-blocks according to the corresponding converting mode and conversion level.
An embodiment of the present invention governs the case where the input data is image data consisting of eight bits, and each LUT is defined by a converting mode (for example, brightness, contrast, etc.) for controlling image quality, and the image quality can be controlled by four conversion levels in each converting mode.
In applying the present invention, if the number of bits of input data, the kinds of converting modes and the number of conversion levels are different from those of the embodiment of the present invention, the memory capacity of the blocks and the sub-blocks of a memory device can be divided appropriately. In addition, if the memory capacity occupied by each LUT is different, the memory blocks for each LUT can be divided into equal capacities or can be variably divided for an efficient use of memory capacity. For the latter case, a problem in data accessing caused by a variable constitution of memory capacity has to be considered.
In addition, LUT data stored in a memory device includes various converting data required for the apparatus to which the present invention is applied, for example, audio or temperature compensation data as well as image compensation data.
A clock signal 451 is a pulse signal whose period equals the time interval between the input of single input data 411 and the output of the data finally converted by all LUTs stored in ROM 49. Clock signal 451 is synchronized with input data 411 and input to first address generator 45 and sync controller 47 to thereby synchronize addresses 453, 433 and 413 for accessing ROM 49.
First address generator 45 receives clock signal 451 and generates first address 453 for sequentially selecting the desired LUT stored in ROM 49. Second address generator 43 generates, according to condition data 431 for determining a conversion level defined for each LUT, second address 433 for selecting a sub-block within the LUT selected by first address 453. Third address generator 41 receives input data 411 and feedback output data 493 and generates third address 413 for selecting converting data within the selected sub-block. In other words, input data 411 is generated as third address 413 when data is converted by the first LUT, and the feedback output data 493 is generated as third address 413 for other cases. Accordingly, an address for accessing the data of ROM 49 has the order of first, second and third addresses 453, 433 and 413.
A first address generator 51 comprises a counter 551 for generating four pulses during one cycle of the input clock signal 561. The generated signal 550 is output to ROM 59, a second MUX 531 and a decoder 515.
A second address generator 53 comprises a second MUX 531 having a three-to-one multiplexer for selecting and outputting one among three types of condition data 541, 542 and 543 according to pulse signal 550 input from counter 551 and a second latch 532 for latching data 545 output from second MUX 531 and outputting the latched data to ROM 59 according to sync signal 570.
A third address generator 51 comprises a decoder 515 for generating the signal 525 for controlling first MUX511 according to pulse signal 550 input from counter 551, a first MUX 511 made up of a two-to-one multiplexer where input data 521 and the feedback output data 590 are input for selecting and outputting one of the input signals 521 and 590 according to control signal 525 generated from decoder 515, and a first latch 513 for latching data 523 output from first MUX 511 and outputting the latched data to ROM 59 according to sync signal 570.
A sync controller 57 comprises first, second and third delays 571, 572 and 573 for outputting clock signal 561 which is delayed by a delay time determined by the data access time of ROM 59, and an OR gate 575 for performing a logical OR operation on clock signal 561 and the delayed signals 582, 583 and 584 and thereby generating sync signal 570. The generated sync signal 570 is input to second latch 532 of second address generator 53 and first latch 513 of third address generator 51.
Sync signal 570 is generated by performing a logical OR operation on clock signal 561 and the first, second and third delay signals 582, 583 and 584 which are delayed by a predetermined time with respect to clock signal 561. Four pulses are generated during one cycle of input data signal 521 and are employed for synchronization with addresses input to ROM 59.
Operation during a first cycle of sync signal 570 can be explained as follows. Counter 551 outputs first address signal 550 for accessing the first LUT of ROM 59 according to the clock signal. Second MUX 531 selects first condition data 541 with respect to a conversion level of the first LUT and outputs the selected data to second latch 532. The latched data is output as second address signal 530 for addressing ROM 59. Decoder 515 generates a control signal that makes first MUX 511 select input data 521, and first MUX 511 selects input data 521 according to the control signal of decoder 515 and outputs the result to first latch 513, and the latched data is output as third address signal 510 for accessing ROM 59. Accordingly, data of the first LUT of ROM 59 is accessed by the first, second and third address signals 550, 530 and 510, and the input data is converted by the first LUT and the first-converted data is fed back and is input to first MUX 511.
Operation during a second cycle of sync signal 570 can be explained as follows. Counter 551 outputs first address signal 550 for accessing the second LUT of ROM 59 according to the clock signal. Second MUX 531 selects second condition data 541 with respect to a conversion level of the second LUT and outputs the selected data to second latch 532. The latched data is output as second address signal 530 for accessing ROM 59. Decoder 515 generates a control signal that makes first MUX 511 select the feedback first-converted data 590, and first MUX 511 selects the feedback first-converted data 590 according to the control signal of decoder 515 and outputs the result to first latch 513, and the latched data is output as third address signal 510 for accessing ROM 59. Accordingly, data of the second LUT of ROM 59 is accessed by the first, second and third address signals 550, 530 and 510, and the feedback first-converted data is converted by the second LUT and the second-converted data is fed back and is input to first MUX 511.
Operation during a third cycle of sync signal 570 is the same as that during the second cycle of the sync signal. Data of a third LUT of ROM 59 is accessed by first, second and third address signals 550, 530 and 510, and the feedback second-converting data is converted by the third LUT and the third-converted data is fed back and is input to first MUX 511.
During a fourth cycle of the sync signal, first MUX 511 selects the feedback third-converted data 590 and outputs the selected data to first latch 513. The latched data is output as finally converted data 510.
According to the present invention, input data is sequentially converted by all LUTs during one clock cycle, to thereby generate final output data. Accordingly, when the number of LUTs for data conversion is increased, output data is fed back so as to convert data through all LUTs. Therefore, the clock cycle is increased in proportion to the delay time of the ROM. However, such a problem can be solved by reducing the access time of the ROM.
As described above, a plurality of LUTs are stored in a single memory device and a data converting device adopting the same is provided, so that the data converting device can be miniaturized by reducing the bulk of the memory device.
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|U.S. Classification||710/3, 358/471, 358/447, 358/468, 358/451, 345/501, 348/651, 348/654|
|International Classification||G06F3/14, G06T5/00, H04N1/60, G06F12/02, G06T5/40, G09G5/00, G06F3/00|
|Cooperative Classification||G06T5/009, H04N1/6019|
|European Classification||H04N1/60D2, G06T5/00M2|
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