|Publication number||USRE38961 E1|
|Application number||US 10/150,379|
|Publication date||Jan 31, 2006|
|Filing date||May 16, 2002|
|Priority date||Oct 6, 1998|
|Also published as||DE69941230D1, EP0993040A2, EP0993040A3, EP1724830A2, EP1724830A3, EP1724830B1, US6063646|
|Publication number||10150379, 150379, US RE38961 E1, US RE38961E1, US-E1-RE38961, USRE38961 E1, USRE38961E1|
|Inventors||Atsushi Okuno, Koichiro Nagai, Noriko Fujita, Yuki Ishikawa, Noritaka Oyama, Tsunekazu Hashimoto|
|Original Assignee||Casio Computer Co., Ltd., Sanyu Rec Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (22), Non-Patent Citations (1), Referenced by (8), Classifications (36), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a method for producing a chip-size semiconductor package.
In view of recent development of electronic equipment such as portable telephones, notebook-size personal computers, electronic personal data books, etc., there are demands for production of semiconductor packages of higher density, smaller size and reduced thickness which are useful for such electronic equipment.
To meet said demands, various kinds of semiconductor packages have been developed. Examples are LSI-mounting TAB, tape carriers, plastic leaded chip carriers (PLCC), ball grid arrays (BGA), chip-size packages (CSP), flip chips, etc. These semiconductor packages have excellent features but are defective in production efficiency and mounting reliability.
Methods have been proposed for producing chip-size semiconductor packages among said semiconductor packages in an attempt to improve the production efficiency and the mounting reliability (of. Japanese Unexamined Patent Publication No. 79362/1998). According to the proposed methods, electronic circuits for a plurality of semiconductor chips are formed on a wafer and bumps are provided on the semiconductor chips. Then, after the wafer is placed into a mold cavity, a resin is supplied to the space around the bumps to encapsulate the bumps by the so-called transfer molding. Thereafter at least the tips of bumps covered with the resin layer are exposed at the surface of the resin layer. Finally the wafer with the resin layer formed thereon is cut into individual semiconductor chips to obtain semiconductor packages.
According to the foregoing conventional methods for producing semiconductor packages, a resin layer is formed on the bump-arranged surface of the wafer before mounting the semiconductor packages on the printed circuit board. Consequently the methods eliminate the need for the step of filling an encapsulation resin into a narrow space between the semiconductor chips and the printed circuit board after mounting the semiconductor chips on the board so that the mounting reliability is improved. Because of the encapsulation of the wafer with a resin, the methods can achieve a higher production efficiency than the encapsulation of individual semiconductor packages with a resin.
However, the conventional methods pose the following problems due to the use of ai a mold. First of all, high investment in equipment is essentially needed. Further, since the encapsulating step and heat-curing step are conducted in this order within the mold, the wafer is confined in the mold for a prolonged period of time, thereby lowering the production efficiency. Moreover, it is difficult to form a resin layer having a thickness of 1 mm or less.
The present invention was accomplished to overcome the above-mentioned prior art problems. An object of the invention is to provide a method for producing semiconductor packages, the method being capable of lowering the equipment investment, increasing the production efficiency and forming a resin layer with a thickness of 1 mm or less.
Other features of the invention will become apparent from the following description.
According to the invention, there is provided a method for producing semiconductor package, the method comprising the steps of:
This invention will be further clarified by the description of two embodiments with reference to the accompanying drawings. The invention, however, is not limited to the embodiments, but various modifications are possible without deviation from the scope of the invention.
First, the structure of a semiconductor package 10 is described below with reference to FIG. 1. The semiconductor package 10 comprises a semiconductor chip 11, bumps 2 serving as electrodes, a sealant layer 4 having substantially the same height as the bumps 2 and solder balls 3 welded to the upper end surface of bumps. Namely the semiconductor package 10 has a very simple structure.
The semiconductor package 10 with said structure is substantially equal in size to the semiconductor chip 11, and is of the so-called chip-size package structure. Because of this structure, the semiconductor package produced by the method of the invention can satisfactorily fulfil the need for the miniaturized semiconductor packages as required in recent years.
The method for producing the semiconductor package 10 is described below with reference to
In the step of forming electronic circuits in
After practicing the step of forming the electronic circuits, the wafer 1 is subjected to the step of forming bumps. In the step of forming bumps, pillar-shaped bumps 2 with the specified height are provided on the wafer surface 111 provided with the circuit as shown in FIG. 4. The bumps 2 are formed by the bump-forming technique conventionally used for flip chips or the like, such as the plating method.
After practicing the step of forming bumps, the wafer 1 is subjected to the step of printing encapsulation. In the printing encapsulation step, a viscous fluid sealant 40 is forcedly filled by screen printing to form on the entire circuit-forming surface of the wafer 1 a sealant layer 4 having a thickness of height higher than the bumps 2 as shown in FIG. 5. Stated more specifically, after a metal mask 6 and the wafer 1 are properly positioned, a specific amount of sealant 40 is fed onto the specified part of the metal mask 6 and forcedly filled into a through-hole 6a of the metal mask 6 by the reciprocative movement of a squeegee 5. After filling, the metal mask 6 is released from the sealant layer 4. The diameter of the through-hole 6a is substantially equal to or smaller by about 1 to about 10 mm than that of the wafer. Preferred sealing materials useful as the sealant 40 are viscous fluids which are excellent in adhesion to the wafer 1, and have low shrinkage in curing, low residual stress after curing, low expansion coefficient, low water absorption and high heat resistance. An epoxy resin composition having such properties is suitable as the sealant 40. Specific examples include a composition containing an epoxy resin and silica in an amount of 60 to 95% by weight based on the composition, such as NPR-780 and NPR-785 (trademarks, products of Japan Rec Co., Ltd.). It may occur that the air is included into the sealant 40 when the sealant 40 is forcedly filled into the through-hole 6a of the metal mask 6. The inclusion of air can be effectively prevented by encapsulation with screen printing means under a vacuum atmosphere preferably in the same vacuum degree between during the forward movement of the squeegee and during the backward movement thereof. Alternatively the vacuum degree may be varied between during the forward movement of the squeegee and during the backward movement thereof (e.g. under 10 Torr or less in the forward movement and under 50 to 150 Torr in the backward movement). In the method of the invention, printing means is used for encapsulation, so that the sealant layer can be thinned to a minimum thickness of about 50 μm. When required, a thick layer up to about 2 mm in thickness can be formed.
After practicing the step of printing encapsulation, the wafer 1 is subjected to the step of curing the sealant layer. In the step of curing the sealant layer, the wafer 1 with the sealant layer is placed into a known heating furnace to cure the sealant layer as shown in FIG. 6.
After practicing the step of curing the sealant layer, the wafer 1 is subjected to the step of exposing the bumps. In the step of exposing the bumps, the surface of the sealant layer 4 is ground with a grinder 7 as shown in
After practicing the step of exposing the bumps, the wafer 1 is subjected to the step of welding solder balls. In the step of welding solder balls, solder balls 3 for bonding to the printed circuit board are placed onto the exposed upper end surface of the bumps and welded thereto by the conventional ball mounter as shown in FIG. 8. The solder balls 3 can be welded to the bumps by the conventional bump-forming technique such as a transfer method.
Finally after executing the step of welding solder balls, the wafer 1 is subjected to the dicing step. In the dicing step, the wafer 1 and the sealant layer 4 as united are diced by a known dicer 8 into individual chips 11, whereby numerous chip-size semiconductor packages 10 are obtained.
A second embodiment of the invention will be described below.
First, the semiconductor package 100 according to the second embodiment is described with reference to FIG. 10. The semiconductor package 100 comprises a semiconductor chip 11, bumps 2, a sealant layer 400 and solder balls 3 which are provided in the semiconductor package 10 of the first embodiment. However, unlike the semiconductor package 10, the upper surface of the sealant layer 400 does not evenly extend and covers the bumps 2 in such a manner that the bump 2 is individually surrounded with a slope as shown in FIG. 10. With this structure, the semiconductor package 100 is such that the bumps 2 are reinforced by the sealant layer 400 and the circuit-forming surface 111 of the chip 11 is covered and protected with the sealant layer 400. Consequently the semiconductor package 100 is equal in mounting reliability to the semiconductor package 10 of the first embodiment shown in FIG. 1.
The method for producing the semiconductor package 100 is described below. In the method for producing the semiconductor package 100, the steps of forming electronic circuits and forming bumps as shown in
After practicing the step of printing encapsulation, the wafer 1 is subject(ed to the step of curing the sealant layer. In the step of curing the sealant layer, the printed wafer 1 is placed into a heating furnace to cure the sealant layer indented between the pairs of bumps as shown in FIG. 12.
After practicing the step of curing the sealant layer, the wafer 1 is subjected to the step of exposing the bumps. In the step of exposing the bumps, the surface of the sealant layer 400 is ground with the grinder 7 as shown in
After practicing the step of exposing the bumps, a plurality of semiconductor packages 100 are obtained following the step of welding solder balls and the dicing steps. The step of welding solder balls and the dicing steps can be carried out in the same manner as in the first embodiment. Thus the description of these steps is omitted.
According to the producing method of the invention, screen printing means is used to encapsulate the entire surface of the wafer with a resin, so that the equipment costs can be markedly reduced as compared with conventional methods using a mold. Since the formation of sealant layer and the heat-curing are separately done, the production operation can be continuously performed without necessity of confining the wafer to a step for a prolonged period of time. Moreover, the sealant layer can be thinned to a minimum thickness of about 50 μm.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3644180 *||Feb 26, 1970||Feb 22, 1972||Western Electric Co||Methods of using inorganic resists|
|US4600600 *||Oct 29, 1984||Jul 15, 1986||Siemens Aktiengesellschaft||Method for the galvanic manufacture of metallic bump-like lead contacts|
|US5232651 *||Dec 10, 1990||Aug 3, 1993||Japan Rec Co., Ltd.||Method of sealing electric parts mounted on electric wiring board with resin composition|
|US5318651 *||Nov 19, 1992||Jun 7, 1994||Nec Corporation||Method of bonding circuit boards|
|US5620927 *||May 25, 1995||Apr 15, 1997||National Semiconductor Corporation||Solder ball attachment machine for semiconductor packages|
|US5641113||Jun 2, 1995||Jun 24, 1997||Oki Electronic Industry Co., Ltd.||Method for fabricating an electronic device having solder joints|
|US5786271 *||Jul 3, 1996||Jul 28, 1998||Kabushiki Kaisha Toshiba||Production of semiconductor package having semiconductor chip mounted with its face down on substrate with protruded electrodes therebetween and semiconductor package|
|US5789279 *||Sep 14, 1995||Aug 4, 1998||Sgs-Thomson Microelectronics S.R.L.||Method and apparatus for electrically insulating heat sinks in electronic power devices|
|US5837427 *||Aug 9, 1996||Nov 17, 1998||Samsung Electro-Mechanics Co Co., Ltd.||Method for manufacturing build-up multi-layer printed circuit board|
|US5849608 *||May 29, 1997||Dec 15, 1998||Nec Corporation||Semiconductor chip package|
|US5851845 *||Dec 18, 1995||Dec 22, 1998||Micron Technology, Inc.||Process for packaging a semiconductor die using dicing and testing|
|US5907786 *||May 21, 1996||May 25, 1999||Mitsubishi Denki Kabushiki Kaisha||Process for manufacturing a flip-chip integrated circuit|
|US5977641 *||May 13, 1998||Nov 2, 1999||Kabushiki Kaisha Toshiba||Semiconductor device and method for manufacturing the same|
|US5989982 *||Nov 10, 1997||Nov 23, 1999||Oki Electric Industry Co., Ltd.||Semiconductor device and method of manufacturing the same|
|US6103552 *||Aug 10, 1998||Aug 15, 2000||Lin; Mou-Shiung||Wafer scale packaging scheme|
|US6194250 *||Sep 14, 1998||Feb 27, 2001||Motorola, Inc.||Low-profile microelectronic package|
|US6232563 *||Nov 22, 1996||May 15, 2001||Lg Electronics Inc.||Bump electrode and method for fabricating the same|
|US6260264 *||Dec 8, 1997||Jul 17, 2001||3M Innovative Properties Company||Methods for making z-axis electrical connections|
|US6423102 *||Dec 9, 1997||Jul 23, 2002||Sharp Kabushiki Kaisha||Jig used for assembling semiconductor devices|
|DE19754372A1||Dec 9, 1997||Sep 24, 1998||Fraunhofer Ges Forschung||Chipanordnung und Verfahren zur Herstellung einer Chipanordnung|
|EP0729182A2||Feb 20, 1996||Aug 28, 1996||Matsushita Electric Industrial Co., Ltd||Chip carrier and method of manufacturing and mounting the same|
|JPH1079362A *||Title not available|
|1||Patent Abstracts of Japan, vol. 1998, No. 06, Apr. 30, 1998 and JP 10-050772 A (Hitachi Ltd; Hitachi VLSI Eng. Corp.), Feb. 20, 1998-Abstract only.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7189599 *||Sep 9, 2004||Mar 13, 2007||Nec Electronics Corporation||Lead frame, semiconductor device using the same and method of producing the semiconductor device|
|US7719096||Jul 9, 2007||May 18, 2010||Vishay General Semiconductor Llc||Semiconductor device and method for manufacturing a semiconductor device|
|US8604568||Nov 28, 2011||Dec 10, 2013||Cambridge Silicon Radio Limited||Multi-chip package|
|US8962470||Mar 30, 2009||Feb 24, 2015||Fujitsu Limited||Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus|
|US20050032271 *||Sep 9, 2004||Feb 10, 2005||Nec Electronics Corporation||Lead frame, semiconductor device using the same and method of producing the semiconductor device|
|US20050161814 *||Mar 21, 2005||Jul 28, 2005||Fujitsu Limited||Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus|
|US20080036072 *||Jul 9, 2007||Feb 14, 2008||Vishay General Semiconductor Llc||Secmiconductor device and method for manufacturing a semiconductor device|
|US20140091457 *||Sep 29, 2012||Apr 3, 2014||Hongjin Jiang||Controlled solder height packages and assembly processes|
|U.S. Classification||438/108, 438/613, 438/107, 438/692, 438/106, 438/127, 438/612, 438/460, 438/114|
|International Classification||H01L21/56, H01L21/60|
|Cooperative Classification||H01L2924/00014, H01L2224/11, H01L2224/13, H01L2924/12042, H01L2924/181, H01L24/13, H01L24/11, H01L2224/11334, H01L2924/01005, H01L2924/01078, H01L2924/01027, H01L2224/1147, H01L2224/131, H01L2224/274, H01L2224/16, H01L2924/01082, H01L2924/01033, H01L2924/014, H01L2924/00013, H01L2924/01006, H01L21/56, H01L23/3114|
|European Classification||H01L23/31H1, H01L24/10, H01L21/56|
|Sep 24, 2007||FPAY||Fee payment|
Year of fee payment: 8
|Oct 19, 2011||FPAY||Fee payment|
Year of fee payment: 12
|Jan 3, 2012||AS||Assignment|
Owner name: TERAMIKROS, INC., JAPAN
Free format text: CHANGE OF OWNERSHIP BY CORPORATE SEPARATION;ASSIGNOR:CASIO COMPUTER CO., LTD.;REEL/FRAME:027465/0812
Effective date: 20111212
|Jan 6, 2012||AS||Assignment|
Owner name: TERAMIKROS, INC., JAPAN
Free format text: CHANGE OF OWNERSHIP BY CORPORATE SEPARATION-TO CORRECT ASSIGNEE'S ADDRESS ON REEL 027465, FRAME 0812;ASSIGNOR:CASIO COMPUTER CO., LTD.;REEL/FRAME:027492/0449
Effective date: 20111212
|Nov 30, 2016||AS||Assignment|
Owner name: TERA PROBE, INC., JAPAN
Free format text: MERGER;ASSIGNOR:TERAMIKROS, INC.;REEL/FRAME:040772/0440
Effective date: 20131001
|Feb 3, 2017||AS||Assignment|
Owner name: AOI ELECTRONICS CO., LTD., JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TERA PROBE, INC.;REEL/FRAME:041169/0952
Effective date: 20170124