US RE39121 E1 Abstract A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D
1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18. Claims(41) 1. A processor that decodes and executes instructions,
the processor comprising:
a source register configured to store a signed m-
bit integer; a destination register configured to store an unsigned s-bit register; a detecting unit for detecting whether an instruction to be decoded is a predetermined instruction; and
a rounding unit for rounding, when the detecting unit is detecting that the instruction is the predetermined instruction, athe signed m-bit integer stored at an operand designated by the predetermined instruction to a value expressed as an unsigned s-bit integer and storing the unsigned s-
bit integer in the destination register wherein s is less than m, wherein a bit length of the destination register where the unsigned s-bit integer is stored is smaller than a bit length of the source register where the signed m-bit integer is stored. 2. The processor of
a first judging circuit for judging, when the detecting unit is detecting that the instruction is the predetermined instruction, whether a signed m-bit integer stored at the operand is a negative number; and
a second judging circuit for judging when the detecting unit is detecting that the instruction is the predetermined instruction, whether a signed m-bit integer stored at the operand exceeds a maximum value expressed as an unsigned s-bit integer, and
wherein the processor further comprises:
transferring unit for transferring one of a first predetermined value expressed as an unsigned s-bit integer a second predetermined value expressed as an unsigned s-bit integer, and a value stored at the operand to the transfer address for a rounding result, based on the combination of respective judging results of the first judging circuit and the second judging circuit.
3. The processor of
wherein the transferring unit transfers a value zero expressed as an s-bit integer as the first predetermined value to the transfer address for the rounding result, when the first judging circuit judges that the signed m-bit integer stored at the operand is a negative number;
wherein the transferring unit transfers the maximum value expressed as an unsigned s-bit integer as a second predetermined value to the transfer address for the rounding result, when the second judging circuit judges that the signed m-bit integer stored at the operand exceeds the maximum value expressed as an unsigned s-bit integer, and
wherein the transferring unit transfers the value stored at the operand to the transfer address for the rounding result, when the first judging circuit judges that the signed m-bit integer stored at the operand is not a negative number and the second judging circuit judges that the signed m-bit integer stored at the operand does not exceed the maximum value.
4. The processor of
wherein the first judging circuit includes a judging unit for judging whether a sign bit of an s-bit integer in the signed m-bit integer stored at the operand is on or off, and
wherein the second judging circuit includes a calculator for subtracting a maximum positive value for an s-bit integer from the signed m-bit integer stored at the operand.
5. The processor of
wherein the judging unit of the first judging circuit examines one of an eighth, sixteenth, and twenty-fourth bit counted from a least significant bit side as the sign bit, in accordance with a content of the indication field included in the predetermined instruction, and
wherein the second judging circuit includes a generating unit for generating one of an unsigned 8-bit integer, and an unsigned 16-bit integer, and an unsigned 24-bit integer, in accordance with a content of the indication field included in the predetermined instruction.
6. The processor of
wherein the predetermined instruction designates the specialized register as the operand, and
the transferring unit transfers the value stored in the specialized register to the transfer address for the rounding result, when the first judging circuit judges that a signed m-bit integer stored in the specialized register is not a negative number and the second judging circuit judges that the signed m-bit integer stored in the specialized register does not exceed the maximum value.
7. The processor of
wherein the predetermined instruction designates one of the general registers in the register file as a transfer address for a rounding result, and
wherein the transferring unit transfers one of a first predetermined value express as an unsigned s-bit integer, a second predetermined value expressed as an unsigned s-bit integer, and a value stored in the specialized register to the general register being designated by the predetermined instruction.
8. A processor that decodes and executes instructions,
the processor comprising: first detecting unit for detecting whether an instruction to be decoded is an instruction performing a calculation; second detecting unit for detecting whether an instruction to be decoded is an instruction performing both a calculation and a rounding of the calculation result; calculating unit for performing, when the first detecting unit detects that the instruction performs a calculation, a calculation using a signed m-bit integer; and rounding unit for rounding, when the second detecting unit detects the instruction performing both a calculation and a rounding, a result of the calculation performed with a signed m-bit integer to a value expressed as an unsigned s-bit integer wherein s is less than m. 9. The processor of
and wherein the rounding unit includes: a first judging circuit for judging, when the second detecting unit detects the instruction performing both a calculation and a rounding, whether the calculation result of the calculating unit is a negative number; and a second judging circuit for judging, when the second detecting unit detects that the instruction performing both a calculation and a rounding, whether the calculation result of the calculating unit exceeds a maximum value expressed as an unsigned s-bit integer, and wherein the processor further comprises: transferring unit for transferring one of a first predetermined value expressed as an unsigned s-bit integer, a second predetermined value expressed as an unsigned s-bit integer, and the calculation result of the calculating unit to the transfer address, based on the combination of respective judging results of the first judging circuit and the second judging circuit. 10. The processor of
wherein the transferring unit transfers a value zero expressed as an s-bit integer as the first predetermined value to the transfer address, when the first judging circuits judges that the calculation result of the calculating unit is a negative number; wherein the transferring unit transfer the maximum value expressed as an unsigned s-bit integer as the second predetermined value to the transfer address, when the second judging circuit judges that the calculation result of the calculating unit exceeds the maximum value expressed as an unsigned s-bit integer; and wherein the transferring unit transfers the calculation result of the calculating unit to the transfer address for the rounding result, when the first judging circuit judges that the calculation result of the calculating unit is not a negative number and the second judging circuit judges that the calculation result of the calculating unit does not exceed the maximum value. 11. The processor of
wherein the second judging circuit includes a calculator for subtracting a maximum positive value for an unsigned s-bit integer from the calculation result of the calculation unit. 12. The processor of
wherein the judging unit of the first judging circuit examines one of an eighth, sixteenth, and twenty-fourth bit from a least significant bit as the sign bit, in accordance with a content of the indication field included in the correction instruction, and wherein the calculator includes a generating unit for generating one of an unsigned 8-bit integer, an unsigned 16-bit integer, and an unsigned 24-bit integer, in accordance with a content of the indication field included in a correction instruction. 13. The processor of
wherein each calculation instruction designates one of the general registers in the register file as a transfer address for a rounding result. 14. A machine readable medium storing a program that enables a processor for executing a rounding process comprising:
detection step for directing the processor for detecting whether an instruction to be decoded by the processor is a predetermined instruction; and rounding step for directing the processor for rounding a signed m-bit integer stored at an operand designated by the predetermined instruction to a value expressed as an unsigned s-bit integer wherein s is less than m. 15. A program recording medium that enables a processor to decode and execute instructions comprising:
first direction for directing the processor to detect whether an instruction to be decoded is an instruction for performing a calculation; second direction for directing the processor to detect whether an instruction to be decoded is an instruction performing both a calculation and a rounding of the calculation result; third direction for directing the processor to perform, when the processor detects that the instruction performs a calculation, a calculation using a signed m-bit integer; and fourth direction for directing the processor, when the processor is detecting an instruction performing both a calculation and a rounding, for rounding a result of the calculation performed with a signed m-bit integer to a value expressed as an unsigned s-bit integer wherein s is less than m. 16. The program recording medium of
17. The program recording medium of
a first judging step for judging, when the processor detects the instruction performing both a calculation and a rounding, whether the calculation result of the calculating means is a negative number; and a second judging step for judging, when the processor detects that the instruction performing both a calculation and a rounding, whether the calculation result of the calculating means exceeds a maximum value expressed as an unsigned s-bit integer, and transferring step for directing the processor to transfer one of a first predetermined value expressed as an unsigned s-bit integer, a second predetermined value expressed as an unsigned s-bit integer, and the calculation result of the calculating data to the transfer address, based on the combination of respective judging results of the first judging step and the second judging step. 18. The program recording medium of
wherein the transferring step directs the processor to transfer the maximum value expressed as an unsigned s-bit integer as the second predetermined value to the transfer address, when the second judging step judges that the calculation result of the calculating data exceeds the maximum value expressed as an unsigned s-bit integer; and wherein the transferring step directs the processor to transfer the calculation result of the calculating data to the transfer address for the rounding result, when the first judging step judges that the calculation result of the calculating data is not a negative number and the second judging step judges that the calculation result of the calculating data does not exceed the maximum value. 19. The processor of
wherein the second judging step directs the processor to subtract a maximum positive value for an unsigned s-bit integer from the calculation result of the calculation data. 20. The program recording medium of
wherein the first judging step directs the processor to examine one of an eighth, sixteenth, and twenty-fourth bit from a least significant bit as the sign bit, in accordance with a content of the indication field, wherein the second judging step directs the processor to generate one of an unsigned 8-bit integer, an unsigned 16-bit integer, and an unsigned 24-bit integer, in accordance with a content of the indication field. 21. A processor that decodes and executes instructions, the processor comprising:
a source register; a destination register; a positive conversion and saturation calculation unit for a) converting a data stored in the source register to zero and storing the zero in the destination register when the data is negative, and b) saturating a data stored in the source register to a maximum value and storing the maximum value in the destination register when the data exceeds the maximum value, wherein at least one of the converting and the saturating is performed by one instruction, wherein a bit length of the destination register where the zero or maximum value is stored is smaller than a bit length of the source register where the signed m-bit integer is stored. 22. The processor of
a decoding unit for decoding an instruction including a first instruction, wherein the first instruction designates the data. 23. The processor of
wherein the positive conversion and saturation calculation unit truncates the data when the data designated by the first instruction is neither negative nor exceeds the maximum value. 24. The processor of
wherein the data is a signed integer, each of the maximum value and the truncated data is an unsigned integer, and an available range of the signed integer entirely includes an available range of the unsigned integer. 25. The processor of
wherein the signed integer is m-bit long and the unsigned integer is s-bit long, wherein s is less than m. 26. The processor of
wherein the positive conversion and saturation calculation unit includes: a zero generator for outputting data having a zero value, and a constant generator for outputting data of the maximum value. 27. The processor of
wherein the positive conversion and saturation calculation unit further includes a selection unit for selecting the output of the zero generator when the data designated by the first instruction is negative, and selecting the output of the constant generator when the data exceeds the maximum value. 28. The processor of
wherein the selection unit selects one of the output of the zero generator, the output of the constant generator, and a value obtained by truncating the data designated by the first instruction, when the data is neither negative nor exceeds the maximum value. 29. The processor of
wherein the data designated by the first instruction is a result of executing a second instruction which is different from the first instruction. 30. The processor of
wherein the positive conversion and saturation calculation unit includes a zero generator for outputting a value zero represented as an s-bit integer, a constant generator for outputting data of the maximum value represented as an unsigned s-bit integer, a truncating unit for truncating the data designated by the first instruction and which is represented as a signed m-bit integer, to an unsigned s-bit integer, s being less than m, and a selection unit for a) selecting the output of the zero generator when the data designated by the first instruction is negative, b) selecting the output of the constant generator when the data exceeds the maximum value, and c) selecting the output of the truncating unit when the data is neither negative nor exceeds the maximum value. 31. The processor of
wherein the positive conversion and saturation calculation unit further includes a polarity judging unit for detecting whether the data designated by the first instruction and which is represented as a signed m-bit integer is negative, and a comparator for detecting whether the data exceeds the maximum value, wherein the selection unit a) selects the output of the zero generator when the polarity judging unit has detected that the data is negative, b) selects the output of the constant generator when the comparator has detected that the data exceeds the maximum value, and c) selects the output of the truncating unit when neither the polarity fudging unit has detected that the data is negative, nor the comparator has detected that the data exceeds the maximum value. 32. The processor of
wherein the positive conversion and saturation calculation unit converts or saturates data provided by the calculating unit, and the calculating together with at least one of the converting and the saturating are performed by one instruction. 33. The processor of
a decoding unit for decoding an instruction including a first instruction, wherein the calculating unit performs calculations on the data designated by the first instruction. 34. The processor of
wherein the positive conversion and saturation calculation unit, when the data provided by the calculating unit is neither negative nor exceeds the maximum value, truncates the data. 35. The processor of
wherein the data provided by the calculating unit is signed integer and each of the maximum value and the truncated data is an unsigned integer, and an available range of the unsigned integer entirely includes an available range of the unsigned integer. 36. The processor of
wherein the signed integer is m-bit long and the unsigned integer is s-bit long, wherein s is less than m. 37. The processor of
wherein the positive conversion and saturation calculation unit includes a zero generator for outputting a value zero represented as an s-bit integer, a constant generator for outputting data of the maximum value represented as an unsigned s-bit integer, a truncating unit for truncating the data provided by the calculating unit and which is represented as a signed m-bit integer, to an unsigned s-bit value, s being less than m; and a selection unit for a) selecting the output of the zero generator when the data provided by the calculating unit is negative, b) selecting the output of the constant generator when the data exceeds the maximum value, and c) selecting the output of the truncating unit when the data is neither negative nor exceeds the maximum value. 38. The processor of
wherein the positive conversion and saturation calculation unit further includes a polarity judging unit for detecting whether the data provided by the calculating unit and represented as a signed m-bit integer is negative, and a comparator for detecting whether the data exceeds the maximum value, wherein the selection unit a) selects the output of the zero generator when the polarity judging unit has detected that the data provided by the calculating unit is negative, b) selects the output of the constant generator when the comparator has detected that the data provided by the calculating unit exceeds the maximum value, and c) selects the output of the truncating unit when neither the polarity judging unit has detected that the data provided by the calculating unit is negative nor the comparator has detected that the data provided by the calculating unit exceeds the maximum value. 39. The processor of
wherein the positive conversion and saturation calculation unit includes a zero generator for outputting a data having a zero value, and a constant generator for outputting data of the maximum value. 40. The processor of
wherein the positive conversion and saturation calculation unit further comprises a selection unit for a) selecting the output of the zero generator when the data provided by the calculating unit is negative, and b) selecting the output of the constant generator, when the data exceeds the maximum value. 41. The processor of
wherein the selection unit selects one of the output of the zero generator, the output of the constant generator, and a value obtained by truncating the data provided by the calculating unit, when the data provided by the calculating unit is neither negative nor exceeds the maximum value. Description More than one reissue application has been filed for the reissue of U.S. Pat. No. This is a divisional application of U.S. Ser. No. 08/980,676 now U.S. Pat. No. 5,974,540 filed Dec. 1, 1997. 1. Field of the Invention The present invention relates to a processor that performs processing according to instruction sequences that are stored in a ROM or the like. 2. Background of the Invention In recent years, there has been a visible increase in the use of application software that can interactively reproduce various kinds of data, such as video data, still image data, and audio data, that have been compressed according to techniques such as frame encoding, field encoding, or motion compensation. As such software has been developed, there has been increasing demand for multimedia-oriented processors that can efficiently execute the software. These multimedia-oriented processors are processors designed with a special architecture to facilitate programming, such as the compression and decompression of video and audio data. The high-speed processing required for handling video data is the matrix multiplication of compressed data that has N*N matrix elements with coefficient data that also has N*N matrix elements. Representative examples of compressed data that has N*N matrix elements are the luminescence block composed of 16*16 luminescence elements, the blue color difference block (Cb block) composed of 8*8 color difference elements, and the red color difference block (Cr block) composed of 8*8 color difference elements used in MPEG (Moving Pictures Experts Group) techniques. The matrix multiplication for compressed data referred to here is performed very frequently when executing the approximation calculations for an inverse DCT (Discrete Cosine Transform) in image compression methods such as MPEG and JPEG (Joint Photographic Experts Group). The following is a description of conventional multimedia-oriented processors that can perform high-speed matrix multiplication. The basic architecture of conventional multimedia-oriented processors is provided with a sum-product result register (hereinafter simply referred to as an MCR register) as hardware, and is provided with an instruction set that includes a “MOV MCR,**” transfer instruction for transferring a sum-product value. An example of the hardware construction of a conventional multimedia-oriented processor is shown in FIG. When a conventional multimedia-oriented processor is used, however, positive correction saturation operations for amending the sum-product value pose many difficulties for programmers. Positive conversion processing refers to the conversion of a sum-product value that is a negative value into either zero or a positive value. Normally, compressed data is expressed as a coded relative value that reflects the relation of the present value to the preceding and succeeding values. As a result, there are many cases when the sum of products for each element in the compressed data and the corresponding coefficients is a negative value. Most reproduction-related hardware, such as displays and speakers, however is only able to process uncoded data, so that when the sum-product values are to be reproduced, it is first necessary to perform positive conversion processing. Saturation calculation processing refers to processing that sets all values that exceed a given range (or, in other words, which are “saturated”) at a predetermined value. This is to say, when an element that includes an erroneous bit generated during transfer is used in a sum-product calculation as part of the sum-product processing for compressed data, there is an increase in the probability of the sum-product value exceeding a value that can be expressed by the stated number of bits. Since most reproduction-related hardware is only physically capable of reproducing uncoded data with a fixed valid number of bits, such as eight bits, saturation processing is required to convert the sum-product value into a value that can be expressed using the valid number of bits. It has been conventional practice to perform this kind of positive value conversion processing and saturation calculation processing by converting the-sum-product value using a subroutine that corrects the sum-product value. An example of a subroutine that corrects the sum-product value is explained below. In this example, the register width and the calculation width of the calculation unit are 32 bits, with the width of the MCR being 32 bits, and the sum-product value being expressed as a coded 16-bit integer. The data that can be handled by the reproduction-related hardware needs to be expressed using uncoded 8-bit integers. This subroutine is set as using the data register D -
- Instruction 1: MOV MCR,D
**0** - Instruction 2: CMP 0XFFFF
_{—}8000,D**0** - Instruction 3: BCC CARRY
- Instruction 4: MOV 0x0000
_{—}00000,D**0** - Instruction 5: BRA END
- CARRY
- Instruction 6: CMP 0x0000
_{—}00FF,D**0** - Instruction 7: BCS END
- Instruction 8: MOV 0x0000
_{—}00FF,D**0** - END: (end of positive conversion saturation calculation processing)
- Instruction 1: MOV MCR,D
Describing the above instructions in order, Instruction 1, “MOV MCR,D The sixteenth bit of the immediate “0xFFFF On the other hand, when the stored value of the D The letter “B” in the “BCC” in Instruction 3 stands for “Branch”, while the letters “CC” stand for “Carry Clear”. When the comparison in Instruction 2 finds that the stored value of the register D The processing described above is performed when the stored value of the register D The letters “CS” in Instruction 7, “BCS END”, stand for “Carry Set”, so that when the carry flag is set, a branch is performed to the label “END” from Instruction 7. When the carry flag is not set, no branch is performed in Instruction 7 and processing advances to Instruction 8, “MOV 0x0000 The problem with the sum-product value amendment process described above lies in the considerable increase in code size caused by the insertion of the above eight instructions for one amendment of a sum-product value. When the program is written into a ROM to embed the software into the information processing apparatus, the required amount of installed ROM will have to need to be increased by an amount equal to this increase in code size, leading to an increase in manufacturing cost. A large number of manufacturers of domestic appliances such as digital video players, electronic notebooks, and word processors seek to improve on their rivals' products by using their own decompression processing programs, although the installation of such decompression processing programs presently has the drawback of increasing costs by increasing the required amount of ROM, making such installation problematic. There is also the problem that since eight instructions need to be executed to correct one sum-product value, there is a large increase in processing time. When, as shown in The same sum-product processing and positive conversion saturation calculation processing is required to obtain the other matrix multiplication result elements H In order to increase the speed of the matrix multiplication, it is possible to install a specialized circuit for performing matrix multiplication. However, if all of the matrix multiplications are performed by a specialized circuit, there would be a vast increase in hardware, and the processor characteristic known as versatility, whereby the processor executes a variety of processes in accordance with the program written by the programmer, is lost. If the versatility of the processor is lost, there is the risk that the processor will not be able to respond to programmers' wishes, and so will not, for example, be able to execute an original decompression processing program. It is a primary object of the present invention to provide a processor that can perform a rounding process made up of a positive conversion process and a saturation calculation process at high speed, while minimizing the increase in code size caused by the rounding process. The stated object can be achieved by a processor that successively decodes and executes instructions in an instruction sequence, the instruction sequence including instructions that indicate a storage address of a value used in an operation, the processor including: a detecting unit for detecting whether a next instruction to be decoded includes an operation content indication showing that the next instruction is a correction instruction and, if present, reading the operation content indication; and a rounding unit for rounding, when the detecting unit has detected an operation content indication showing that the next instruction is a correction instruction, a coded m-bit integer stored at a storage address indicated by the instruction to a value expressed as an uncoded s-bit integer (where s<m). With the stated construction, the processing for rounding values is performed once each time a correction instruction is detected out of the instruction sequence, so that the rounding process can be executed by the programmer writing only one instruction. As the rounding process is performed according to one correction instruction, the execution time for one execution of the rounding process is extremely short. When the rounding of calculated values is required very often, such as when decompressing data, there will not be a significant increase in the time taken by the decompression processing. Since the rounding process can be performed by simply executing a correction instruction, when the processor attempts to perform a sum-products operation at high speed through pipeline processing, thee will be no confusion in the pipeline. Accordingly, the code size of the instruction sequence can be reduced and the execution of the instruction sequence made faster by adding a small amount of hardware to the processor. The stated object can also be achieved by a processor that successively decodes and executes instructions in an instruction sequence, the instruction sequence including instructions that indicate a storage address of a value to be used in an operation, the processor including: a first detecting unit for detecting whether a next instruction to be decoded includes an indication showing that the instruction has a calculation performed; a second detecting unit for detecting whether the next instruction to be decoded includes an indication showing that calculation is to be performed and that rounding is-to be performed on a calculation result; a calculating unit for performing, when the first detecting unit detects that the next instruction includes an indication showing that the instruction has a calculation performed, a calculation using an m-bit integer in accordance with the indication; and a rounding unit for rounding, when the second detecting unit has detected that the next instruction to be decoded includes an indication showing that rounding is to be performed, a calculation result of a calculation that uses an m-bit integer to a value expressed as an uncoded s-bit integer (where s<m). With the stated construction, correction instructions for performing a rounding process of a coded calculation result are provided, so that the two processes composed of a calculation process and a rounding process can be performed in a single step. As a result, positive conversion saturation calculation processing is performed in the same step as the calculation processing, so that the effective number of steps taken the positive conversion saturation calculation processing is zero. These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings which illustrate a specific embodiment of the invention. In the drawings: First Embodiment The following is an explanation of the first embodiment of the present invention with reference to the drawings. The RAM ROM In the present embodiment, the decompression processing program includes a matrix multiplication subroutine that generates the matrix multiplication result Hij with 8*8 elements by multiplying the compressed data Fij composed of 8*8 matrix elements by the coefficient data Gij composed of 8*8 matrix elements. It should be especially noted that this matrix multiplication subroutine is mainly composed of sum-product function multiplication instructions “MACCB Dm,Dn” and positive conversion saturation calculation instructions “MCSST Dm”. The following is a description of the generation of the matrix Hij with 8*8 elements by multiplying the compressed data Fij (i,j=1,2,3,4,5 . . . 8) composed of 8*8 matrix elements by the coefficient data Gji (i,j=1,2,3,4,5 . . . 8) also composed of 8*8 matrix elements. When doing so, the calculation shown in Equation 1 below is necessary to calculate the 1 This Equation 1 has Gji*Fij (i,j=1,2,3,4,5 . . . 8) as its elemental operations and is a compound operation which finds an algebraic sum of the elemental operations. The calculation of the respective elemental operations and the calculation of the algebraic sum are expressed in the present matrix multiplication subroutine by a loop statement (this loop statement being called a “sum-product loop”) that repeatedly has a sum-product function multiplication instruction “MACCB Dm,Dn” performed. As a result of the transfer instructions mentioned above, the address registers A Instruction 4, “MOV INIT,D Instruction 9, “BCS LP1_NEXT” is a conditional branch instruction that branches to instruction 13 “ADD 1,D Instruction 10, “MCSST D Instruction 13, “INC D The label LP1_START is attached to instruction 5, “MOV (A The label LP1_NEXT is attached to instruction 13, “ADD 1,D The field indicating the read address of the multiplier and the field indicating the read address of the multiplicand can each be set at one of “00”, “01”, “10”, and “11”, thereby indicating one of data register D The one-bit field for indicating the calculated content of the elementary operation shows the content of the calculation of the elementary operation performed for the multiplier Gji and the multiplicand Fij. When “1” is written into this field, the multiplication “Gji*Fij” of the multiplier Gij and the multiplicand Fij is indicated as the content of the elementary operation on the multiplier Gji and the multiplicand Fij. When the one-bit field indicating the storage address of a sum-product value is set at “1”, this indicates that the MCR (the sum-product result register When the sum-product operation “G The format of the operation codes for the positive conversion saturation calculation instruction “MCSST Dm” is shown in FIG. As described above, the decompression processing program stored in the ROM This completes the description of the instruction sequences stored in the ROM The instruction fetch circuit The decoder (1) Register output control refers to a controlling of the operation execution apparatus The address bus The operation execution apparatus It should be especially noted here that the construction is such that the instruction fetch circuit This completes the description of the constructional elements of the processor. The following description will focus on the internal construction of the operation execution apparatus The register file The first internal bus The second internal bus The code extension circuit The code extension circuit The ALU circuit When a sum-product function multiplication instruction “MACCB Dm,Dn” is decoded, the ALU circuit It should be noted here that when the sum-product function multiplication instruction “MACCB D The sum-product result register The positive conversion saturation calculation circuit The middle part of The lower part of In It should be noted here that the range of values that can be used the sum-product value is a range of 15-bit positive and negative values to avoid the totaling of rounding errors. In more detail, when the sum-product value is found from the multiplication result of the multiplier Gji and the multiplicand Fij which are both coded 8-bit values, if the multiplication result were to be rounded to eight bits every time because the range of the multiplication matrix element Hij is eight bits, the rounding error would increase every time multiplication is performed. To avoid such increases in rounding error, the sum-product result register The stored value of the sum-product result register The positive conversion saturation calculation circuit The internal construction of the positive conversion saturation calculation circuit When the instruction read by the instruction fetch circuit The comparator When a carry is detected as the result of the subtraction described above and the latched value is judged to exceed the maximum value, the comparator The polarity judging unit When the indication in the positive conversion-saturation calculation width field of the positive conversion saturation calculation instruction “MCSST” is for a 24-bit uncoded value, the polarity judging unit The zero generator The multiplexer If the logic value outputted by the comparator As shown in When the output value of the comparator When the output value of the comparator In The multiplication of the 32-bit held value “0x0000 The following is a description of the operation of the processor constructed as described above. A transfer instruction included in the matrix multiplication subroutine is first written into the instruction buffer of the decoder The next instruction in the matrix multiplication subroutine is instruction 7 which is the sum-product function multiplication instruction “MACCB D When the sum-product function multiplication instruction “MACCB D Once the sum-product result register After the read addresses have been incremented, the following instruction, instruction 16:“BRA LP1_START” is decoded. The branch address of instruction 16:“BRA LP1_START” is instruction 5:“MOV(A As a result of these transfer instructions, the 2 In the matrix multiplication subroutine, these transfer instructions are followed by the sum-product function multiplication instruction “MACCB D When the sum-product function multiplication instruction “MACCB D Since the held value of the same-product result register Once the addition of the held value “G The processing described above is repeated for all of the elements on the first row of the coefficient data Gji and all of the elements in the first column of the compressed data Fij, so that the sum-product value is calculated for “G After this, the next loop statement in the ROM When the positive conversion saturation calculation instruction “MCSST D The polarity judging unit In the present case, the maximum value “0x0000 According to control by the decoder When the sum-product has been completed for all of the elements in the first column of the compressed data matrix Fij and the elements on the first row of the coefficient matrix Gji, the sum-product processing is performed for the elements in the second column of the compressed data matrix Fij and the elements on the first row of the coefficient matrix Gji. When the calculation of “G Here, if there is a bit error when transferring the element F After this, the next loop statement in the ROM When the positive conversion saturation calculation instruction “MCSST D The polarity judging unit In the present case, the maximum value “0x0000 According to control by the decoder By repeating the above processing and writing in the remaining elements in the matrix multiplication table, the matrix multiplication table is written into the RAM On the other hand, when the carry flag is set at “OFF”, the decoding stage of instruction 10:“MCSST D In this way, even if the processor provided in the positive conversion saturation calculation circuit With the present embodiment described above, the positive conversion saturation calculation processing of sum-product values is performed by subjecting the sum-product value accumulated in the sum-product result register The positive conversion saturation calculation processing for the sum-product value is such that the positive correction processing and the saturation calculation processing are performed at the same time for the held value of the sum-product result register Since the positive conversion saturation calculation processing performed by the positive conversion saturation calculation circuit Since positive conversion saturation calculation processing is performed without installing a specialized circuit for matrix multiplication, there is no loss in versatility for the processor. Accordingly, should a user wish to control the processor according to an original decompression processing program, this is still possible. Applied Example for the First Embodiment In this example, one of the data registers D By writing one of “11”, “00”, “10”, and “01” into the storage address indication field, one of the sum-product result register The instruction format of this positive conversion saturation calculation instruction “MCSST” has been amended so the internal construction of the operation execution apparatus The path C In the same way, the path C The selector The path C By making the simple addition described above, the functioning of the positive conversion saturation calculation instruction “MCSST” can be extended in the present embodiment. Second Embodiment The second embodiment of the present invention executes positive conversion saturation calculation processing for a multiplication result when multiplication is performed by the ALU circuit A “MULBSST Dm,Dn” instruction is a multiplication instruction that indicates that the multiplication result should be further subjected to positive conversion saturation calculation processing. In other words, multiplication is performed using the lower 8 bits of the Dm register and the Dn register, and the positive conversion saturation calculation circuit By writing one of “01”, “10”, and “11” into the positive conversion saturation calculation processing field, it is possible to specify that the positive conversion saturation calculation processing with a rounding width of a 24-bit positive number, a 16-bit positive number, or an 8-bit positive number. By writing one of “00”, “01”, “10”, and “11” into the multiplier read address indicating field and the multiplicand read address indicating field, any of the data register D When executing the positive conversion saturation calculation function multiplication instruction “MULBSST Dm,Dn”, the register file The following is an explanation of the operation of the above processor based on a matrix multiplication subroutine. First, a transfer instruction included in the matrix multiplication subroutine is written into the instruction buffer of the decoder In the matrix multiplication subroutine, the positive conversion saturation calculation function multiplication instruction “MULBSST D When the positive conversion saturation calculation function multiplication instruction “MULBSST D When the decoder The polarity judging unit In the present case, the constant generator According to control by the decoder By means of the second embodiment described above, a calculation instruction that performs saturation calculation processing and positive conversion processing on the coded calculation result is provided, so that three types of processing composed of calculation processing, positive conversion processing, and saturation calculation processing can be performed in one step, meaning that positive conversion saturation calculation processing is performed in the same step as the calculation processing. As a result, the effective number of execution steps required by positive conversion saturation calculation processing is reduced to zero. It should be noted here that this second embodiment has been described as performing a rounding process for an uncoded 8-bit width, although the maximum number can be freely set at any positive integer. Although the present invention has been fully described by way of examples with reference to accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. Therefore, unless such changes and modifications depart from the scope of the present invention, they should be construed as being included therein. Patent Citations
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