|Publication number||USRE39274 E1|
|Application number||US 10/621,555|
|Publication date||Sep 12, 2006|
|Filing date||Jul 16, 2003|
|Priority date||Feb 5, 1999|
|Also published as||EP1026689A2, EP1026689A3, EP1026689B1, EP1026689B8, US6300810|
|Publication number||10621555, 621555, US RE39274 E1, US RE39274E1, US-E1-RE39274, USRE39274 E1, USRE39274E1|
|Inventors||Kim C. Hardee|
|Original Assignee||United Microelectronics Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Non-Patent Citations (1), Referenced by (4), Classifications (7), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims benefit of provisional application No. 60/118,736, filed Feb. 5, 1999.
1. Field of the Invention
The present invention relates, in general, to integrated circuits and, more particularly, to integrated circuits having voltage regulator circuits generating an internal power supply voltage from an external power supply voltage.
2. Relevant Background
Integrated circuits (ICs) comprise thousands or millions of individual devices interconnected to provide desired functionality. Significant effort is expended to improve processing techniques so as to reduce the size of each individual device in order to provide greater functionality on a given IC chip at reduced cost. In general, smaller geometry devices operate faster while dissipating less power than do larger geometry devices. As device geometries are reduced the breakdown voltages of the devices and the isolation that separates the devices decreases also.
Electronic systems usually comprise ICs manufactured with a variety of technologies. This has created a need for multiple power supply voltages to be supplied to a single printed circuit board to support the various types of devices on that board. For example, devices are available that require a power supply voltages ranging from 5.0 volts to 2.5 volts. A practical solution to this disparity is to provide voltage down converter circuitry that decreases the higher voltage (e.g., 5.0 V in the above example) to the lower voltage required internally by the small geometry device (e.g., 3.3 V or 2.5 V). Hence, it is necessary to regulate the available external power supply voltage to provide voltages consistent with that required internally by each of the small geometry ICs.
To limit undesirable volt age droop on the internal voltage supply node during high current loads, a large capacitor is coupled between the internal voltage supply nod e and ground. In practice, however, filter capacitors consume a great deal of area without adding functionality. Cost and circuit size considerations dictate limiting the filter capacitor to more modest sizes. Hence, it is desirable to minimize voltage ripple in ways that do not require large filter capacitors.
A conventional voltage down converter (also called regulators and DC/DC converters) is designed to generate a lower voltage than the available supply voltage In a linear regulator, a transistor is coupled in series between the external voltage supply node and the internal voltage supply node. The conductivity of the transistor is modulated to drop the excess voltage across the transistor. Linear regulators have many desirable characteristics such as simplicity, low output ripple, high quality line and load regulation, and fast recovery time. However, linear regulators are inefficient resulting in wasted power and excess heat generation.
Pulse width modulation (PWM) regulators are becoming more common because of their higher efficiency. A PWM down converter compares the voltage on the internal voltage supply node to a reference voltage to generate a PWM signal that is on (i.e., a logic high) when the internal supply voltage is too low, and off (i.e., a logic low) when the internal supply voltage is too high. The PWM signal controls the transistor coupled in series between the external voltage node and the internal voltage supply node. The series transistor operates primarily in either the on or off state where power losses are smallest (as compared to the linear region where power loss is greater).
The comparator used in conventional PWM regulators to compare the reference voltage to the internal supply voltage has a time delay before its outputs react to a change in the internal supply voltage. This delay is manifested as drooping and overshoot in the internal supply voltage, particularly under high current loads. In a memory device, for example, thousands of sense amplifiers are activated simultaneously creating periodic high current loads. This is complicated in light of a trend towards smaller transistors in the voltage down converter as well as smaller filter capacitors. Moreover, as more memory cells are placed on a single integrated circuit the interconnect lines become smaller, more resistive, and greater in number all of which lead to greater demand on the circuitry generating the internal supply voltage.
A technique used to minimize voltage droop in external (i.e., off-chip) down converters employs a hysteretic comparator to compare the converter output voltage to a reference voltage. However, it is difficult to generate accurate hysteresis using off-chip components that do not have direct access to the internal voltage supply levels that must be regulated. Although this limitation can be overcome by bringing the internal supply voltage out to a pin of the IC, this solution degrades the system's noise performance as well as raises the cost to manufacture the device. Moreover, the load capacitance created by the pins is significant making the design more complex in addition to degrading the overall performance device. A need exists for a voltage down converter that can be implemented on-chip with improved resistance to droop and overshoot in high load applications.
The present invention involves a voltage down converter with hysteresis generator combining a hysteresis signal to a reference voltage and an output voltage feedback signal applied to a comparator. The hysteresis generator is coupled to a control signal giving advance notice of when a high current load is to be activated. The hysteresis signal is switched to a first state prior to the high current load activation, and switched to a second state prior to the high current load being deactivated. In the first state, the hysteresis voltage is added to a reference voltage. In the second state, the hysteresis voltage is added to the voltage output feedback signal.
The present invention involves a voltage down converter including an input node receiving an external voltage and a driver unit selectively coupling the input node to an internal voltage supply node in response to a drive control signal. A hysteresis timing unit responsive to an external control signal generates a first control signal VHYST− and a second control signal VHYST+. A comparator unit is coupled to the internal voltage supply node, VREF, VHYST− and VHYST+ and coupled to the driver unit to generate the drive control signal. The comparator unit has a first mode, a second mode, and a third mode selected by the VHYST− and VHYST+ signals.
The voltage down converter in accordance with the present invention is illustrated in block diagram form in FIG. 1. It should be understood that the implementations shown in FIG. 1-
A four-input hysteresis comparator 101 produces a control signal on line 105 that is coupled to a driver unit 103. Driver unit 103 supplies current from the external power supply voltage VCCEXT in response to the control signal to charge filter capacitor 106. To converse power, the major power consuming components of the down converter are desirably selectively enabled by the VDCEN control signal.
The output voltage VCCI is controlled by comparing a reference voltage (VREF) to VTRIM. VREF is generated in a conventional manner using voltage generating components such as a band gap reference circuit that provides a suitably stable reference voltage. VTRIM is derived from VCCI by VTRIM generator 104. Conveniently, VTRIM is set to one half VCCI, although any value may be selected. VTRIM generator 104 may comprise a simple voltage divider circuit, for example.
Ignoring the effects of hysteresis timer 102 for the moment, in a particular example the output of comparator 101 (i.e., line 105 in
Comparator 101 includes a VHYST− and a VHYST+ control signals that indicate when a hysteresis voltage is to be added or subtracted by comparator 101. When the VHYST− signal is active, a hysteresis voltage is effectively added to VTRIM thereby causing comparator 101 to turn off when VCCI rises to slightly below the target VCCI. Similarly, when the VHYST+ signal is active, a hysteresis voltage is effectively added to VREF thereby causing comparator 101 turn on when VCCI falls to slightly above the VCCI target. Hysteresis timer unit 102 generates VHYST− and VHYST+ control signals using an externally generated timing signal such as VDCPRE shown in FIG. 1. Although VDCPRE is referred to as externally generated, this means that it is generated externally to comparator 101—it should be understood that VDCPRE is preferably generated by control circuitry on the same IC as comparator 101. In a particular implementation, VDCPRE is a control signal in a memory device that goes high prior to sensing and then goes low shortly after sensing has begun. Other control signals may be useful to generate VHYST− and VHYST+ and such control signals are equivalent to the specific example provided herein.
Coupled in parallel with input transistor 302 is a series combination of transistors 303 and 304. Transistor 303 is controlled by the VHYST− signal. Transistor 304 is coupled to the VREF signal and so will conduct a constant current whenever VHYST− and VDCEN are on. Hence, when VHYST− is on, the differential comparator is imbalanced and behaves as if VTRIM were higher than it actually is. As a result, the output at node 105 will switch from low to high whwn VTRIM is slightly (e.g., 0.2 volts in a particular example) below VREF. In operation, VHYST− is active when an overshoot is expected such as when sense amplifiers in a memory circuit are being turned off. In this manner, when an overshoot condition occurs or is expected, driver 103 begins to turn off at a VCCI level lower than the target level so that it is substantially off when VCCI reaches the target level. In this manner, VCCI does not rise above acceptable levels.
Coupled in parallel with input transistor 312 is a series combination of transistors 313 and 314. Transistor 313 is controlled by the VHYST+ signal. Transistor 314 is coupled to the VREF signal and so will conduct current whenever VHYST+ and VDCEN are on. Hence, when VHYST+ is on, the differential comparator is imbalanced and behaves as if VREF were higher than it actually is. As a result, the output at node 105 will not switch from high to low until VTRIM is slightly (e.g., 0.2 volts in a particular example) above VREF. In operation, VHYST+ is active when a droop is expected such as when sense amplifiers in a memory circuit are being turned on. In this manner, when an high load condition occurs or is expected, driver 103 turns on at a higher VCCI level than the target level to couple charge to filter capacitor 106 so that filter capacitor 106 can supply the high load current without allowing VCCI to fall below acceptable levels.
The voltage at which the output of comparator 100 101 switches is referred to as the “trip-point”. The trip-point is centered at VREF as shown in FIG. 4. The hysteresis voltage (indicated by ΔV in
Likewise, NOR gate 503 should be driven from VCCEXT to ensure full turn on of transistor 303 shown in FIG. 3. The signal on node 105 is logically combined with the voltage translated output of voltage shift unit 502 by NOR gate 503 to generate the VHYST− signal. Again, care should be taken to ensure that any delays associated with NOR gate 502 provide acceptable timing margin for the turn on of transistor 303 when VDCPRE indicates that a high current load is being turned off.
As VDCPRE and VHYST+ fall just after time 15, VHYST− goes high to turn on transistor 303 shown in FIG. 3. Again, the VHYST− timing is selected to anticipate the voltage overshoot condition that occurs when the high current load is turned off. In response to VHYST− going high and VTRIM rising to a voltage just below VREF, VDRIVE falls just before time 20 thereby turning off driver 103. As a result the VCCI waveform is markedly flatter and consistently near to the target VCCI specification throughout the high load current switching event using the method and apparatus in accordance with the present invention.
Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.
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|U.S. Classification||327/206, 327/536, 327/540|
|International Classification||H03K3/356, G11C5/14|
|Feb 6, 2007||CC||Certificate of correction|
|Apr 5, 2009||FPAY||Fee payment|
Year of fee payment: 8
|Feb 27, 2013||FPAY||Fee payment|
Year of fee payment: 12