|Publication number||USRE39518 E1|
|Application number||US 09/908,390|
|Publication date||Mar 13, 2007|
|Filing date||Jul 18, 2001|
|Priority date||May 28, 1997|
|Also published as||US5926690|
|Publication number||09908390, 908390, US RE39518 E1, US RE39518E1, US-E1-RE39518, USRE39518 E1, USRE39518E1|
|Inventors||Anthony John Toprac, Douglas John Downey, Subhash Gupta|
|Original Assignee||Advanced Micro Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (6), Referenced by (16), Classifications (7), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to semiconductor fabrication methods. More precisely, the present invention relates to a control system used in semiconductor fabrication for controlling feature critical dimensions.
2. Description of the Related Art
Two aspects of feature sizes are controlled in a lithographic and etch process. The first aspect is a critical dimension, the absolute size of a feature, including linewidth, spacing or contact dimensions. The second aspect is the variation in feature size across the wafer surface as measured by steps of a wafer stepper. Linewidth and spacing measurements are regularly performed to determine the actual sizes of critical dimensions at each masking level of a process.
Another aspect of linewidth control is that correct feature sizes are to be maintained across an entire wafer and also maintained from wafer to wafer. As a feature size is reduced, the tolerable error on feature size control is also reduced. When an exposure is performed by a wafer stepper, the feature size is controlled across every exposure field and field-to-field variations are to be held within specified limits.
Linewidth control is affected by many factors including fabrication tools and equipment, process recipes, and raw materials. Critical dimensions are analyzed by measuring fabricated test structures with nominal feature sizes at many positions of a wafer. The measurement results are then plotted as a function of location to determine critical dimension variation.
Linewidth control and control of critical dimensions is largely determined by specific characteristics of the steps of photoresist processing. Photoresist processing typically includes steps of substrate cleaning, dehydration baking and priming, spin coating, soft-baking or pre-baking, exposure, post-exposure treatment, a photoresist develop step, inspection following development, plasma de-scumming, post-baking, etching, deep ultraviolet hardening of photoresist, and stripping of the photoresist. Many of these steps are very important for determining linewidth control and control of critical dimensions. For example, dehydration baking and priming assures adhesion of the photoresist during processing. Poor adhesion can cause a loss of linewidth control including the entire loss of pattern elements in extreme cases.
The coating process including resist formulation, spinner type, wafer size, spin parameters, and ambient temperature during deposition determine the thickness variation across a wafer which, in turn, influences the critical dimensions across the wafer. Contamination with airborne particles and air bubbles can occur during the coating step. The soft-baking step can lead to wafer-to-wafer variations in critical dimensions since, for example, solvent vapors can coat infrared soft-baking lamps changing the energy output.
Exposure of the photoresist is a critical step in the resist processing procedure for several reasons. First, exposure is a step in which wafers are processed individually, leading to possible wafer-to-wafer variations in exposure. Second, the results of the exposure are highly dependent on photoresist thickness so that differences in coating thickness arising in the photoresist coating step are amplified during exposure.
Critical dimensions are conventionally tested by randomly sampling one wafer or a few wafers of a lot or multiple lots of processed wafers on post-develop inspection. If a sampled wafer is found to have critical dimensions that are outside specifications, another sample from the lots of processed wafers may be tested. If the subsequent test results in critical dimensions outside specified values, many wafers may be remeasured. If the critical dimensions are consistently outside the specification limits, the lot or entire group of lots are stripped of photoresist and reprocessed through the photolithography process.
The critical dimensions of polysilicon gates affect many operating parameters of integrated circuits, but fundamentally the greatest considerations of critical dimensions is speed performance and power consumption of a circuit. The smaller this critical dimension, the faster the operation of the transistor and the integrated circuit as a whole. Too small a polysilicon gate critical dimension, however, results in unacceptably high power consumption and parasitic currents in the transistor. An optimal operating point for this critical dimension is therefore defined by these countervailing effects. Thus, the narrower the distribution of critical dimension values centered about the optimal critical dimension in a lot of wafers, the more high speed, functional circuits are produced. Unfortunately, the critical dimensions resulting from conventional manufacturing methods are rarely optimum, resulting in reduced yield of high performance circuits. Furthermore, the conventional process is very wasteful when process conditions are substandard.
What is need is a technique for reducing polysilicon gate linewidth variability and controlling the process at, or very near, the optimal linewidth value. What is further needed is a technique for reducing lot average critical dimensions in a polysilicon gate etch process without negatively impacting other parameters such as uniformity and line shape.
It has been discovered that all causes of critical dimension variation, both known and unknown, are compensated by adjusting the time duration of a photoresist etch. Accordingly, a control method employs a control system using photoresist etch time as a controlling variable in either a feedforward or a feedback control configuration to control critical dimension variation during semiconductor fabrication. By controlling critical dimensions through the adjustment of photoresist etch time, many advantages are achieved including a reduced lot-to-lot variation, an increased yield, and increased speed of the fabricated circuits. In one embodiment these advantages are achieved for polysilicon gate critical dimension control in microprocessor circuits.
In accordance with an embodiment of the present invention, polysilicon gate linewidth variability is reduced using a control method using either feedforward or feedback. In some embodiments, feedback control is implemented for controlling critical dimensions using photoresist etch time as a manipulated variable. In an alternative embodiment, critical dimensions are controlled using RF power, gas flow rates, chamber pressure, and/or other recipe variables as manipulated variable(s).
In accordance with an embodiment of the present invention, a run-to-run control technique is used to drive the critical dimensions of integrated circuits to a set specification. In a run-to-run control technique a wafer test or measurement is made and a process control recipe is adjusted based on the result of the test or measurement on a run-by-run basis.
In accordance with a further embodiment of the present invention, the run-to-run control technique is applied to drive the critical dimensions of a polysilicon gate structure to a target specification.
In accordance with a yet further embodiment of the present invention, the run-to-run control technique is applied to drive the critical dimensions in an integrated circuit to a defined specification using photoresist etch time as a manipulated variable.
Many advantages are achieved by the described process control method. One advantage is that the control of critical dimension uniformity is substantially improved by the described process. It is also highly advantageous that the described method improves manufacturability as well as control.
The features of the described embodiments believed to be novel are specifically set forth in the appended claims. However, embodiments of the invention relating to both structure and method of operation, may best be understood by referring to the following description and accompanying drawings.
In overview, the fabrication process 100 involves selection of one or more test wafers, called “pilot” wafers from an entire lot of wafers. The pilot wafers are tested to characterize the lot of wafers, processed through the photoresist etch step 106 using a nominal, average, or moving average processing recipe, and measured in a Final Inspection Critical Dimensions step 108. The results from the pilot lot tests are applied to update a process model 114 which is used to adjust the etch recipe for the remaining wafers in the lot to drive their critical dimensions to the target values. In the illustrative embodiment, scanning electron microscopy (SEM) measurements are made to determine changes in the etch recipe for the remainder of the lot, adjusting the average critical dimension toward a current target critical dimension.
The fabrication process 100 of the illustrative embodiment first under-exposes a wafer 102 to initially produce critical dimensions that are larger than target critical dimension values so that the photoresist etch time is subsequently varied during the photoresist etch step 106 to control driving of the critical dimensions to the target value. In one embodiment, the step of under-exposing the wafer 102 involves exposing the wafer to less energy, typically 5 to 15 milliJoules (mJ) less energy, than is used in the nominal process.
In a Develop Inspection Critical Dimensions (DICD) step 104, the critical dimensions are measured for some of the wafers following the develop step of the photoresist processing procedure. Measurements performed during the Develop Inspection Critical Dimensions (DICD) step 104 are typically inaccurate by nature relative to the Final Inspect Critical Dimension (FICD) measurement. DICD measurements are relatively noisy and often do not reflect important process variations in the photolithography process. In the illustrated method, the Develop Inspection Critical Dimensions step 104 involves measurement of critical dimensions for three “pilot” wafers in a lot of 24 wafers. In other embodiments of the fabrication process 100 more or fewer wafers may be tested to characterize a full lot of wafers. A single wafer may be tested. The greater the number of tested “pilot” wafers, the better the characterization of the lot remainder.
The wafers measured in the Develop Inspection Critical Dimensions step 104 are etched in the photoresist etch step 106 with the etch time set to a nominal photoresist etch time that is based on the initial, average, or moving average operating conditions of the fabrication process 100. The photoresist etch procedure advantageously improves across-wafer uniformity according to FICD measurements, including improvement of the critical dimension ratio for dense and isolated gate structures.
The initial or average operating conditions are set according to the original state of the process model 114. In one embodiment, the nominal etch time is set as an average of the exponentially-weighted moving average of the current photoresist etch times.
Following the photoresist etch step 106, the polysilicon gates are etched, the pilot wafers are stripped and cleaned, and the critical dimensions of the etched wafers are measured in a Final Inspection Critical Dimensions (FICD) step 108. Measurements resulting from the Final Inspection Critical Dimensions (FICD) step 108 more accurately reflect the critical dimensions than DICD measurements generally because the photoresist, which resolves relatively poorly in a scanning electron microscope, is stripped from the wafer for the FICD measurement.
Various measurement techniques may be used for the Develop Inspection Critical Dimensions step 104 and the Final Inspection Critical Dimensions step 108 including scanning electron microscopy (SEM), mechanical measurement techniques, image shearing, and reflectance measurements. Scanning electron microscopy is highly accurate for measuring line widths. A scanning electron microscope uses an electron beam as an illumination source which is scanned over a wafer surface. Impinging electrons from the illumination cause ejection of electrons from the wafer surface. The ejected electrons are collected and translated into a picture of the surface of the wafer on a screen or photograph.
Once the measurements are acquired in the Develop Inspection Critical Dimensions step 104 and the Final Inspection Critical Dimensions step 108, measurement data is added to a database including a DICD database and an FICD database.
Measurements acquired during the Develop Inspection Critical Dimensions step 104 are filtered in a filter DICD step 110 and the filtered measurements are applied to the process model 114 to supply a feed forward control of critical dimensions. Similarly, measurements acquired in the Final Inspection Critical Dimensions step 108 are filtered in a filter FICD step 112 and applied to the process model 114 to supply feedback control of critical dimensions. In some embodiments or some applications, only feedback control of critical dimensions is employed using feedback of the FICD measurements. In other embodiments or other applications, feedforward control of critical dimensions is implemented using feedforward of DICD measurements in conjunction with feedback control from FICD measurements. The filter DICD step 110 and the filter FICD step 112 are used for averaging or smoothing of the data for removal of measurement noise such as random noise and measurement variability. In one embodiment, both the filter DICD step 110 and the filter FICD step 112 are performed using an exponentially-weighted moving average filter.
In the process model 114, the critical dimension measurements for the pilot wafers are used to determine a proper value for the manipulated variable, the photoresist etch time, and applied to the remaining wafers in the lot. The process model 114 determines the extent that the final inspection critical dimensions differ from the FICD target value and changes the photoresist etch time for the remainder of the lot of wafers. In addition, the value of the average etch time may be updated using the updated or changed new value of etch time. The process model 114 is updated to establish a quantitative relationship between the manipulated variable, photoresist etch time in the illustrative embodiment, and the etched polysilicon gate critical dimensions. The process model 114 is updated by adjusting one or more model parameters such that the latest value of photoresist etch time, when input to the model, gives a model prediction for FICD value which is the same as the measured FICD value resulting from the given photoresist etch time. The measurements acquired during the Develop Inspection Critical Dimensions step 104 are typically not sufficiently accurate and reliable for sole usage in controlling the fabrication process 100 although the measurements are useful for predictive modeling at the early stages of the process model 114.
The operation of the process model 114 is shown graphically in
In the illustrated embodiment, the process model 114 is updated using the measurement of final inspection critical dimensions and the photoresist etch time used for the pilot test wafers. The updated model is used to predict an effective photoresist etch time to improve critical dimensions for the remaining 24 wafers of the 24 wafer lot. Following etching of all wafers in a lot, the Final Inspection Critical Dimensions step 108 measures the critical dimensions of the remaining wafers in the lot and the process model 114 is updated according to the measurements of the remaining wafers. If a plurality of wafer lot runs are processed, the process model 114 may be continually updated for the series of runs depending on the results of the tests. For example, the fabrication process 100 may be controlled so that the model is either updated or unchanged between runs. Furthermore, the manipulated variable may be set by external adjustment.
In one embodiment, the process model 114 uses a quadratic relationship between the critical dimensions and the photoresist etch time. A polynomial function for the critical dimensions is shown in equation (3), as follows:
which may be solved by iterative methods or by using the quadratic formula, shown in equation (4) as follows:
The quadratic relationship is used for modeling various physical phenomena, reverting to a linear relationship for lateral etches and remaining in a quadratic form for isotropic vertical etches. In this embodiment, the c parameter in the quadratic relationship is used to center the relationship between the final inspection critical dimensions and the photoresist etch times. By setting the c parameter, the process model 114 sets the model through a current average operating point which is indicative of the characteristics of the wafers, the etch chamber, and the process in general. Once the current average operating point of the process is set, the model presumably reflects the actual current state of the process, wafers and chamber so that any difference between the final inspection critical dimensions and the target FICD values reflects the amount of time the photoresist etch time is to be changed to drive measured FICDs to the target value.
In some embodiments, the c parameter is derived from the DICD measurement which is supplied using feedforward control of the process model 114. The c parameter is used in this manner as an adjustable constant. In some embodiments, the value of c used to update the model is the value of c determined as described above and then averaged or filtered using the exponentially weighted moving average or other filtering method to “smooth” variations in the c parameter.
In an alternative embodiment, the process model 114 is developed based on the sidewall angle of photoresist lines, which is depicted in a cross-sectional view in FIG. 3. In the alternative process model 114 the difference between the Develop Inspection Critical Dimensions step 104 and the Final Inspection Critical Dimensions step 108 is developed, shown in equation (5) as follows:
where DICD is the develop inspection critical dimensions, FICD is the final inspection critical dimensions, CB is the chamber bias, ER is the etch rate, ET is the etch time, and Θ0 is the initial sidewall angle of the photoresist. The initial sidewall angle of the photoresist Θ0 may be a measured parameter. The relationship shown in equation (5) reduces to the quadratic form or equation (3) to attain a very good approximation for small angles Θ such that tan Θ is approximately equal to Θ. Preliminary studies have shown that usage of the polynomial function as shown in equation (3) and (4) produces a more stable model than usage of a function according to equation (5).
The fabrication process 100 uses feedback control of the process recipe using run-by-run control to control critical dimensions. In particular, photoresist etch time is varied depending on the measurement of wafers which were previously processed. In an alternative embodiment, critical dimensions are controlled using radio frequency power as a control variable. Generally, embodiments using photoresist etch time as the control variable advantageously provide more stable control of critical dimensions without unwanted process side-effects.
In an alternative embodiment, a plurality of pilot wafers are tested with each pilot wafer representing a “split” of wafers. In one example, a lot of 24 wafers is divided into three splits with each split containing eight wafers. One pilot wafer is assigned for each of the three splits. In the step of under-exposing the wafer 102, the splits are processed separately using a different exposure energy to produce three levels of DICD measurements. The range of DICD measurements is determined based on the range of acceptable values of the manipulated variables, for example the photoresist etch times, and constraints of the process model 114.
While the invention has been described with reference to various embodiments, it will be understood that these embodiments are illustrative and that the scope of the invention is not limited to them. Many variations, modifications, additions and improvements of the embodiments described are possible. In various embodiments of the critical dimension control procedure, the method may be practiced in a manual or automatic form. For example, a software system may be used to automate the entire critical dimension control loop.
In an alternative implementation of a critical dimension control procedure, a Bottom Anti-Reflective Coating (BARC) etch step is implemented prior to etching of polysilicon or other substrates. The BARC process is used to improve a photolithography process by reducing the stray light photoresist exposure from reflections off a substrate, such as polysilicon. A BARC process involves the formation of an anti-reflective coating beneath the photoresist layer but overlying the polysilicon layer. The BARC layer is etched before the polysilicon is exposed for etching.
In an embodiment of a critical dimension control procedure for an implementation of the photoresist processing procedure using a BARC etch step, the BARC etch time may be used as a control variable for controlling critical dimensions, rather than usage of photoresist etch time as the control variable.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5629772 *||Dec 20, 1994||May 13, 1997||International Business Machines Corporation||Monitoring of minimum features on a substrate|
|US5655110 *||May 31, 1995||Aug 5, 1997||Advanced Micro Devices, Inc.||Method for setting and adjusting process parameters to maintain acceptable critical dimensions across each die of mass-produced semiconductor wafers|
|US5773174 *||Jul 9, 1997||Jun 30, 1998||Matsushita Electric Industrial Co., Ltd.||Method of forming a resist pattern utilizing correlation between latent image height, resist pattern linewidth and surface modification layer width|
|US5939130||May 27, 1997||Aug 17, 1999||Tokyo Electron Limited||Coating film forming method and coating film forming apparatus|
|US6004047||Mar 4, 1998||Dec 21, 1999||Tokyo Electron Limited||Method of and apparatus for processing photoresist, method of evaluating photoresist film, and processing apparatus using the evaluation method|
|US6072191||Dec 16, 1997||Jun 6, 2000||Advanced Micro Devices, Inc.||Interlevel dielectric thickness monitor for complex semiconductor chips|
|US6221787||Apr 19, 1999||Apr 24, 2001||Tokyo Electron Limited||Apparatus and method of forming resist film|
|US6593245 *||Aug 1, 1996||Jul 15, 2003||Advanced Micro Devices||Silicon nitride etch process with critical dimension gain|
|EP0810633A2||May 24, 1997||Dec 3, 1997||Tokyo Electron Limited||Coating film forming method and apparatus|
|EP0863438A1||Mar 3, 1998||Sep 9, 1998||Tokyo Electron Limited||Method of and apparatus for processing photoresist, method of evaluating photoresist film, and processing apparatus using the evaluation method|
|JPH11340134A||Title not available|
|1||*||187th ECS Meeting in Reno, NV-E. Zafiriou et al., "Non-lineal Model Based Run-To-Run Control For Rapid Thermal Processing With Unmeasured Variable Estimation", May 1995.|
|2||*||1995 IEEE/SEMI Advanced Semiconductor Manufacturing Conference-Boning et al., "Practical Issues in Run by Run Process Control", 1995, pp. 201-208.|
|3||*||Hankinson et al., "Integrated Real-Time and Run-to-Run Control of Etch Depth in Reactive Ion Etching", Mar. 13, 1996, pp. 1-17.|
|4||*||IEEE Transactions on Semiconductor Manufacturing-Sachs et al., "Process Control System for VLSI Fabrication", Apr. 5, 1990, pp. 1-31.|
|5||*||IEEE/CHMT International Electronics Manufacturing Technology Symposium, Austin, Texas-Boning et al., "Run by Run Control of Chemical-Mechanical Polishing", Oct. 2-4, 1995.|
|6||*||VMIC, Santa Clara, CA-Smith et al., "Compensating for CMP Pad Wear Using Run by Run Feedback Control", Jun. 18-20, 1996.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7682847 *||Oct 9, 2008||Mar 23, 2010||Micron Technology, Inc.||Method for sorting integrated circuit devices|
|US7738988||Jun 14, 2007||Jun 15, 2010||Micron Technology, Inc.||Process and method for continuous, non lot-based integrated circuit manufacturing|
|US7875821||Oct 9, 2008||Jan 25, 2011||Micron Technology, Inc.||Method for sorting integrated circuit devices|
|US7885782||Oct 17, 2006||Feb 8, 2011||Micron Technology, Inc.||Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed during their manufacture|
|US8315730||May 10, 2010||Nov 20, 2012||Micron Technology, Inc.||Methods for non lot-based integrated circuit manufacturing|
|US8429569 *||Apr 14, 2011||Apr 23, 2013||Taiwan Semiconductor Manufacturing Company, Ltd.||Method and system for feed-forward advanced process control|
|US8600540||Sep 13, 2012||Dec 3, 2013||Micron Technology, Inc.||Methods for non-lot-based manufacturing of articles|
|US8683395 *||Apr 22, 2013||Mar 25, 2014||Taiwan Semiconductor Manufacturing Company, Ltd.||Method and system for feed-forward advanced process control|
|US8929665 *||May 21, 2010||Jan 6, 2015||Hitachi High-Technologies Corporation||Method of manufacturing a template matching template, as well as a device for manufacturing a template|
|US20070094632 *||Oct 17, 2006||Apr 26, 2007||Beffa Raymond J||Method in an integrated circuit (IC) manufacturing process for identifying and redirecting ICs mis-processed during their manufacture|
|US20080248412 *||Apr 9, 2007||Oct 9, 2008||John Douglas Stuber||Supervisory etch cd control|
|US20090038997 *||Oct 9, 2008||Feb 12, 2009||Micron Technology, Inc.||Method for sorting integrated circuit devices|
|US20090060703 *||Oct 9, 2008||Mar 5, 2009||Micron Technology, Inc.||Method for sorting integrated circuit devices|
|US20100241250 *||Mar 18, 2009||Sep 23, 2010||TECH Semiconductor Singapore Ptd Ltd||Feedback and feedforward control of a semiconductor process without output values from upstream processes|
|US20120070089 *||May 21, 2010||Mar 22, 2012||Yukari Yamada||Method of manufacturing a template matching template, as well as a device for manufacturing a template|
|CN102737960B *||Feb 13, 2012||Apr 22, 2015||台湾积体电路制造股份有限公司||Method and system for feed-forward advanced process control|
|U.S. Classification||438/17, 438/780, 438/725|
|International Classification||H01L21/302, H01L21/66|
|Apr 24, 2007||CC||Certificate of correction|
|Dec 28, 2010||FPAY||Fee payment|
Year of fee payment: 12