|Publication number||USRE39529 E1|
|Application number||US 09/536,646|
|Publication date||Mar 27, 2007|
|Filing date||Mar 28, 2000|
|Priority date||Apr 18, 1988|
|Publication number||09536646, 536646, US RE39529 E1, US RE39529E1, US-E1-RE39529, USRE39529 E1, USRE39529E1|
|Inventors||Koyo Katsura, Shinichi Kojima, Noriyuki Kurakami|
|Original Assignee||Renesas Technology Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (29), Referenced by (2), Classifications (11), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of Reissue application Ser. No. 07/985,141, filed Dec. 3, 1992 now U.S. Pat. No. RE37103.
The present invention relates to a graphic processing apparatus for processing graphic data stored in a memory, and in particular, to a graphic processing apparatus in which the number of memories to be employed can be reduced so as to minimize the size of the processing apparatus.
For example, the Japanese Patent Publication JP-A-60-136793 describes a graphic processing apparatus in which characters and graphic data are generated in a display memory (frame buffer) so as to be delivered to output devices such as a display and a printer. In this conventional example, a high-speed graphic drawing operation is achieved by use of a method in which data bits constituting at least one pixel are packed in a word so as to be stored in the memory. In contrast with the prior method in which information of a pixel requires a plurality of words, this method allows accessing of the memory in the unit of a word (16 bits); in consequence, by packing information of a pixel in a single word, at least one pixel can be updated through one access, which therefore increases the processing speed.
In the conventional example above, although the memory is connected to a 16-bit data bus, the dynamic random access memory (DRAM) generally possesses a 1-bit or 4-bit data bus, and hence at least four to 16 memory elements are required, which prevents the apparatus from being miniturized.
In addition, the Japanese Patent Publication JP-A-60-225888 describes an apparatus including a dynamic random access memory (DRAM) having a nibble function (one of consecutive data read functions); however, description has not been given of a combination with a graphic processor in which data are accessed in a parallel fashion.
Moreover, in the Japanese Patent Publication JP-A-55-129387, there is described a system for transferring serial data between a processor and an external device; however, parallel data access is carried out between the processor and a memory.
It is therefore an object of the present invention to provide a small-sized graphic processing apparatus in which data transfer is enabled through a data bus having a reduced bit width so as to minimize the number of memory elements employed.
In order to achieve the object above, according to the present invention, there is disposed data converting means between processor means processing parallel data and a memory so as to enable the data bus width of the memory to be smaller than that of the processor means. The data converting means includes a latch for temporarily storing read data and a multiplexer for writing data. The present invention is characterized in that a memory having a successive data read function is applied to a processor effecting parallel data processing.
In the graphic processing apparatus according to the present invention, the memory is accessed in a time shared fashion such that data is converted by the converting means into parallel data. That is, in a data reading operation, data sequentially read out in a time shared fashion is temporarily stored in a latch so as to be supplied as parallel data to the processor. Moreover, in a data writing operation, parallel data supplied from the processor is sequentially written through the multiplexer into the memory in a time shared fashion.
The present invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
Referring now to the drawings, description will be given of an embodiment according to the present invention.
On receiving control signals (
Read/write data is transferred between the ACRTC 10 and the frame buffer 30 through the MIVAC 20.
In the display operation, parallel data read from the frame buffer 30 is fetched into the MIVAC 20 to be converted into serial data by means of a parallel/serial converter integrated therein, thereby producing digital video signals. These digital signals are converted by the CPLT 40 into analog video signals so as to be displayed on the CRT 50. In this embodiment, although the CRT 50 is used as the output device, other output equipment, such as a printer, may also be employed.
Terminal INCLK of the operation control signals is used to receive a clock for the operation basis of the MIVAC 20. The interface signals for the ACRTC 10 include the 2CLK as the basic clock of the ACRTC 10, control signals MRD and
The INCLK as the basis of the operation of the MIVAC 20 is divided by 2, 4, 8 16, and 32 by INCLK 2006 and an INCLK divider 2009. The results are combined in a state decoder 2007 to generate a timing signal, which is used in the respective logic circuits.
The 2CLK as the basic clock of the ACRTC 10 is produced from a 2CLK generator 2008. In the 2CLK 2008, in order to effect a plurality of read and write operations in the memory cycle, the first half cycle is shorter than the second half cycle, i.e., this signal has an asymmetric shape.
For the DOTCLK, a multiplex operation is achieved on the signals attained by dividing INCLK by 1, 2, and 4 by means of a multiplexer 2010 to produce a multiplexed signal. Selection of the divided signals is automatically achieved depending on the operation mode of the MIVAC 20.
The frame buffer address MAD0 to MAD15 and MA16 to MA19 supplied from the ACRTC 10 is temporarily latched in a latch 2001 so as to be then multiplexed through a multiplexer 2003 into a row/column address, thereby generating a ten-bit address associated with the frame buffer address signals FA0 to FA9. In addition, there is integrated a column address counter 2002 such that the value of this counter and the latched address are multiplexed by the multiplexer 2003, so that the resultant signal is adopted as a portion of the column address, thereby effecting several read/write operations in a memory cycle.
The control signals from the ACRTC 10 are latched in a latch 2004. Depending on
In addition, when
The video signal is skewed by a skew circuit 2022 so as to be synchronized with the control signal from the ACRTC 10. For the video signal, a superimposing operation of a cursor can be achieved by use of a cursor blink 2023, or the video signals can be multiplexed through a multiplexer 2024 in response to a signal attained by dividing
By using BLINK2 of the attribute codes, a
In the case of a two chip memory configuration of
In the case of a four chip memory configuration of
In this mode, since the data buses are employed to input display data, it is impossible to effect a read operation in which 16 read operations are achieved in two memory cycles; however, when comparison is conducted in the read mode associated with four read operations per memory cycle, the operation above is applicable to a CRT which develops a higher processing speed as compared with the cases of
(1) For the display color (color/gradation), there can be specified a monochrome display represented by 1 bit/pixel, a four-color display expressed by 2 bits/pixel, and 16-color display represented by 4 bits per pixel. In the case of 1 bit/pixel, a word of the memory is loaded with information of 16 consecutive pixels in the horizontal direction. In the case of 2 bits/pixel, a word of the memory is loaded with information of 8 consecutive pixels in the horizontal direction, and in the case of 4 bits/pixel, a word of the memory is loaded with information of 4 consecutive pixels in the horizontal direction.
(2) The shift length of the shift register may be set to 4, 8, 16, or 32 bits.
(3) The access modes include a single access mode, a dual access mode in which high-speed drawing is possible, and a 2MCYC mode in which 16 display accesses are conducted in two memory cycles. In the modes 0 to 5, the single access mode is employed, whereas in the modes 6 to C, the dual access mode is used. In the modes D to F, the 2MCYC mode is adopted.
(4) The number of memories selectable is 1, 2, or 4. For the memory, there is utilized a memory such as one having a static column mode in which a plurality of read/write operations can be accomplished in a cycle.
(5) DOTCLK is generated by dividing INCLK by 1, 2, and 4. The division ratios are determined according to the respective operation modes. Based on the frequency, the screen layout of the CRT is determined for each operation mode.
(1) When CUR1 and CUR0 are both 0
The four bits of video outputs VIDEOA to VIDEOD are set to 0, and hence a black cursor is displayed.
(2) When CUR1 is 0 and CUR0 is 1
The four bits of video outputs VIDEOA to VIDEOD are set to 1 and hence a white cursor is displayed.
(3) When CUR1 is 1 and CUR0 is 0
For the four bits of video outputs VIDEOA to VIDEOD, the respective colors are reversed on the display.
(4) When CUR1 and CUR0 are both 1
For the three bits of video outputs VIDEOA to VIDEOC, the respective colors are reversed on the display, whereas VIDEOD is kept unchanged.
BLINK1=0, the cursor is not displayed, whereas for
BLINK1=1, the cursor is displayed.
As described above, according to the present invention, the data bus width of the memory can be minimized, and hence the size of the graphic processing apparatus can be reduced.
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|JPS6383844A||Title not available|
|JPS6488962A||Title not available|
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|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8713248||Jun 2, 2009||Apr 29, 2014||Nokia Corporation||Memory device and method for dynamic random access memory having serial interface and integral instruction buffer|
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|U.S. Classification||345/531, 345/520, 345/537, 345/503, 345/545, 345/571, 345/564|
|International Classification||G09G5/39, G09G5/393|
|Sep 26, 2003||AS||Assignment|
Owner name: RENESAS TECHNOLOGY CORPORATION, JAPAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:014569/0585
Effective date: 20030912