|Publication number||USRE39578 E1|
|Application number||US 11/176,885|
|Publication date||Apr 17, 2007|
|Filing date||Jul 7, 2005|
|Priority date||Jan 18, 2002|
|Also published as||US6591286|
|Publication number||11176885, 176885, US RE39578 E1, US RE39578E1, US-E1-RE39578, USRE39578 E1, USRE39578E1|
|Original Assignee||Faust Communications, Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (26), Referenced by (2), Classifications (9), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to computer arithmetic devices, and more particularly to incrementers.
Many types of computing systems include an arithmetic-logic-unit (ALU). The ALU may be capable of performing sophisticated logical and arithmetic operations including multiply and divide. Special logic blocks may be added to speed up the more complex operations. A dedicated multiplier can rapidly perform multiply operations, while an integer divider can perform divide operations that otherwise would require thousands of clock cycles of the basic ALU.
These auxiliary math units may themselves contain several smaller blocks, such as shifters, adders, and leading-zero and other condition detectors. In particular, a divider may use an adder to increment a value such as for rounding a value from a floating point datapath. A general-purpose adder could be used for this sub-function.
Adders are often constructed from a one-bit adder cell known as a half-adder.
Both a sum S and a carry-out CO to the next higher bit position (i+1) are generated by half-adder cell 10. The sum at position (i) of A and CI can be generated by exclusive-OR (XOR) gate 14, while the carry out CO to position (i+1) is generated by AND gate 12.
This is known as a half-adder cell because to perform a full add of two inputs X, Y, two such half-adder cells are needed for each bit position. One half-adder cell adds bit (i) of inputs X and Y to generate A(i), while the second half-adder cell adds the intermediate result A(i) to the carry CI(i) to generate the final sum.
While a full adder can be used to increment a binary number, a dedicated incrementer can be constructed. This incrementer can only add 1 or 0 to an input; it cannot add an arbitrary number as can a full adder. However, the amount of logic inside the incrementer can be less than the logic inside a full adder. A single half-adder cell is needed for each bit position in the incrementer, while two half-adder cells are required for each bit position in the full adder.
The LSB half-adder cell 10 adds this lowest CI to the LSB of input A, A(0), to form sum bit S(0). The carry output of bit 0 is coupled to the carry input CI of the half-adder cell 10 adding the next higher bit, A(1). This second half-adder cell 10 generates sum S(1) and a carry out CI that is connected to the carry input CI of the third half-adder cell 10.
The carry output generated by each half-adder cell is applied to the carry input of the next higher half-adder cell. The final carry output CO(6) from bit 6 can be discarded, or it can signal on overflow when it is a 1.
Since the carries are propagated through an AND gate in each half-adder cell 10, the LSB carry bit may have to pass through seven AND gates to reach the final carry out of bit 6 in a worst-case delay path. This is known as a ripple carry since the carry signal ripples through all bits of the adder or incrementer.
In full adders, various techniques have been used to reduce this worst-case delay of the carry rippling through all the bits of the adder. For example, look-ahead logic can be used to generate an intermediate carry by looking at the binary-number inputs and carry into a group of bits.
What is desired is a look-ahead for an incrementer rather than for a full adder. An incrementer with a carry-lookahead is desired to reduce carry ripple delays in a fast incrementer. A pipelined incrementer is desired to further reduce delays that occur within a clock cycle.
The present invention relates to an improvement in fast incrementers. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
FIG. 3—Carry Lookahead for an Incrementer
The LSB carry input CI(0) is added to bit 0 of input word A by the first half-adder cell 10, generating the LSB of the sum, S(0). The carry output from bit-position 0 is coupled to the carry input of the half-adder cell 10 at bit position 1, where it is added to A(1) to generate S(1) and CO(1). The carry output CO(1) is applied as the carry input to bit-position 2. The third half-adder cell 10 adds A(2) to CI(2) to generate S(2) and CO(3).
The LSB carry input CI(0) thus ripples up through bit positions 0, 1, 2. There is a delay of 2 AND gates from CI(0) to CI(2).
Rather than use CO(2) as the carry input CI(3) to half-adder cell 10 at bit position 3, a lookahead carry is generated by AND gate 16. AND gate 16 receives inputs A(0), A(1), A(2) from the binary input word A. If it is assumed that the incrementer always increments, then CI(0) is always 1 and never 0. Then the carry output from bit position 2 is A(0) & A(1) & A(2), where “&” represents a logical AND operation. Thus AND gate 16 generates CI(3) to the half-adder cell 10 at bit position 3.
Using AND gate 16 to generate CI(3) rather than the carry output CO(2) from the third half-adder cell 10 reduces delay. There are 3 AND gate delays from CI(0) to CO(2), while only one AND-gate delay to CI3 when AND gate 16 is used. Thus the carry-lookahead provided by AND gate 16 reduces the CI(3) delay.
The intermediate carry CI3 generated by AND gate 16 is rippled through half-adder cells 10 for bit positions 3 and 4. However, the carry output CO(4) from bit position 4 is not used but instead discarded. A second intermediate carry-lookahead CI5 is generated by AND gate 18 for bit 5. This carry-lookahead CI5 is applied to carry input CI(5) of half-adder cell 10 for bit position 5. The second intermediate carry CI5 is rippled through the last 2 bit positions that generate sum bits S(5,6).
AND gate 18 receives A(3) and A(4) from the binary-word input A. When both these input bits are 1, the carry input to bit-position 3, CI3, is propagated by AND gate 18, which also received CI3 as an input. CI3 is generated by AND gate 16 from A(0), A(1), A(2). Thus CI5 is high when all five input bits A(1) to A(4) are high.
In general, for an incrementer that always increments, a lookahead carry input for any bit-position is high when all lower-position input bits are high. Any bit-position's carry lookahead could be generated by ANDing the binary-input bits below that position.
Since the incrementer has only one binary-word input, the carry-lookahead logic is much simpler than for a 2-input full adder. Only input bits from one binary input word need to be considered in the lookahead logic.
FIG. 4—Fixed Sequence of Incrementer States
For example, when input A is 0000, the sum is 0001, as shown in the first row. The sum 0001 is applied to the input A for the next clock cycle, as shown in the second row. The incrementer then generates the sum 0010 as the next state shown in the second row. Once the sequence reaches 1111, the next state or sum wraps back to 0000 as shown in the last row.
For any bit position (i), when all lower bits in an input A are high, then the carry-lookahead to the bit position (i) is high. The sum bit for bit position (i) is the XOR of the carry input CI(i) and the binary input A(i). Thus when the 111 . . . 1 condition occurs in the lower bits, the current sum bit is generated by XORing the carry in (which is a 1) with the current input bit A(i).
This is shown in the table in the 8th and 16th rows. The lower bits are 111, causing the carry in to be high. The input bit A(3) is XORed with the carry in, causing the uppermost input bit to toggle. Thus input 0111 produces the sum 1000, while the input 1111 produces the sum 0000.
For other rows, the lower bits are not all ones. The carry input CI3 is low, so the uppermost bit does not change. The uppermost bit only changes when the lower bits are all ones.
FIG. 5—Detection of All-Ones Condition
The inventor detects this all-ones condition, further simplifying the incrementer's logic.
XOR gate 24 receives CI(i) from AND gate 22 and toggles A(i) when CI(i) is high.
Otherwise, XOR gate 24 passes input A(i) through without change as the sum bit S(i) for this bit-position i.
The state of sum bit S(i) from XOR gate 24 is latched by flip-flop 20 when clock CLK rises. The latched sum bit is output by flip-flop 20 as output Q(i), and is fed back to the incrementer's input A as input bit A(i). Signals Q(i) and A(i) can be the same signal. The logic of
FIG. 6—Pipelining of Carry-Lookahead
The inventor has realized that the carry generation can be pipelined. Since the incrementer sequences through a fixed series of states or binary counts, the next several states are known in advance. An incrementer cannot jump from 1001 to 1110 without passing through 1010, 1011, 1100, and 1101. The inventor uses this knowledge of the sequence of states to pipeline carry generation.
AND gate 22 detects the 1111 condition of the lower input bits A(i−1), A(i−2), etc. to generate CI(i). C(i) causes A(i) to be toggled by XOR gate 24 to generate sum bit S(i), which is latched by flip-flop 20.
However, the lowest 5 input bits A(0), A(1), A(2), A(3), and A(4) are not input to AND gate 22. Instead, pipelined carry lookahead signal C0, C1 are input to AND gate 22. This reduces the number of inputs to AND gate 22 and its complexity and propagation delay.
While carry lookahead signal C0 could be generated by ANDing input signal A(0), A(1), and A(2), it is instead generated by ANDing the corresponding sum signals during the previous clock cycle. Thus AND gate 34 ANDs sum bits S(0), S(1), S(2) to generate LCI0, which is input to flip-flop 30 and latched. Likewise, AND gate 36 ANDs sum bits S(3), S(4) to generate LCI1, which is input to flip-flop 32 and latched to generate pipelined carry lookahead signal C1.
The output of flip-flop 30 is pipelined carry lookahead signal C0 that is input to AND gate 22. Sum bits S rather than input bits A are combined to generate the pipelined carry-lookahead signals since the sum bits become the input bits after the next rising clock edge.
AND gate 22, XOR gate 24, and flip-flop 20 can be replicated for other bit-positions of the incrementer. However, carry lookahead generation by AND gates 34, 36 and pipelining flip-flops 30, 32 can be instantiated only once and shared by many bit-positions.
FIG. 7—7-bit Incrementer with Pipelined Carry-Lookahead
Carry-lookahead generation is pipelined. AND gate 34 receives lower sum bits S(0), S(1), S(2). The output of AND gate 34 is applied to the D input of flip-flop 30, which latches the pre-lookahead and drives the pipelined carry lookahead signal C0 during the following clock cycle. Likewise, AND gate 36 receives lower sum bits S(3), S(4). The output of AND gate 36 is applied to the D input of flip-flop 32, which latches this second pre-lookahead signal and drives the second pipelined carry lookahead signal C1 during the following clock cycle.
The LSB sum bit S(0) is toggled each clock cycle by inverter 58, which receives Q from flip-flop 40 and also drives the D-input to flip-flop 40. XOR gate 51 receives Q (0) and Q(1) and toggles Q(1) when Q(0) is high. Otherwise Q(1) is passed through to the D-input of flip-flop 41 as S(1).
AND gate 62 drives the upper input to XOR gate 52 high when both Q(0) and Q(1) are high. This is the 11 carry-in condition. XOR gate 52 receives this carry in generated by AND gate 62 and toggles Q(2) when the output of AND gate 62 is high. Otherwise Q(2) is passed through to the D-input of flip-flop 42 as S(2).
The pipelined carry lookahead signal C0 from flip-flop 30 is applied to the upper input of XOR gate 53. When pipelined carry lookahead signal C0 is high (sum bits S(0), S(1), S(2) were all high in the prior clock period) XOR gate 53 toggles Q(3) from the Q-output of flip-flop 43 to generate sum S(3) to the D-input of flip-flop 43. Otherwise XOR gate 53 passes Q(3) through unchanged as S(3) to flip-flop 43.
AND gate 64 drives the upper input to XOR gate 54 high when both pipelined carry lookahead signal C0 and Q(3) are high. This is the 1111 carry-in condition. XOR gate 54 receives this composite carry-in generated by AND gate 64 and toggles Q(4) when the output of AND gate 64 is high. Otherwise Q(4) is passed through to the D-input of flip-flop 44 as S(4).
For bit-position 5, AND gate 66 drives the upper input to XOR gate 55 high when both pipelined carry lookahead signal C0 and C1 are high. This is the 11111 carry-in condition when all five lower sum bits were high in the prior clock cycle. XOR gate 55 receives this composite carry-in generated by AND gate 66 and toggles Q(5) when the output of AND gate 66 is high. Otherwise Q(5) is passed through to the D-input of flip-flop 45 as S(5).
For the most-significant-bit (MSB) bit-position (6), AND gate 68 drives the upper input to XOR gate 56 high when both pipelined carry lookahead signal C0 and C1 are high and Q(5) is high. This is the 111111 carry-in condition when all six lower sum bits are high. XOR gate 56 receives this composite carry-in generated by AND gate 68 and toggles Q(6) when the output of AND gate 68 is high. Otherwise Q(6) is passed through to the D-input of flip-flop 46 as S(6).
FIG. 8—Resetable 7-bit Incrementer with Pipelined Carry-Lookahead
Inverting NAND gates 62′, 64′, 66′, 68′ operate as AND gates 62, 64, 66, 68 described earlier for
A synchronous reset is added by inserting inverters 80-86 and NOR gates 70-76 between the sum bits S(0:6) and the D-inputs to flip-flops 40-46. The lower inputs to NOR gates 70-76 is an active-high reset signal RS. When RS is high, NOR gates 70-76 drive a low to the D-inputs of flip-flops 40-46. Otherwise the sum bits are passed through after a double inversion.
NAND gates 34′, 36′ perform the same function as AND gates 34, 36 described earlier, and are followed by NOR gates 77, 78 which drive a low to the D-inputs of flip-flops 30, 32 when reset signal RS is high. Thus pipelined carry lookahead signals C0, C1 are also resetable.
Several other embodiments are contemplated by the inventor. For example the incrementer can count upward or downward (decrement) and the increment can be a value other than 1, such as +2, +4, −4, etc. The incrementer can count in binary or in gray code or in some other sequence. Falling-edge-triggered flip-flops could be substituted for rising-edge flip-flops. Various logic inversions and applications of DeMorgan's theorem could be applied to adjust the logic gates. Rather than XOR gates, exclusive-NOR (XNOR) gates could be employed without inverters on the Q input to the XNOR gate.
Different groupings of sum bits into the pipelined carry lookahead signals can be substituted, and the pipelined carry-lookahead logic can be combined or rippled together before or after the flip-flops. More than two pipelined carry lookahead signals could be generated and latched. Reset logic can be added to the incrementer, such as by making all flip-flops settable or resetable, either asynchronously or synchronously. The incrementer could be reset to a value other than zero, such as to a non-zero starting address or pointer. Other logic can be added or inserted for other functions, such as to vary the increment amount or direction of counting. The clock could be a free-running clock, or it could be paused or gated so that the incrementer stops counting for periods of time.
The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 C.F.R. §1.72(b). Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC §112, paragraph 6. Often a label of one or more words precedes the word “means” The word or words preceding the word “means” is a label intended to ease referencing of claims elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word means are not intended to fall under 35 USC §112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
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|International Classification||G06F7/505, G06F7/508, G06F7/50|
|Cooperative Classification||G06F7/508, G06F7/5055, G06F2207/3884|
|European Classification||G06F7/505J, G06F7/508|
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