|Publication number||USRE39603 E1|
|Application number||US 10/645,782|
|Publication date||May 1, 2007|
|Filing date||Aug 22, 2003|
|Priority date||Sep 30, 1994|
|Also published as||CA2159242A1, CA2159242C, DE69526895D1, DE69526895T2, EP0704895A2, EP0704895A3, EP0704895B1, US5844304|
|Publication number||10645782, 645782, US RE39603 E1, US RE39603E1, US-E1-RE39603, USRE39603 E1, USRE39603E1|
|Inventors||Keiichiro Kata, Shinichi Chikaki|
|Original Assignee||Nec Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (33), Non-Patent Citations (2), Referenced by (8), Classifications (28), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to a process for manufacturing a semiconductor device and, more particularly, to a process suited for mass production of a highly integrated semiconductor device.
Semiconductor devices of various forms have been developed to meet recent demands in the electronics field towards size and weight reduction, speed increase, and improvement of functional operations of the devices. The semiconductor device comprises a package and a semiconductor chip (hereinafter, also referred to as a chip) contained in the package. The chip has been integrated higher and higher, and such a highly integrated semiconductor chip increases the number of terminals thereon. In addition, there have been severe demands on the semiconductor chips towards the possible reduction in size. The terminal-to-terminal pitch should thus be reduced to meet these demands or requirements for the semiconductor devices. A semiconductor device having a high terminal count can be obtained by inner lead bonding or by area array bonding. The inner lead bonding and the area array bonding are expected to be inevitable for the field of the semiconductors.
The inner lead bonding (ILB) is used to make electrical contact between the chip and the leads within the package. Various bonding technologies are available to achieve this inner lead bonding. Wire bonding is the most extensively used electrical interconnection process. In this process, fine wires are used to make electrical contact between the bonding pads on the chip and the corresponding leads on the package. The wire diameter is typically from 20 to 30 micrometers. Wire bonding techniques include thermocompression bonding, ultrasonic bonding, and thermosonic bonding.
The use of the fine wires limits the number of interconnections available in one package. The recent demands for the semiconductor devices with a high terminal count thus causes a problem of poor connections between the wire and the bonding pads. Considering this fact, the wire bonding has been replaced with wireless bonding. The wireless bonding is also called gang bonding, with which all bumps on the electrode pads are bonded simultaneously to the leads. Wireless bonding techniques include tape automated bonding (TAB) and flip-chip bonding. The TAB is also referred to as tape carrier bonding.
In the TAB technique, a laminated tape of gold-plated copper foil etching in the form of leads is bonded to the bumps on the electrode pads. The elimination of the wire bonding is advantageous from viewpoints of size reduction and highly integrated packaging of the device. On the other hand, the flip-chip bonding requires to make a raised metallic bump of solder on the chip. The chip is then inverted and bonded face down to the substrate interconnection pattern. This process lends itself to production of semiconductor devices with a high terminal count and a smaller pitch. In addition, this technique is also advantageous to provide a fast, low-noise semiconductor device with the short length of the interconnections.
The TAB and flip-chip bonding techniques use the bumps provided between the chip and the package to make electrical interconnection between them. These techniques are disclosed in, for example, Japanese Patent Laid-open Nos. 5-129366 and 6-77293.
As mentioned above, the film carrier semiconductor device disclosed in these laid-open publications uses the bumps for the electrical interconnection between the chip and the carrier film. There is another film carrier semiconductor device in which the electrical interconnection between the chip and the carrier film is achieved without using the bumps. The semiconductor chip and the carrier film are electrically connected during the assembly process. The bumps are used only for the purpose of connecting the film carrier semiconductor device with, for example, a circuit board or a mounting board. The film carrier semiconductor device of the type described comprises a semiconductor chip and a carrier film. Contact pads are provided on the semiconductor chip at one side thereof. The contact pads are arranged along the periphery of the semiconductor chip. Interconnecting layers are provided on the carrier film. The carrier film is also provided with through-holes and openings formed therein. The openings are formed at the position corresponding to the contact pads (chip electrodes).
A conventional process for manufacturing a semiconductor device is described first for the purpose of facilitating the understanding of the present invention. In this event, description is made on a process for manufacturing a film carrier semiconductor device. A wafer, which comprises a number of chip sections each having chip electrodes formed thereon, is covered with a passivating film by using a well-known technique. After the formation of the passivating film, the chip electrodes are exposed to the atmosphere. The chip sections are then separated from each other into individual chips along scribe lines by means of a known dicing technique using a dicing saw. The semiconductor chip so obtained is prepared along with a carrier film and an adhesion film. The adhesion film is positioned relative to the semiconductor chip and placed thereon. The carrier film and the semiconductor chip are subjected to heat and pressure to adhere them through the adhesion film. The carrier film is then cut along the edges of the chip by means of any adequate method. Next, bump electrodes (solder bump) are formed on corresponding outer chip electrodes arranged on the carrier film.
Semiconductor devices so obtained may find various applications in the electronics, electrical, and other fields. For example, semiconductor devices may be used for memories and drivers for a liquid crystal display. Such applications are suited for mass-production of the semiconductor device. However, the above mentioned manufacturing process has a certain limitation on the number of chips obtained per unit time because the operation should be made for each chip. Recent demands for smaller memories or drivers have reduced the size of the semiconductor device itself. Accordingly, it is necessary to conduct the operations such as the inner lead bonding and the formation of the bumps for each small chip. Such operation is so elaborate and somewhat troublesome because the semiconductor chip is relatively small. It is thus difficult to position the carrier film positively or with a high accuracy. The elaborate operation is also associated with the reliability of the electrical interconnection between the semiconductor chip and the carrier film. In other words, there may be trouble in the interconnection between the semiconductor chip and the carrier film as well as the adhesion of the individual components. In this respect, a batch process may be more effective than the conventional process for the mass-production of the semiconductor device, in which most operations are conducted on chip sections of a wafer. In this process, the bump electrodes are formed on the chip sections of the wafer which are not separated from each other into the individual chips.
Such a method is disclosed in, for example, U.S. Pat. No. 5,137,845, issued to Lochon et al. This method has developed by IBM Corporation and is applicable to the manufacturing of bump electrodes for semiconductor chips that are suitable for Controlled Collapse Chip Connection (C4) or flip-chip technique. In this method, a barrier metal is deposited on aluminum chip electrodes, on which bump electrodes are deposited for a terminal contact. The resultant wafer is, however, directed to the application as it is. In other words, this patent is not for a wafer to be divided into semiconductor chips. There is no disclosure of the separation of the wafer nor the disclosure about the position of the interconnection, chip electrodes, and bump electrodes to avoid the breakage of them upon dicing. In addition, the bump electrodes in the above mentioned conventional semiconductor devices are formed on the corresponding chip electrodes. The formation of the bumps on the electrodes is, however, difficult or even impossible by the practical consideration to meet recent demands on the semiconductor chips towards the possible reduction in size with a higher terminal count and a smaller pitch.
This problem may be solved by means of using a multi-layered electrode structure of the semiconductor device which allows the distribution of the solder pads on the entire surface of the semiconductor chip. Such a structure is, however, complex and difficult to be manufactured. In addition, the multi-layered electrode significantly affects the configuration of the chip surface. A larger number of layers may sometimes make the surface irregular.
Accordingly, an object of the present invention is to provide a process for manufacturing a semiconductor device having bump electrodes formed at different positions from chip electrodes, which is suited for mass-production.
Another object of the present invention is to provide a process for manufacturing a semiconductor device having a good thermal stress resistance.
Yet another object of the present invention is to provide a process for manufacturing a semiconductor device having a good moisture resistance.
In order to achieve the above mentioned object, there is provided a process for manufacturing a semiconductor device comprising the steps of defining a number of semiconductor chip sections on a wafer, each semiconductor chip section having a number of chip electrodes formed on one surface along a periphery thereof, the one surface being covered with a passivating film except for the positions where the chip electrodes are formed; forming a number of interconnection layers on the wafer for each semiconductor chip section such that each interconnection layer is connected to the chip electrode at one end thereof and is extended inward the chip section at the other end; covering the entire surface of the wafer with a cover coating film; forming a number of apertures in the cover coating film, the apertures being formed into a matrix; forming a number of bumps on the apertures; and separating the semiconductor chip sections on the wafer as individual semiconductor chips along scribe lines.
In the above mentioned process, the intermediate layer extended inward the semiconductor chip section is preferably exposed to the atmosphere through the aperture. In addition, the solder bumps are preferably formed away from the scribe line. Furthermore, the bump electrodes are preferably formed at the position not just over the chip electrodes.
The above and other objects, features and advantages of the present invention will become more apparent in the following description and the accompanying drawing in which like reference numerals refer to like parts and components.
According to another aspect of the present invention, there is provided a semiconductor wafer having a number of semiconductor chips comprising bump electrodes formed into a matrix on an entire surface of the wafer except for on scribe lines between the semiconductor chips.
A conventional process for manufacturing a semiconductor device is described first for the purpose of facilitating the understanding of the present invention. In this event, description is made on a process for manufacturing a film carrier semiconductor device. Referring to
The carrier film 30 comprises an organic insulation film 31. The organic insulation film 31 may be, for example, a polyimide-based insulation film. The organic insulation film 31 has a first surface 31a and a second surface 31b. Interconnection layers 32 are provided on the organic insulation film 31 on the side of the first surface 31a. Through-holes 33 are formed in the insulation film 31. One end of each through-hole 33 faces the interconnection layer 32. Each through-hole 33 passes through the insulation film 31 to the second surface 31b thereof. The insulation film 31 is also provided with openings 34 penetrating through the film. The openings 34 are formed at the position corresponding to the chip electrodes 11. Each through-hole 33 is filled with a conductive electrode 35. Likewise, each opening 34 is filled with a filler material 36.
The above mentioned steps illustrated in
As mentioned above, this conventional manufacturing process is available only for the limited number of chips obtained per unit time because it is necessary to conduct the operations such as the inner lead bonding and the formation of the bumps for each small chip. Accordingly, there may be trouble in the interconnection between the semiconductor chip and the carrier film as well as the adhesion of the individual components. In addition, the bump electrodes in the above mentioned conventional semiconductor devices are formed on the corresponding chip electrodes, which causes some problems under the recent demands on the semiconductor chips towards the possible reduction in size with a higher terminal count and a smaller pitch.
Next, an embodiment of the present invention is described with reference to
The wafer at this stage is illustrated in
The conventional wafer 10′ illustrated in
As mentioned above, according to the present invention, it is possible to mass-produce semiconductor devices without making a large investment for manufacturing facilities because the present process is in-line with a well-known chip manufacturing process. The semiconductor device obtained according to the present invention has a superior thermal stress resistance and good joints between the adjacent layers. This improves the moisture resistance of the semiconductor devices.
While the present invention has thus been described in conjunction with a specific embodiment thereof, it is understood that the present invention is not limited to the illustrated embodiment. Instead, any changes, modifications, and variations may be made by those skilled in the art without departing from the scope and spirit of the appended claims. For example, gold may be used for the bumps rather than the solder. In such a case, the nickel plating and the gold plating can be eliminated.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3719981 *||Nov 24, 1971||Mar 13, 1973||Rca Corp||Method of joining solder balls to solder bumps|
|US3760238||Feb 28, 1972||Sep 18, 1973||Microsystems Int Ltd||Fabrication of beam leads|
|US4604644 *||Jan 28, 1985||Aug 5, 1986||International Business Machines Corporation||Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making|
|US4878098||Mar 24, 1989||Oct 31, 1989||Kabushiki Kaisha Toshiba||Semiconductor integrated circuit device|
|US4907062||Oct 14, 1988||Mar 6, 1990||Fujitsu Limited||Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon|
|US4948754||Aug 31, 1988||Aug 14, 1990||Nippondenso Co., Ltd.||Method for making a semiconductor device|
|US5027188 *||Sep 13, 1989||Jun 25, 1991||Hitachi, Ltd.||Semiconductor integrated circuit device in which a semiconductor chip is mounted with solder bumps for mounting to a wiring substrate|
|US5049980||Apr 14, 1988||Sep 17, 1991||Kabushiki Kaisha Toshiba||Electronic circuit device and method of manufacturing same|
|US5111278||Mar 27, 1991||May 5, 1992||Eichelberger Charles W||Three-dimensional multichip module systems|
|US5137845 *||Jul 12, 1991||Aug 11, 1992||International Business Machines Corporation||Method of forming metal contact pads and terminals on semiconductor chips|
|US5250843 *||Sep 8, 1992||Oct 5, 1993||Integrated System Assemblies Corp.||Multichip integrated circuit modules|
|US5289038||Oct 28, 1992||Feb 22, 1994||Fuji Electric Co., Ltd.||Bump electrode structure and semiconductor chip having the same|
|US5327013 *||Jul 15, 1993||Jul 5, 1994||Motorola, Inc.||Solder bumping of integrated circuit die|
|US5434452 *||Sep 20, 1994||Jul 18, 1995||Motorola, Inc.||Z-axis compliant mechanical IC wiring substrate and method for making the same|
|US5554940||Jul 5, 1994||Sep 10, 1996||Motorola, Inc.||Bumped semiconductor device and method for probing the same|
|US5604379 *||May 30, 1995||Feb 18, 1997||Sharp Kabushiki Kaisha||Semiconductor device having external electrodes formed in concave portions of an anisotropic conductive film|
|US5844304 *||Sep 25, 1995||Dec 1, 1998||Nec Corporation||Process for manufacturing semiconductor device and semiconductor wafer|
|EP0485760A1 *||Oct 18, 1991||May 20, 1992||International Business Machines Corporation||Low temperature controlled collapse chip attach process|
|JPH0677293A *||Title not available|
|JPH01173733A||Title not available|
|JPH01196856A||Title not available|
|JPH04373131A||Title not available|
|JPH05121413A||Title not available|
|JPH05129366A *||Title not available|
|JPH05166812A||Title not available|
|JPH05218042A||Title not available|
|JPH05267302A||Title not available|
|JPH06112211A||Title not available|
|JPS4952973A *||Title not available|
|JPS5287983A||Title not available|
|JPS6386458A||Title not available|
|JPS6457643U||Title not available|
|JPS63293965A||Title not available|
|1||*||R. Chanchani et al., "A New mini Ball Grid Array (mBGA) Multichip Module Technology"; International Journal of Microcircuits & Electronic Packaging, 18(1995) Third Quarter, No. 3, Reston, VA, pp. 185-192., Dec. 1995.|
|2||Ray-Long Day et al., "A Silicon-on-Silicon Multichip Module Technology with Integrated Bipolar Components in the Substrate", IEEE Multi-Chip Module Conference MCMC-94, Mar. 15-17, 1994, pp. 64-67.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7510898 *||May 16, 2007||Mar 31, 2009||Canon Kabushiki Kaisha||Method of manufacturing image display device and method of dividing device|
|US8115284||Jan 7, 2011||Feb 14, 2012||Seiko Epson Corporation||Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument|
|US8384213||Mar 6, 2009||Feb 26, 2013||Seiko Epson Corporation||Semiconductor device, circuit board, and electronic instrument|
|US8633588 *||Dec 21, 2011||Jan 21, 2014||Mediatek Inc.||Semiconductor package|
|US9142526||Dec 11, 2013||Sep 22, 2015||Mediatek Inc.||Semiconductor package with solder resist capped trace to prevent underfill delamination|
|US20070275493 *||May 16, 2007||Nov 29, 2007||Canon Kabushiki Kaisha||Method of manufacturing image display device and method of dividing device|
|US20090174068 *||Mar 6, 2009||Jul 9, 2009||Seiko Epson Corporation||Semiconductor device, circuit board, and electronic instrument|
|US20110095432 *||Jan 7, 2011||Apr 28, 2011||Seiko Epson Corporation||Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument|
|U.S. Classification||257/620, 257/786, 257/737, 257/738|
|International Classification||H01L23/485, H01L23/12, H01L21/78, H01L21/60, H01L23/544|
|Cooperative Classification||H01L2924/12042, H01L24/11, H01L2224/83101, H01L2924/01029, H01L2924/01079, H01L21/78, H01L2924/01013, H01L2924/014, H01L2924/01082, H01L2924/01033, H01L2924/01078, H01L2924/01014, H01L2224/13099, H01L2224/131, H01L24/13, H01L2924/351|
|European Classification||H01L24/10, H01L24/11, H01L21/78|
|Aug 26, 2008||CC||Certificate of correction|
|May 7, 2010||FPAY||Fee payment|
Year of fee payment: 12
|Dec 22, 2010||AS||Assignment|
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN
Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025525/0145
Effective date: 20100401