|Publication number||USRE39690 E1|
|Application number||US 09/998,595|
|Publication date||Jun 12, 2007|
|Filing date||Nov 16, 2001|
|Priority date||Dec 6, 1993|
|Also published as||DE69425636D1, DE69425636T2, EP0657925A1, EP0657925B1, US5435888, US5633534, US5837613, US5986330|
|Publication number||09998595, 998595, US RE39690 E1, US RE39690E1, US-E1-RE39690, USRE39690 E1, USRE39690E1|
|Inventors||Alex Kalnitsky, Yih-Shung Lin|
|Original Assignee||Stmicroelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (50), Non-Patent Citations (19), Referenced by (8), Classifications (31), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of patent application Ser. No. 08/456,343, filed Jun. 1, 1995 now abandoned which is a continuation of Ser. No. 08/163,043 filed on Dec. 6, 1993 now U.S. Pat. No. 5,435,888.
The present invention relates to formation and structures for interlevel dielectrics in integrated circuit fabrication.
A high degree of planarization is essential in the fabrication of integrated circuits with multiple levels of interconnect. Application of spin-on glass,1 followed by global etch-back, is widely used in the industry to achieve the desired level of surface planarity. However, spin on glass (“SOG”) and SOG etch-back technique are inadequate in a variety of situations where topologies with high aspect ratio and/or more topologies are encountered due to lack of planarization and/or sog cracks.
1Spin-on glass deposition is an example of a “sol-gel” process, which has been used in the semiconductor industry for many years. The unprocessed spin-on-glass material (available in numerous formulations) is a fluid material (actually a gel). After the liquid material is coated onto the face of a wafer, the wafer is rotated at high speed to throw off the excess material. The surface tension and adhesion of the material provides a flat (planarized) surface with a controlled thickness. The liquid material is then baked, to drive off solvents and provide a stable solid silicate glass. See generally, e.g., Dauksher et al., “Three ‘low Dt’ options for planarizing the pre-metal dielectric on an advanced double poly BiCMOS process,” 139 J. Electrochem Soc 532-6 (1992), which is hereby incorporated by reference.
In most cases, successful planarization of severe topologies is achieved by a single or double SOG deposition+etchback step in the following sequence:
However, in extreme topologies, when the volume of SOG is very large, shrinkage of SOG during planarization and post-planarization processing leads to formation of undesirable cracks or voids.
The proposed method seeks to alleviate the problem of SOG cracking by performing the following operations:
2“TEOS,” or tetraethoxysilane, is a popular and convenient feedstock for deposition of oxides from the vapor phase.
This process will leave a layer of dielectric between the 1st and the 2nd SOG layers in locations where conventional planarization technique are likely to crack or void. This provides enhanced reliability.
The thickness of the first SOG layer can be reduced to avoid any undesired effects, such as field inversion of underlying devices or enhanced hot-carrier injection.3
3See, e.g., Lifshitz et al., “Hot-carrier aging of the MOS transistor in the presence of spin-on glass as the interlevel dielectric,” 12 IEEE ELECTRON DEVICE LETTERS 140-2 (March 1991), which is hereby incorporated by reference.
A positive sloped valley is produced for second dielectric deposition. The step coverage will be enhanced due to this positive slope.
The structure provided by these steps has improved resistance to cracking, and improved resistance to other undesirable possible effects of thick spin-on glass layers.
According to a disclosed class of innovative embodiments, there is provided: An integrated circuit fabrication method, comprising the steps of: providing a partially fabricated integrated circuit structure; applying and curing spin-on glass, to form a first dielectric; depositing dielectric material under vacuum conditions, to form a second dielectric layer over said first layer; applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers; performing a global etchback to substantially remove said dielectric stack from high points of said partially fabricated structure; deposition of an interlevel dielectric; etching holes in said interlevel dielectric in predetermined locations; and depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
According to a disclosed class of innovative embodiments, there is provided: An integrated circuit fabrication method, comprising the steps of: providing a partially fabricated integrated circuit structure; applying and curing spin-on glass, to form a first dielectric; depositing silicon dioxide under vacuum conditions, to form a second dielectric layer over said first layer; applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers; performing a global etchback to substantially remove said dielectric stack from high points of said partially fabricated structure; deposition of an interlevel dielectric; etching holes in said interlevel dielectric in predetermined locations; and depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
According to a disclosed class of innovative embodiments, there is provided: An integrated circuit fabrication method, comprising the steps of: providing a partially fabricated integrated circuit structure; applying and curing spin-on glass, to form a first dielectric layer; depositing dielectric material under vacuum conditions, to form a second dielectric layer over said first layer, said second dielectric layer having a thickness equal to or less than said first layer; applying and curing spin-on glass, to form a dielectric stack including a third dielectric layer over said first and second layers, said third dielectric layer having a thickness equal to or greater than said second layer; performing a global etchback to substantially remove said dielectric stack from high points of said partially fabricated structure; deposition of an interlevel dielectric; etching holes in said interlevel dielectric in predetermined locations; and depositing and patterning a metallization layer to form a desired pattern of connections, including connections through said holes.
According to a disclosed class of innovative embodiments, there is provided: An integrated circuit, comprising: an active device structure, including therein a substrate, active device structures, isolation structures, and one or more patterned thin film conductor layers including an uppermost conductor layer; and a planarization structure, overlying recessed portions of said active device structure, comprising a layer of sol-gel-deposited dielectric overlain by a layer of vacuum-deposited dielectric overlain by a further layer of sol-gel-deposited dielectric; an interlevel dielectric overlying said planarization structure and said active device structure, and having via holes therein which extend to selected locations of said uppermost conductor layer; and an additional thin-film patterned conductor layer which overlies said interlevel dielectric and extends through said via holes to said selectred locations of said uppermost conductor layer.
The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:
The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
The disclosed process steps can be applied, for example, after fabrication of the first metal layer. Thus, the starting structure would be patterned metallization lines running over an interlevel dielectric which includes contact holes, and also has topographical excursions due to the underlying polysilicon layer(s) and field oxide layer. The maximum topographical excursion will include contributions from all of these. (However, the disclosed innovations can also be applied after fabrication of the second metal layer, before deposition of a third metal layer.)
As shown in
As shown in
A global etchback step is then performed, to remove the SOG from flat areas. The resulting surface contour, as shown in
A first layer 1 of SOG is deposited as in FIG. 1A. That is, for example, a siloxane-based spin-on glass4 is spun on to a thickness of 2000 Å over flat areas, and is then cured for 60 minutes at 425° C.
4Such materials may be obtained, for example, from Ohka America™ or Allied Signal™ or other suppliers.
A layer 3 of low-temperature oxide is then deposited, to a thickness of 2000 Å. (For example, this may be done by plasma-enhanced deposition of TEOS.) This produces the structure shown in FIG. 2B.
A second layer 2 of SOG is then be spun on and cured, to provide an additional thickness of e.g. 3000 Å in flat areas.
A global etchback step is then performed, to remove the SOG and TEOS from flat areas. The resulting surface contour, as shown in
For simplicity, the drawing of
A first layer 1 of SOG is spun on and cured to produce a thickness of 2000 Å over flat areas, as shown in FIG. 3A.
A layer 3 of low-temperature oxide is then deposited, to a thickness of 3000 Å. (For example, this may be done by plasma-enhanced deposition of TEOS.) This produces the structure shown in FIG. 3B.
A second layer 2 of SOG is then be spun on and cured, to provide an additional thickness of e.g. 2000 Å in flat areas.
A global etchback step is then performed, to remove the SOG and TEOS from flat areas. The resulting surface contour, as shown in
For simplicity, the drawing of
In alternative embodiments, it is also possible to deposit a plasma oxide before the first layer of spin-on glass. (This is commonly done to prevent direct contact between the SOG and the underlying metallization.) In this embodiment, 1000 Å-5000 Å of (for example) TEOS oxide would be deposited before the first layer of SOG.
Processing then continues with deposition of an interlevel dielectric, such as PSG, and conventional further processing steps.
One particular advantage of the disclosed invention is that it can be very easily implemented (in at least some processes) by a simple transposition of steps (depositing the low-temperature oxide before, rather than after, the second layer of spin-on glass).
It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts.
The disclosed innovative steps have been described in the context of via formation (e.g. forming connections from second metal to first metal, or third metal to second metal). Due to the accumulated topographical excursions, planarization is especially desirable at these stages. However, the disclosed innovative concepts can also be applied to planarization of lower levels as well.
The disclosed innovative concepts can also be applied to other spin-on materials, such as polyimide or polymethylmethacrylate.
As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4253907 *||Mar 28, 1979||Mar 3, 1981||Western Electric Company, Inc.||Anisotropic plasma etching|
|US4354896 *||Aug 5, 1980||Oct 19, 1982||Texas Instruments Incorporated||Formation of submicron substrate element|
|US4384938 *||May 3, 1982||May 24, 1983||International Business Machines Corporation||Reactive ion etching chamber|
|US4654112 *||Sep 26, 1984||Mar 31, 1987||Texas Instruments Incorporated||Oxide etch|
|US4657628 *||Mar 7, 1986||Apr 14, 1987||Texas Instruments Incorporated||Process for patterning local interconnects|
|US4660278 *||Jun 26, 1985||Apr 28, 1987||Texas Instruments Incorporated||Process of making IC isolation structure|
|US4676867 *||Jun 6, 1986||Jun 30, 1987||Rockwell International Corporation||Planarization process for double metal MOS using spin-on glass as a sacrificial layer|
|US4707218 *||Oct 28, 1986||Nov 17, 1987||International Business Machines Corporation||Lithographic image size reduction|
|US4721548 *||May 13, 1987||Jan 26, 1988||Intel Corporation||Semiconductor planarization process|
|US4755476 *||Nov 17, 1986||Jul 5, 1988||Siemens Aktiengesellschaft||Process for the production of self-adjusted bipolar transistor structures having a reduced extrinsic base resistance|
|US4792534 *||Dec 15, 1986||Dec 20, 1988||Kabushiki Kaisha Toshiba||Method of manufacturing a semiconductor device involving sidewall spacer formation|
|US4801350 *||Dec 29, 1986||Jan 31, 1989||Motorola, Inc.||Method for obtaining submicron features from optical lithography technology|
|US4801560 *||Oct 2, 1987||Jan 31, 1989||Motorola Inc.||Semiconductor processing utilizing carbon containing thick film spin-on glass|
|US4824767 *||Jun 2, 1987||Apr 25, 1989||Intel Corporation||Dual glass contact process|
|US4894351 *||Feb 16, 1988||Jan 16, 1990||Sprague Electric Company||Method for making a silicon IC with planar double layer metal conductors system|
|US4912061 *||Apr 4, 1988||Mar 27, 1990||Digital Equipment Corporation||Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer|
|US4962414 *||Jun 8, 1989||Oct 9, 1990||Sgs-Thomson Microelectronics, Inc.||Method for forming a contact VIA|
|US4986878 *||Jul 19, 1988||Jan 22, 1991||Cypress Semiconductor Corp.||Process for improved planarization of the passivation layers for semiconductor devices|
|US5003062 *||Apr 19, 1990||Mar 26, 1991||Taiwan Semiconductor Manufacturing Co.||Semiconductor planarization process for submicron devices|
|US5063176 *||May 30, 1990||Nov 5, 1991||Hyundai Electronics Industries Co., Ltd.||Fabrication of contact hole using an etch barrier layer|
|US5068711 *||Mar 19, 1990||Nov 26, 1991||Fujitsu Limited||Semiconductor device having a planarized surface|
|US5110763 *||Jan 22, 1991||May 5, 1992||Yamaha Corporation||Process of fabricating multi-level wiring structure, incorporated in semiconductor device|
|US5117273 *||Nov 16, 1990||May 26, 1992||Sgs-Thomson Microelectronics, Inc.||Contact for integrated circuits|
|US5158910 *||Nov 26, 1990||Oct 27, 1992||Motorola Inc.||Process for forming a contact structure|
|US5166088 *||Jun 25, 1991||Nov 24, 1992||Sharp Kabushiki Kaisha||Method of manufacturing semiconductor device contact vias in layers comprising silicon nitride and glass|
|US5244841 *||Dec 10, 1991||Sep 14, 1993||Applied Materials, Inc.||Method for planarizing an integrated circuit structure using low melting inorganic material and flowing while depositing|
|US5250472 *||Sep 3, 1992||Oct 5, 1993||Industrial Technology Research Institute||Spin-on-glass integration planarization having siloxane partial etchback and silicate processes|
|US5266525 *||Aug 7, 1991||Nov 30, 1993||Seiko Epson Corporation||Microelectronic interlayer dielectric structure and methods of manufacturing same|
|US5310720 *||Feb 24, 1993||May 10, 1994||Fujitsu Limited||Process for fabricating an integrated circuit device by forming a planarized polysilazane layer and oxidizing to form oxide layer|
|US5320983 *||Feb 6, 1991||Jun 14, 1994||Mitel Corporation||Spin-on glass processing technique for the fabrication of semiconductor devices|
|US5331117 *||Nov 12, 1992||Jul 19, 1994||Sgs-Thomson Microelectronics, Inc.||Method to improve interlevel dielectric planarization|
|US5399533 *||Dec 1, 1993||Mar 21, 1995||Vlsi Technology, Inc.||Method improving integrated circuit planarization during etchback|
|US5435888 *||Dec 6, 1993||Jul 25, 1995||Sgs-Thomson Microelectronics, Inc.||Enhanced planarization technique for an integrated circuit|
|US5534731 *||Oct 28, 1994||Jul 9, 1996||Advanced Micro Devices, Incorporated||Layered low dielectric constant technology|
|DE410244C *||Feb 2, 1924||Feb 26, 1925||Friedrich Lunow||Loseblaetterbuch mit schwingbar gelagerten ineinander eintretenden Aufreihern|
|EP0111706A1 *||Nov 3, 1983||Jun 27, 1984||International Business Machines Corporation||Sidewall isolation for gate of field effect transistor and process for the formation thereof|
|EP0185787A1 *||Dec 21, 1984||Jul 2, 1986||Deutsche ITT Industries GmbH||Plastic encapsulated semiconductor component|
|EP0265638A2 *||Sep 8, 1987||May 4, 1988||International Business Machines Corporation||Lithographic image size reduction|
|EP0327412A1 *||Jan 6, 1989||Aug 9, 1989||Sgs-Thomson Microelectronics S.A.||Passivation process of a integrated circuit|
|EP0491408A2 *||Nov 7, 1991||Jun 24, 1992||Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno||Process for making planarized sub-micrometric trenches in integrated circuits|
|GB2083948A *||Title not available|
|GB2167901A *||Title not available|
|GB2227452A *||Title not available|
|JP31033131A *||Title not available|
|JPH0492453A *||Title not available|
|JPS6058635A *||Title not available|
|JPS6126240A *||Title not available|
|JPS61232646A *||Title not available|
|JPS62106645A *||Title not available|
|JPS63293946A *||Title not available|
|1||*||"A Margin-Free Contact Process Using an AI303 Etch-Stop Layer for High □□Density Devices", Fukase et al., IEDM, p. 837 (1992).|
|2||*||"A New Technology for Oxide Contact and Via Etch", by Pete Singer, □□Semiconductor International, p. 36 (1993). □□.|
|3||*||"A Super Self-Aligned Source/Drain MOSFET," Lau et al., IEDM, p. 358 □□(1987). □□.|
|4||*||"Advantages of Using Spin on Glass Layer in Interconnection Dielectric Planarization", Microelectronic Engineering, vol. 5 (1986).|
|5||*||"Doped Silicon Oxide Deposition by Atmospheric Pressure and Low Temperature Chemical Vapor Deposition Using Tetraethoxysilane and Ozone", Fujino et al., J. Electrochem. Society, vol. 138, No. 10, p. 3019 Oct. 1991.|
|6||*||"Etching Applications and Trends of Dry Etching", Ephrath et al., □□Semiconductor Technology and Computer Systems, Ch. 2, p. 26. 1991. □□.|
|7||*||"Etching-Applications and Trends of Dry Etching", by L.M. Eprath and G.S. □□ Mathad, Handbook of Advanced Technology and Computer Systems at 27 ff (1988).|
|8||*||"Hot-Carrier Aging of the MOS Transistor in the Presence of Spin-On Glass as the Interlevel Dielectric", by N. Lifschitz and G. Smolinsky, IEEE Electron Device Letters, vol. 12, No. 3, p. 140 (1991).|
|9||*||"Plasma Etch Anisotrophy", C.B. Zarowin, J. Electrochem. Soc., Solid-State □□Science and Technology, p. 1144 (1983).|
|10||*||"Polysilicon Planarization Using Spin-On Glass", S. Ramaswami and A. Nagy, J. Electrochem. Soc., vol. 139, No. 2, p. 591 (1992).|
|11||*||"Reactive Ion Etching", by B. Gorowitz and R. Saia, 8 VLSI Electronics, □□297ff (1984).|
|12||*||"The Effect of Plasma Cure Temperature on Spin-On Glass", by H. Namatsu and K. Minegishi, J. Electrochem. Soc., vol. 140, No., p. 140 (1991).|
|13||*||"Three 'Low Dt' Options for Planarizing the Premetal Dielectric on an Advanced Double Poly BiCMOS Process", by W. Dauksher, M. Miller, and C. Tracey, J. Electrochem. Soc., vol. 139, No. 2, p. 532 (1992).|
|14||*||Handbook on Semiconductors, (ed. C. Holson), vol. 4, p. 208 (1981).|
|15||*||IBM Technical Disclosure Bulletin, vol. 29, No. 3, p. 1328, Aug. 1986. □□.|
|16||*||IBM Technical Disclosure Bulletin, vol. 30, No. 8, p. 252, Jan. 1988.|
|17||*||Patent Abstracts of Japan, vol. 15, No. 348 (E-1107) Sep. 4, 1991 & JP-A-31 33 131 (Mitsubishi Electric Corp.) Jun. 6, 1991.|
|18||*||Research Disclosure No. 282, Oct. 1987, Havant GB p. 608, "Spin on Glass □□Insulator Enhancement".|
|19||*||VLSI Electronics Microstructures Science, vol. 8, ed. Norman Einspruch, p. □□298 (1984).|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7737017 *||Dec 23, 2008||Jun 15, 2010||Hynix Semiconductor Inc.||Semiconductor device having recess gate and isolation structure and method for fabricating the same|
|US7833861 *||Oct 1, 2007||Nov 16, 2010||Hynix Semiconductor Inc.||Semiconductor device having recess channel structure and method for manufacturing the same|
|US8067799||Nov 16, 2010||Nov 29, 2011||Hynix Semiconductor Inc.||Semiconductor device having recess channel structure and method for manufacturing the same|
|US9252080 *||Oct 15, 2014||Feb 2, 2016||Globalfoundries Inc.||Dielectric cover for a through silicon via|
|US20070059898 *||Mar 30, 2006||Mar 15, 2007||Dong-Suk Shin||Semiconductor devices including trench isolation structures and methods of forming the same|
|US20080157191 *||Oct 1, 2007||Jul 3, 2008||Hynix Semiconductor Inc.||Semiconductor device having recess channel structure and method for manufacturing the same|
|US20100078757 *||Apr 1, 2010||Hynix Semiconductor Inc.||Semiconductor device having recess gate and isolation structure and method for fabricating the same|
|US20110057261 *||Nov 16, 2010||Mar 10, 2011||Hynix Semiconductor Inc.||Semiconductor device having recess channel structure and method for manufacturing the same|
|U.S. Classification||257/644, 257/634, 257/647|
|International Classification||H01L21/3105, H01L21/768, H01L23/522, H01L21/316, H01L21/3205, H01L23/58|
|Cooperative Classification||H01L21/02274, H01L21/02126, H01L21/02164, H01L21/022, H01L21/02282, H01L21/02216, H01L21/31051, H01L21/31055, H01L21/768, H01L21/76819, H01L21/31612|
|European Classification||H01L21/768B4, H01L21/316B2B, H01L21/3105B2B, H01L21/768, H01L21/3105B, H01L21/02K2C1L5, H01L21/02K2E3L, H01L21/02K2C3, H01L21/02K2E3B6B, H01L21/02K2C7C4B, H01L21/02K2C1L1|