|Publication number||USRE39768 E1|
|Application number||US 10/283,165|
|Publication date||Aug 14, 2007|
|Filing date||Oct 30, 2002|
|Priority date||Oct 14, 1998|
|Also published as||US6140630|
|Publication number||10283165, 283165, US RE39768 E1, US RE39768E1, US-E1-RE39768, USRE39768 E1, USRE39768E1|
|Inventors||Howard E. Rhodes|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Non-Patent Citations (24), Referenced by (7), Classifications (19), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates generally to improved semiconductor imaging devices and in particular to an imaging device which can be fabricated using a standard CMOS process. Particularly, the invention relates to a CMOS imager having an array of image sensing cells and to the driving signals which operate the cells.
There are a number of different types of semiconductor-based imagers, including charge coupled devices (CCDs), photodiode arrays, charge injection devices and hybrid focal plan arrays. CCDs are often employed for image acquisition and enjoy a number of advantages which makes it the incumbent technology, particularly for small size imaging applications. CCDs are also capable of large formats with small pixel size and they employ low noise charge domain processing techniques. However, CCD imagers also suffer from a number of disadvantages. For example, they are susceptible to radiation damage, they exhibit destructive read out over time, they require good light shielding to avoid image smear and they have a high power dissipation for large arrays. Additionally, while offering high performance, CCD arrays are difficult to integrate with CMOS processing in part due to a different processing technology and to their high capacitances, complicating the integration of on-chip drive and signal processing electronics with the CCD array. While there has been some attempts to integrate on-chip signal processing with the CCD array, these attempts have not been entirely successful. CCDs also must transfer an image by line charge transfers from pixel to pixel, requiring that the entire array be read out into a memory before individual pixels or groups of pixels can be accessed and processed. This takes time, CCDs may also suffer from incomplete charge transfer from pixel to pixel during charge transfer which also results in image smear.
Because of the inherent limitations in CCD technology, there is an interest in CMOS imagers for possible use as low cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits would be beneficial to many digital applications such as, for example, in cameras, scanners, machine vision systems, vehicle navigation systems, video telephones, computer input devices, surveillance systems, auto focus systems, star trackers, motion detection systems, image stabilization systems and data compression systems for high-definition television.
The advantages of CMOS imagers over CCD imagers are that CMOS imagers have a low voltage operation and low power consumption; CMOS imagers are compatible with integrated on-chip electronics (control logic and timing, image processing, and signal conditioning such as A/D conversion); CMOS imagers allow random access to the image data; and CMOS imagers have lower fabrication costs as compared with the conventional CCD since standard CMOS processing techniques can be used. Additionally, low power consumption is achieved for CMOS imagers because only one row of pixels at a time needs to be active during the readout and there is no charge transfer (and associated switching) from pixel to pixel during image acquisition. On-chip integration of electronics is particularly advantageous because of the potential to perform many signal conditioning functions in the digital domain (versus analog signal processing) as well as to achieve a reduction in system size and cost.
A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including either a photogate or a photodiode overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output field effect transistor formed in the substrate and a charge transfer section formed on the substrate adjacent the photogate or photodiode having a sensing node, typically a floating diffusion node, connected to the gate of an output transistor. The imager may include at least one electronic device such as a transistor for transferring charge from the underlying portion of the substrate to the floating diffusion node and one device, also typically a transistor, for resetting the node to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node accompanied by charge amplification; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node. The charge at the floating diffusion node is typically converted to a pixel output voltage by a source follower output transistor. The photosensitive element of a CMOS imager pixel is typically either a depleted p-n junction photodiode or a field induced depletion region beneath a photogate. For photo diodes, image lag can be eliminated by completely depleting the photodiode upon readout.
CMOS imagers of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12) pp. 2046-2050, 1996; Mendis et al, “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3) pp. 452-453, 1994 as well as U.S. Pat. No. 5,708,263 and U.S. Pat. No. 5,471,515, which are herein incorporated by reference.
To provide context for the invention, an exemplary CMOS imaging circuit is described below with reference to FIG. 1. The circuit described below, for example, includes a photogate for accumulating photo-generated charge in an underlying portion of the substrate. It should be understood that the CMOS imager may include a photodiode or other image to charge converting device, in lieu of a photogate, as the initial accumulator for photo-generated charge.
Reference is now made to
The photodetector circuit 14 is shown in part as a cross-sectional view of a semiconductor substrate 16 typically a p-type silicon, having a surface well of p-type material 20. An optional layer 18 of p-type material may be used if desired, but is not required. Substrate 16 may be formed of, for example, Si, SiGe, Ge, and GaAs. Typically the entire substrate 16 is p-type doped silicon substrate and may contain a surface p-well 20 (with layer 18 omitted), but many other options are possible, such as, for example p on p− substrates, p on p+ substrates, p-wells in n-type substrates or the like. The terms wafer or substrate used in the description includes any semiconductor-based structure having an exposed surface in which to form the circuit structure used in the invention. Wafer and substrate are to be understood as including, silicon-on-insulator (SOI) technology, silicon-on-sapphire (SOS) technology, doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation.
An insulating layer 22 such as, for example, silicon dioxide is formed on the upper surface of p-well 20. The p-type layer may be a p-well formed in substrate 16. A photogate 24 thin enough to pass radiant energy or of a material which passes radiant energy is formed on the insulating layer 22. The photogate 24 receives an applied control signal PG which causes the initial accumulation of pixel charges in n+ region 26. The n+ type region 26, adjacent one side of photogate 24, is formed in the upper surface of p-well 20. A transfer gate 28 is formed on insulating layer 22 between n+ type region 26 and a second n+ type region 30 formed in p-well 20. The n+ regions 26 and 30 and transfer gate 28 form a charge transfer transistor 29 which is controlled by a transfer signal TX. The n+ region 30 is typically called a floating diffusion region. It is also a node for passing charge accumulated thereat to the gate of a source follower transistor 36 described below. A reset gate 32 is also formed on insulating layer 22 adjacent and between n+ type region 30 and another n+ region 34 which is also formed in p-well 20. The reset gate 32 and n+ regions 30 and 34 form a reset transistor 31 which is controlled by a reset signal RST. The n+ type region 34 is coupled to voltage source VDD, e.g., 5 volts. The transfer and reset transistor 29, 31 are n-channel transistors as described in this implementation of a CMOS imager circuit in a p-well. It should be understood that it is possible to implement a CMOS imager in an n-well in which case each of the transistors would be p-channel transistors. It should also be noted that while
Photodetector circuit 14 also includes two additional n-channel transistors, source follower transistor 36 and row select transistor 38. Transistors 36, 38 are coupled in series, source to drain, with the source of transistor 36 also coupled over lead 40 to voltage source VDD and the drain of transistor 38 coupled to a lead 42. The drain of row select transistor 38 is connected via conductor 42 to the drains of similar row select transistors for other pixels in a given pixel row. A load transistor 39 is also coupled between the drain of transistor 38 and a voltage source VSS, e.g. 0 volts. Transistor 39 is kept on by a signal VLN applied to its gate.
The imager includes a readout circuit 60 which includes a signal sample and hold (S/H) circuit including a S/H n-channel field effect transistor 62 and a signal storage capacitor 64 connected to the source follower transistor 36 through row transistor 38. The other side of the capacitor 64 is connected to a source voltage VSS. The upper side of the capacitor 64 is also connected to the gate of a p-channel output transistor 66. The drain of the output transistor 66 is connected through a column select transistor 68 to a signal sample output node VOUTS and through a load transistor 70 to the voltage supply VDD. A signal called “signal sample and hold” (SHS) briefly turns on the S/H transistor 62 after the charge accumulated beneath the photogate electrode 24 has been transferred to the floating diffusion node 30 and from there to the source follower transistor 36 and through row select transistor 38 to line 42, so that the capacitor 64 stores a voltage representing the amount of charge previously accumulated beneath the photogate electrode 24.
The readout circuit 60 also includes a reset sample and hold (S/H) circuit including a S/H transistor 72 and a signal storage capacitor 74 connected through the S/H transistor 72 and through the row select transistor 38 to the source of the source follower transistor 36. The other side of the capacitor 74 is connected to the source voltage VSS. The upper side of the capacitor 74 is also connected to the gate of a p-channel output transistor 76. The drain of the output transistor 76 is connected through a p-channel column select transistor 78 to a reset sample output node VOUTR and through a load transistor 80 to the supply voltage VDD. A signal called “reset sample and hold” (SHR) briefly turns on the S/H transistor 72 immediately after the reset signal RST has caused reset transistor 31 to turn on and reset the potential of the floating diffusion node 30, so that the capacitor 74 stores the voltage to which the floating diffusion node 30 has been reset.
The readout circuit 60 provides correlated sampling of the potential of the floating diffusion node 30, first of the reset charge applied to node 30 by reset transistor 31 and then of the stored charge from the photogate 24. The two samplings of the diffusion node 30 charges produce respective output voltages VOUTR and VOUTS of the readout circuit 60. These voltages are then subtracted (VOUTS−VOUTR) by subtractor 82 to provide an output signal terminal 81 which is an image signal independent of pixel to pixel variations caused by fabrication variations in the reset voltage transistor 31 which might cause pixel to pixel variations in the output signal.
It should also be noted that CMOS imagers may dispense with the transfer gate 28 and associated transistor 29, or retain these structures while biasing the transfer transistor 29 to an always “on” state.
The operation of the charge collection of the CMOS imager is known in the art and is described in several publications such as Mendis et al., “Progress in CMOS Active Pixel Image Sensors,” SPIE Vol. 2172, pp. 19-29 1994; Mendis et al., “CMOS Active Pixel Image Sensors for Highly Integrated Imaging Systems,” IEEE Journal of Solid State Circuits, Vol. 32(3), 1997; and Eric R, Fossum, “CMOS Image Sensors: Electronic Camera on a Chip,” IEDM Vol. 95 pages 17-25 (1995) as well as other publications. These references are incorporated herein by reference.
Prior CMOS imagers suffer from inconsistent noise effects, voltage drops and leakage across the reset transistor 31, the row select transistor 38 and the transfer transistor 29. These affect the dynamic range of the pixel output as well as the ability of the pixel to accurately depict an image. Moreover, due to imprecision in the fabrication process, the electrical properties of these transistors will vary from pixel to pixel causing inconsistent output for the same level of charge from pixel to pixel. Since the size of the pixel electrical signal is very small due to the collection of photons in the photo array, the signal to noise ratio of the pixel should be as high as possible and charge leakage within a pixel as low as possible. Moreover, pixel output and the leakage of charge must be as consistent as possible from pixel to pixel.
The present invention is designed to improve variations in the reset voltage and the leakage characteristics of a CMOS imager pixel while improving the consistency of the pixel to pixel output of the pixel array and increasing the dynamic range of the pixel output. This is accomplished by driving one or more of the reset gate, transfer gate (if used) and the row select gate with one or more charge pumps. The charge pump provides a higher voltage than the supply voltage VDD to improve the gating operation of the reset, transfer and row select transistors. The charge pump increases the voltage to the reset gate so that the voltage drop across the reset transistor does not lower the VDD reset charge at floating diffusion node 30 and increases the voltage to the transfer gate to allow barrier and well lowering in its operation. By overdriving one or more of the gates of the reset, transfer and row select transistors with the output of a charge pump, pixel to pixel fabrication differences in electrical characteristics of these transistors can also be avoided. Moreover, if a photogate is used to acquire image charges this too may be overdriven by an output voltage from a charge pump. Since the photogate turn on voltage is typically VSS, e.g., 0 volts, a charge pump is used which drives the photogate with an even lower voltage than VSS. Additionally, the photogate may be overdriven, e.g. 6 volts, during charge collection to assure that charge is effectively collected by the device.
The above and other advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.
The present invention will now be described with reference to the figures. Reference is now made to FIG. 4. This figure shows a portion of an active pixel array constructed according to the present invention in which respective charge pumps 300, 301 and 302 are used to supply the gate voltages for the reset, transfer and row select transistors 31, 29 and 38. In addition, a charge pumps 303 and 304 are shown for providing a gate voltage to a photogate 24 for charge transfer and charge storage respectively. This figure shows a 2×2 array of pixels for simplification. It should be understood that the invention is directed to a M×N multiple pixel array of any size.
The operation of the
Signal ROW SELECT1 on lead 86 turns row select transistor 38 on. The voltage controlled by the row select signal 86 is a charge pump 302 output voltage. Row select 86 is connected to charge pump 302 to overdrive the row select transistor, that is, the gate voltage of transistor 38 is higher than the VDD supply voltage. In a 5V VDD system, charge pump 302 will supply at least VDD+Vth volts to the gate of row select transistor 38 where Vth is the threshold voltage for transistor 38. The reset signal RST1 turns on transistor 31 which causes the floating diffusion node 30 to be reset to a potential of VDD−Vth, where Vth is the threshold voltage of the reset transistor 31. In the invention, the actual gate signal to transistor 31 is supplied by charge pump 300 to overdrive the gate of the reset transistor with a voltage of at least the value VDD+Vth to maintain a constant voltage reset value on node 30 at VDD. By having a higher reset voltage available at node 30, a wider dynamic response range is available for the pixel output signal and variation in the voltage at which the floating diffusion node 30 is reset due to the reset transistor 31 Vth variation is reduced.
The photogate 24 is also supplied from a charge pump 304, ensuring that the photogate to be overdriven to its on state to ensure that all possible collected charge for an image signal is stored in the imager substrate beneath the photogate until it is to be transferred out of the collection area. The photogate 24 is also supplied from a charge pump 303 in response to photogate signal PG over line 46, ensuring that the photogate to be overdriven to its on state to ensure that all possible collected charge for an image signal is transferred from the substrate beneath the photogate to the collection area.
In the invention, the charge pumps 300, 301 provide voltage to the reset gate 32 and transfer gate 28 at a potential which is greater than the supply potential VDD. The pumped voltage enhances the performance of the transfer and reset transistors. In order to turn “on” the various transistors of the pixel array, a gate voltage to the transistor must exceed a source or drain voltage (depending on the type of transistor) by a threshold voltage Vth. However, the threshold voltage (Vth) may differ for each transistor of a pixel array due to manufacturing imperfections. As a consequence, when all transistors of the array are turned “on” or “off” using the voltage supply potentials to supply control signals to the gates of the transistors, some transistors which are turned “on” are more “on” than other transistors thereby inconsistently transferring and/or amplifying the pixel charges transferred to the pixel output line 42. Likewise, some of the transistors which are turned “off” are more “off” than other transistors causing leakage. This is reflected as an improper output of signals reflecting the charges collected by the photodetector circuit 14.
The charge pumps 300, 301, 302 and 304 help to overcome the inconsistent on/off threshold voltages (Vth) of the transistors by overdriving the gates with voltages which ensure that they turn on or off as required, regardless of manufacturing inconsistencies. Also, the charge pump 300 increases the dynamic operating range of each pixel since the full reset voltage VDD will be applied to the floating diffusion node 30. The charge pump 303 ensures that the maximum possible charges are collected in the collection region beneath the photogate.
While multiple charge pumps 300, 301, 302, 303, 304 are shown in
Reference is now made to
An output transistor 325 is connected between node 350 of capacitors 315 and a circuit output 355 node. An input signal SIG, which might vary between VDD and VSS, is output as an elevated potential signal SIGp which may vary between VSS and VDDp where VDDp>VDD. Where the potential signal SIGp is desired to be less than the operating voltage, i.e., charge pump 303, the output signal SIGp which may vary between VSSp and VDD where VSSp<VSS.
Both clamp circuits 320, 330 turn on and off at the same time, but the connection of clamp circuit 330 across capacitor 335 and in series with the output transistor has the result that the operation of the second clamp circuit 330 causes the output transistor 325 to conduct when potential at the node 350 is at a high potential. The rising edge of the oscillator 310 couples a high voltage through the capacitors 315, 335 which shuts the clamps 320, 330 off and allows the nodes 350, 355 to go high. The falling edge of the output of the oscillator 310 couples a drop in potential through the capacitors 315, 335, at which point, the clamps 320, 330 turns on, preventing the nodes 350, 355 from going low. A decoupling capacitor 345 further cooperates with the charge pump 300 in order to provide a steady boosted output which is switched by input signal SIG.
For operating the photogate PG, the charge pump 303 is configured to supply an output voltage VSSp where VSSp<VSS. For collecting charge in the photogate, the charge pump 304 is configured to supply an output voltage VPGp where VPGp is greater than input voltage VDD.
As noted, the particular construction of the charge pump is not critical to the invention and many circuits besides the
A typical processor based system which includes a CMOS imager device according to the present invention is illustrated generally at 400 in
A processor system, such as a computer system, for example generally comprises a central processing unit (CPU) 444 that communicates with an input/output (I/O) device 446 over a bus 452. The CMOS imager 442 also communicates with the system over bus 452. The computer system 400 also includes random access memory (RAM) 448, and, in the case of a computer system may include peripheral devices such as a floppy disk driver 454 and a compact disk (CD) ROM drive 456 and I/O devices like a keyboard and/or mouse which also communicate with CPU 444 over the bus 452. CMOS imager 442 is preferably constructed as an integrated circuit which includes the voltage charge pumps 300, 301 and 302, as previously described with respect to
It should again be noted that although the invention has been described with specific reference to a CMOS imaging circuit having a photogate 24 and a floating diffusion node 30, the invention has broader applicability and may be used in any CMOS imaging apparatus. Similarly, the process described above for charge collection, transfer and readout is but one method of many that could be used. Accordingly, the above description and accompanying drawings are only illustrative of preferred embodiments which can achieve the features and advantages of the present invention. It is not intended that the invention be limited to the embodiments shown and described in detail herein. The invention is only limited by the scope of the following claims.
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|U.S. Classification||250/208.1, 348/294, 257/239|
|International Classification||H04N5/369, H04N5/3745, H04N5/363, H04N5/374, H01J40/14, H01L27/146|
|Cooperative Classification||H01L27/14609, H04N5/3698, H04N5/374, H04N5/3745, H04N5/363|
|European Classification||H04N5/369C, H04N5/363, H04N5/374, H04N5/3745, H01L27/146A4|
|Nov 13, 2007||CC||Certificate of correction|
|Apr 18, 2008||FPAY||Fee payment|
Year of fee payment: 8
|Apr 11, 2012||FPAY||Fee payment|
Year of fee payment: 12
|Mar 28, 2016||AS||Assignment|
Owner name: APTINA IMAGING CORPORATION, CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038274/0385
Effective date: 20080926
|Apr 6, 2016||AS||Assignment|
Owner name: MICRON TECHNOLOGY INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RHODES, HOWARD E.;REEL/FRAME:038205/0159
Effective date: 19981012