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Publication numberUSRE40061 E1
Publication typeGrant
Application numberUS 10/346,860
Publication dateFeb 12, 2008
Filing dateJan 16, 2003
Priority dateApr 6, 1993
Publication number10346860, 346860, US RE40061 E1, US RE40061E1, US-E1-RE40061, USRE40061 E1, USRE40061E1
InventorsMichael B. Ball
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Multi-chip stacked devices
US RE40061 E1
Abstract
A multiple stacked die device is disclosed that contains up to four dies and does not exceed the height of current single die packages. Close-tolerance stacking is made possible by a low-loop-profile wire-bonding operation and thin-adhesive layer between the stacked dies.
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Claims(12)
1. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer of about 0.001 inches affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first diebonding pads, said wire bond having a wire height above the bonding pad of about 0.006 inches, and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. two additional dies affixed above the second die by additional subsequent layers of adhesive of about 0.008 inches and having additional thin wires bonded to additional bonding pads and lead fingers; and
g. an encapsulated layer surrounding all dies, adhesive layers, and thin wires wherein a total encapsulated-package height is about 0.110 inches.
2. A multiple-die low-profile semiconductor device comprising:
a. a lead-frame paddle supported by a lead frame;
b. a controlled, first, thin-adhesive layer of about 0.001 to 0.005 inches affixing a first die above the paddle;
c. a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads, said low-loop wire ball bond having a wire height above the bonding pads of about 0.006 inches and a second wire bond to a plurality of adjacent lead-frame lead fingers;
d. a second thin-adhesive layer of about 0.008 to 0.010 inches affixing a second die above the first die;
e. a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
f. an encapsulated layer surrounding all die adhesive layers and thin wires wherein a total encapsulation-layer height is about 0.070 inches.
3. A method for fabricating a multiple-die, low-profile semiconductor device, comprising:
a.providing a lead frame having a lead frame paddle and a plurality of lead fingers;
b.affixing to said paddle a first die having a plurality of first die-bonding pads;
c.connecting bond wires between each of said plurality of first die-bonding pads and corresponding lead fingers of said plurality of lead fingers by way of a low-loop wire bond on each of said plurality of first die-bonding pads and a wire bond on each of said corresponding lead fingers;
d.affixing to said first die, following said connecting bond wires, a second die having a plurality of second die-bonding pads;
e.connecting bond wires between each of said plurality of second die-bonding pads and corresponding lead fingers of said plurality of lead fingers by way of a low-loop wire bond on each of said plurality of second die-bonding pads and a wire bond on each of said corresponding lead fingers; and
f.affixing two additional dies above said second die.
4. The method of claim 3, further comprising encapsulating all dies and bond wires with an encapsulation layer having a height of about 0.110inchesinch.
5. The method of claim 3, wherein die-bonding pads of said first plurality of die-bonding pads are connected to said corresponding lead fingers of said plurality of lead fingers in parallel with die-bonding pads of said second plurality of die-bonding pads.
6. The method of claim 3, wherein die-bonding pads of said first plurality of die-bonding pads and die-bonding pads of said second plurality of die-bonding pads are each connected to individual ones of said plurality of lead fingers.
7. The method of claim 3, wherein said providing comprises providing a lead frame having a downset lead frame paddle and a plurality of lead fingers upset relative to said downset lead frame paddle.
8. The method of claim 3, wherein said connecting bond wires between each of said first and second pluralities of die-bonding pads and corresponding ones of said lead fingers comprises forming said low-loop wire bonds on each of said die-bonding pads to be ball bonds.
9. The method of claim 3, wherein said connecting bond wires between each of said first and second pluralities of die-bonding pads and corresponding ones of said lead fingers comprises forming said wire bonds on each of said corresponding lead fingers to be wedge bonds.
10. The method of claim 3, wherein said affixing said first die to said lead frame paddle comprises disposing a layer of adhesive between said lead frame paddle and said first die.
11. The method of claim 10, wherein said disposing said layer of adhesive comprises forming said layer of adhesive to be about 0.001inchesinch thick.
12. The method of claim 3, wherein said affixing said second die to said first die comprises disposing a layer of adhesive between said first die and said second die.
Description
CROSS REFERENCE TO RELATED APPLICATION

This reissue application is a divisional of application Ser. No. 09/427,123, filed Oct. 21, 1999, pending, which is a continuation of reissue application Ser. No. 08/610,127, filed Feb. 29, 1996, now U.S. Pat. Re. 36,613, reissued on Mar. 14, 2000, from U.S. Pat. No. 5,291,061, dated Mar. 1, 1994.

FIELD OF THE INVENTION

This invention relates to a multiple die module that has a thickness the same or less than a standard package but has two or more stacked die, thereby increasing device density.

BACKGROUND OF THE INVENTION

Semiconductor devices are typically constructed en masse on a silicon or gallium arsenide wafer through a process which comprises a number of deposition, masking, diffusion, etching, and implanting steps. When the devices are sawed into individual rectangular units, each takes the form of an integrated circuit (IC) die. In order to interface a die with other circuitry, it is (using contemporary conventional packaging technology) mounted on a lead frame paddle of a lead-frame strip which consists of a series of interconnected lead frames, typically ten in a row. The die-mounting paddle of a standard lead frame is larger than the die itself, and it is surrounded by multiple lead fingers of individual leads. The bonding pads of the die are then connected one by one in a wire-bonding operation to the lead frame's lead finger pads with extremely fine gold or aluminum wire. Following the application of a protective layer to the face of the die, it, and a portion of the lead frame to which it is attached, is encapsulated in a plastic material, as are all other die/lead-frame assemblies on the lead-frame strip. A trim-and-form operation then separates the resultant interconnected packages and bends the leads of each package into the proper configuration.

In the interest of higher performance equipment and lower cost, increased miniaturization of components and greater packaging density have long been the goals of the computer industry. IC package density is primarily limited by the area available for die mounting and the height of the package. Typical computer-chip heights in the art are about 0.110 inchesinch. A method of increasing density is to stack die or chips vertically.

U.S. Pat. No. 5,012,323, issued Apr. 30, 1991, having a common assignee with the present application, discloses a pair of rectangular integrated-circuit dice mounted on opposite sides of the lead frame. An upper, smaller die is back-bonded to the upper surface of the lead fingers of the lead frame via a first adhesively coated, insulated film layer. The lower, slightly larger die is face-bonded to the lower surface of the lead extensions within the lower lead-frame die-bonding region via a second, adhesively coated, insulative, film layer. The wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum wires. The lower die needs to be slightly larger in order that the die pads are accessible from above so that gold wire connections can be made to the lead extensions (fingers).

U.S. Pat. No. 4,996,587 (referred to hereafter as '587) shows a semiconductor chip package which uses a chip carrier to support the chips within a cavity. The chip carrier as shown in the figures has a slot that permits connection by wires to bonding pads which, in turn, connect to the card connector by conductors. An encapsulation material is placed only on the top surface of the chip in order to provide heat dissipation from the bottom surface when carriers are stacked.

A Japanese Patent No. 56-62351(A) issued to Sano in 1981 discloses three methods of mounting two chips on a lead frame and attaching the pair of semiconductor chips (pellets) to a common lead frame consisting of:

  • method 1 two chips mounted on two paddles;
  • method 2 one chip mounted over a paddle and one below not attached to the paddle; and
  • method 3 one chip attached above and one chip attached below a common paddle.
    The chips are apparently wired in parallel as stated in the “PURPOSE” of Sano.

The chips of patent '587 are also apparently wired in parallel by contacts on the “S” chips which contact the connection means.

It is the purpose of this invention to provide multiple stacked dies assembled in a special vertical configuration such that as many as four encapsulated dies will have a height no greater than existing 0.110-inch high dies and also have a separate lead and lead finger for each die pad connection.

SUMMARY OF THE INVENTION

The invention generally stated is a multiple-die low-profile semiconductor device comprising:

  • a lead-frame paddle supported by a lead frame;
  • a controlled, first, thin-adhesive layer affixing a first die above the paddle;
  • a plurality of thin wires having a first low-loop wire bond to a plurality of first die-bonding pads and a second wire bond to a plurality of adjacent lead-frame lead fingers;
  • a second thin-adhesive layer affixing a second die above the first die;
  • a second plurality of thin wires having low-loop wire bonds to a plurality of second die-bonding pads and second wire bonds to the plurality of lead fingers;
  • additional dies affixed above the second die, by additional subsequent layers of adhesive and having additional thin wires bonded to additionadditional bonding pads and lead fingers; and
  • an encapsulated layer surrounding all dies, adhesive layers, and thin wires.

Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be better understood and further advantages and uses thereof may become more readily apparent when considered in view of the following detailed description of exemplary embodiments, taken with the accompanied drawings, in which:

FIG. 1 is a partial plan view of the stacked die, lead fingers, and bonded wires of the present invention; and

FIG. 2 is a side elevation taken through lines 22 of FIG. 1 showing a four die stacking.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, the stacked die device 10 is shown prior to encapsulation disclosing the top die 12 mounted uponto the paddle 14 and other dies 16, 18, and 20 (FIG. 2) which are adhesively connected to each other by a controlled-thickness thermoplastic-adhesive layer at 22. Thermoplastic indicating“Thermoplastic” indicates that the adhesive sets at an elevated temperature. The group of four dies are attached to the paddle 14 by a controlled thin-adhesive layer 24.

Each of the die bonding pads 26 in double rows are electrically connected to multiple lead fingers 28A, 28B, 28C . . . 28N by thin (0.001 inch) gold or aluminum wires 30A, 30B, 30C . . . 30N; gold being the preferred metal. For clarity, only part of the 18 bonding pads, wires, and fingers are shown. The critical bonding method used at the die end pad 26 is an ultrasonic ball bondbond, as named by the shape of the bond as at 32. This first-installed bond and formed gold wire are low-loop wire bonds as seen at critical dimension 34, as will be described later.

The other end of gold wires 30 are attached to the lead fingers by a wedge bond 36, which is also an ultrasonic bond, indicating the use of ultrasonic energy to heat the wire 30 as it is compressed against the lead finger 28. The wedge bond is not used on the die because the bonding machine contacts the bonding surface and could damage this critical surface. The lead fingers may be formed upward as at 38 to permit the use of shorter wires 30.

Paddle 14 which supports the stack is attached to the lead frame typically at four corners as at 40 and also typically, in this application, would have a downset from the lead frame and lead fingers 28 as at dimension 42. The stack is finally encapsulated by a plastic or ceramic at 44.

A dimensional analysis is provided by referring to FIG. 2.

By careful control of layer thicknesses, it is possible to fabricate a four-stack die device having an overall height 46 of about 0.110 inchesinch which is the same height as a current single die. Starting at the bottom, the encapsulation thickness 48 is between 0.010 and 0.012 inchesinch. The paddle 74 14 thickness 50 can be between 0.005 and 0.010 inchesinch and is a matter of choice. The controlled adhesive-layer thickness 52 can be from 0.001 to 0.005 inchesinch. The individual dies 20, 18, 16, and 12 each have a thickness 54 of 0.012 inchesinch and the critical controlled, adhesive-layer thicknesses 56 between each die are between 0.008 and 0.010 inchesinch. These thin layers have to be slightly greater than the low-loop wire dimension 34, which is about 0.006 inchesinch. Finally, the top encapsulation thickness 58 is between 0.010 and 0.012 inchesinch so as to cover the top loop.

Thus, it can be seen by carefully controlling and minimizing the adhesive layer thicknesses 56, the top and bottom encapsulation thicknesses 48 and 58, and the paddle adhesive layer 52 that it is possible to have an overall height between 0.108 and 0.110 inchesinch overall for the four-stack die.

If the looser tolerances were used for a two-stack die, the height at 60 would be between 0.058 and 0.073 inchesinch and for a three-die stack it would be from 0.078 to 0.100 inchesinch.

The fabrication of these two or four-stack die devices, necessarily, has to be from the bottom up, since it is not possible to form the die pad wire ball bond 32 on the lower dies 16, 18, and 30, if the four dies are already stacked. This is due to the overhead space required by the wire bond machine.

The die pads 26 of each die can be each connected to an individual lead finger 28 or the dies can be wired in parallel. The former configuration would, therefore, require (for a four die stack) something less than 4×18=72 4×18=72 leads, while parallel connections would require something on the order of 22 or more pins, depending on the type of devices and system requirements. The final packages can be in the form of a small outline J-leaded (SOJ) package, a dual in-line package (DIP), a single in-line package (SIP), a plastic leaded chip carrier (PLCC), and a zig-zag in-line package (ZIP).

While a preferred embodiment of the invention has been disclosed, various modes of carrying out the principles disclosed herein are contemplated as being within the scope of the following claims. Therefore, it is understood that the scope of the invention is not to be limited except as otherwise set forth in the claims.

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US4567643Oct 24, 1983Feb 4, 1986Sintra-AlcatelMethod of replacing an electronic component connected to conducting tracks on a support substrate
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US4996587Mar 23, 1990Feb 26, 1991International Business Machines CorporationIntegrated semiconductor chip package
US5012323Nov 20, 1989Apr 30, 1991Micron Technology, Inc.Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5049976Jan 10, 1989Sep 17, 1991National Semiconductor CorporationStress reduction package and process
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7691668 *Dec 19, 2006Apr 6, 2010Spansion LlcMethod and apparatus for multi-chip packaging
US7888185 *Aug 17, 2006Feb 15, 2011Micron Technology, Inc.Semiconductor device assemblies and systems including at least one conductive pathway extending around a side of at least one semiconductor device
US8324716 *Mar 9, 2010Dec 4, 2012Spansion LlcMethod and apparatus for multi-chip packaging
US8384228 *Apr 29, 2009Feb 26, 2013Triquint Semiconductor, Inc.Package including wires contacting lead frame edge
US20100164124 *Mar 9, 2010Jul 1, 2010Yong DuMethod and apparatus for multi-chip packaging
Legal Events
DateCodeEventDescription
Jan 4, 2010ASAssignment
Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416
Effective date: 20091223