|Publication number||USRE40188 E1|
|Application number||US 10/318,583|
|Publication date||Mar 25, 2008|
|Filing date||Dec 12, 2002|
|Priority date||Feb 17, 1999|
|Also published as||CA2362962A1, CA2362962C, CN1155909C, CN1346473A, EP1203329A1, EP1203329A4, US6161213, WO2000049538A1|
|Publication number||10318583, 318583, US RE40188 E1, US RE40188E1, US-E1-RE40188, USRE40188 E1, USRE40188E1|
|Original Assignee||Icid, Llc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Non-Patent Citations (4), Referenced by (9), Classifications (18), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates in general to a system for uniquely identifying an integrated circuit (IC), and in particular to a device that may be embedded in the IC which, due to randomly occurring chip-to-chip or device-to-device parametric variations, produces a unique output identification for each IC chip in which it is implemented.
2. Description of Related Art
Integrated circuits are manufactured with batch processing intended to make all integrated circuit chips identical, thereby lowering manufacturing costs and improving quality. However, it is useful to be able to distinguish each individual integrated circuit from all others, for example to track its source of manufacture, or to identify a system employing the integrated circuit. Individually identifiable integrated circuits can be used to validate transactions, route messages, track items through customs, verify royalty counts, recover stolen goods, validate software, and many other uses.
It has been known to include circuits within a chip that produce a signal identifying the nature or type of the chip. U.S. Pat. No. 5,051,374, issued Sep. 24, 1991 to Kagawa et al., “Method of manufacturing a semiconductor device with identification pattern”, shows a technique for identifying the type of mask-programmed read-only memory (ROM). ROMs of different types may have indistinguishable visible structures, but the special processing steps described in this patent produce a visible pattern on the ROM identifying its nature. U.S. Pat. No. 4,150,331 issued Apr. 17, 1979 to Lacher, “Signature encoding for integrated circuits”, describes an embedded system that puts a type-specific identifier on the pins of a circuit when stimulated. U.S. Pat. No. 5,079,725 issued Jan. 7, 1992 to Geer et al., “Chip Identification Method for use with Scan Design Systems and Scan Testing Techniques”, describes a method for incorporating type specific identification into a scan test chain. These methods of identification are useful for indicating the type of component being manufactured or placed in an assembly, but they do not distinguish individual chip one from another.
It has been also known to customize each individual chip as it is manufactured in order to make it uniquely identifiable. Such customization may be performed as the chip is fabricated, typically by inscribing pattern on its die, or after it is fabricated, for example, by employing electrical or laser signals to alter its circuitry in some way. U.S. Pat. No. 5,642,307 issued Jun. 24, 1997 to Jernigan, “Die Identifier and Die Identification Method” includes a non-volatile, programmable read-only memory (PROM) on a chip. After the chip is fabricated, the PROM is programmed to store a date, a lot number, a wafer number, and a wafer position, as well as other useful manufacturing data. U.S. Pat. No. 4,419,747, issued Dec. 6, 1983, to Jordan, “Method and Device for Providing Process and Test Information in Semiconductors”, stores similar information in an extension of an existing programmable memory array. The information may be read back when an unusual combination of voltages is placed on the input pins and detected by the chip, overriding the normal function of the device.
U.S. Pat. No. 5,056,061, issued Oct. 8, 1991 to Akylas et al., “Circuit for encoding identification information on circuit die using FET capacitors” discloses the use of high voltage signals to break a capacitor structure within each individual chip so that some aspect of the chip's behavior is permanently altered in some identifiable way. U.S. Pat. No. 5,553,022, issued Sep. 3, 1996 to Weng et al., “Integrated circuit identification apparatus and method”, performs a similar breakdown on the gate oxide of a MOSFET. In both cases an oxide is permanently altered, and this requires careful circuit design and process characterization to do reliably. U.S. Pat. No. 4,766,516, issued Aug. 23, 1988 to Ozdemir et al., “Method and apparatus for securing integrated circuits from unauthorized copying and use”, teaches us to electronically after a semiconductor die with lasers or focused ion beams. While such approaches are effective to provide each chip with an ID, the additional processing steps needed to customize each individual chip add time and cost to the chip manufacturing process.
Other techniques do not result in an electrically detectable modification of the integrated circuit die. Instead, they physically inscribe a pattern onto an unused portion of the die surface, to be observed optically by a machine or by a person using a microscope. U.S. Pat. No. 5,350,715, issued Sep. 27, 1994 to Lee, “Chip identification scheme” teaches applying a pattern of dots to electrically inactive areas on each die site on a wafer. This may be done with an additional mask step applied to the whole wafer. U.S. Pat. No. 4,510,673, issued Apr. 16, 1995 to Shils et al., “Laser written chip identification method”, describes using an X-Y controllable laser beam to produce identification patterns on the surface of a chip.
While such methods can provide each chip with a unique identification, they require special processing steps during the semiconductor manufacturing process that add cost and time to the manufacturing process. What is needed is a method for reliably and easily identifying and authenticating individual integrated circuits that does not require any additional manufacturing steps or equipment.
An integrated circuit identification (ICID) circuit in accordance with one aspect of the invention produces a unique identification number or record (ID) for each chip in which it is included even though the ICID circuit is fabricated on all chips using identical masks. The ICID circuit includes a set of circuit cells and produces its output ID based on measurements of outputs of those cells that are functions of random parametric variations that naturally occur when fabricating chips. When the number of cells is large enough, each of millions of chips can be provided with a unique identifying ID without having to customize each chip.
In accordance with another aspect of the invention, the cells are organized into an array and the ICID circuit also includes a circuit for selecting each cell of the array in turn, measuring that element's output, and producing the chip ID based on the pattern of measured outputs of all cells of the array. When the number of elements in the array is large enough, the pattern of measured array element characteristics for an ICID circuit of one IC chip will be unique to a high degree of probability. The identification pattern will differ from that of an ICID circuit of any other IC, even when similar ICID circuits are installed in millions of other IC chips. Thus the value of the output data produced by an ICID circuit acts as a unique :fingerprint: for the chip in which it is installed that can be employed as an easily accessed chip-unique ID.
In accordance with a further aspect of the invention, in a preferred embodiment thereof, the elements of the array are suitably pairs of metal oxide semiconductor field effect (MOSFET) transistors having interconnected sources and gates. The measurable output of each MOSFET pair represents the difference between their drain currents, which is highly susceptible to fluctuations that naturally occur in chip fabrication.
The ICID circuit of the present invention provides a means for enabling each of millions of chips to uniquely and reliably identify itself without having to customize each individual chip using costly and time-consuming additional processing steps during or after chip fabrication.
The concluding portion of this specification particularly points out and distinctly claims the subject matter of the present invention. However, those skilled in the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the following descriptions in view of the accompanying drawings wherein like reference characters refer to like elements.
The present invention relates to an integrated circuit identification (ICID) circuit 38 as illustrated in
It has been known to provide each of a large number of IC chips with a non-volatile memory for storing and reading out an ID uniquely identifying each chip. However such prior art chip ID systems require that a separate ID be written into each individual IC using additional processing steps during or after IC fabrication. The additional customizing steps for each IC add time and cost to the IC manufacturing process. ICID 38, on the other hand, does not have to be customized in any way for each chip in which it is installed in order to ensure that its output ID is unique for each chip. Even though the same ICID 38 may be installed on millions of IC chips, the probability is low that the ICID circuits of any two chips will generate the same output ID number. The ICID circuit is therefore an improvement over prior art chip identification systems because it doesn't require any customization of individual ICs.
ICID 38 achieves this feat by deriving its output ID from measurements of a set of circuit parameters that naturally vary from chip-to-chip and from circuit element-to-element. Due to natural, random parametric variations, no two ICs are really alike. For example, try as we might, it is not possible to make two identical transistors even though we may form them by similar processes, using similar masks, in adjacent areas of the same IC die. We cannot make two transistors identical because their dimensions are the result of the random accumulation of photons through the photomask and their doping levels and distributions are the result of the random distribution of doping atoms from thermal diffusion and ion implantation. Designers have long been aware of the effect of such random parametric variations on the behavior of transistors and other IC circuit elements and have taken them into account when designing ICs. A good IC design ensures that all copies of an IC behave as expected even though the transistors and other circuit elements forming the ICs exhibit a random variation in operating characteristics from element-to-element and from chip-to-chip.
While such random parametric variations have been a problem that IC designers have had to overcome, ICID 38 of the present invention makes beneficial use of them. In the preferred embodiment of the invention, each ICID 38 includes an array of identically designed cells. Each cell is suitably a simple transistor circuit that produces a pair of currents whose difference is influenced by random parametric variations affecting the operating characteristics of the transistors forming the cell. ICID 38 measures the difference between the two output currents of each cell of the array and encodes the measurements for all cells into a single output ID that is unique to the particular combination of measurements. When the array is large enough, there is a very low probability that the cell array of an ICID 38 installed in any one IC chip will produce the same combination of measurements as an ICID circuit installed in any of millions of other IC chips. Thus an ID generated in such fashion can be used as a unique ID for each chip.
ICID 38 is advantageous over prior art chip identification systems because it does not require any custom modification to each individual chip during or after fabrication in order to make its ID unique. The acquisition and logging of a chip's ID can be easily and quickly done by an IC tester when it tests the chip's logic. ICID Architecture
A stimulus circuit 48 responds to the control input 36 by supplying row select data (ROW) and a column select data (COL) to array 46 to individually select and stimulate each of its cells in turn. As it selects a cell, stimulus circuit 48 sends timing signals (TIMING) to a measurement circuit 50 telling it when to measure a difference between the currents IH and IL of the selected cell. In the preferred embodiment of the invention, each cell includes P channel, metal oxide silicon field-effect transistors (MOSFETs). Stimulus circuit 48 also produces an N-Well bias control line WELL for controlling the bias for the N-Well underneath the P channel MOSFETs in the identification cell array 46. When ICID circuit is enabled, the N-Well is biased on, at the positive supply voltage, allowing the identification array to operate. When the ICID circuit is disabled, the N-Well is biased to the negative supply voltage, along with all the other signal lines connected to the identification cell array 46. This eliminates electrical stresses on the identification cells when the ICID circuit is not being used, helping protect the cells against drift.
Measurement circuit 50, sequenced by TIMING strobes from stimulus circuit 48, measures the current difference between IH and IL for each cell and, as described in detail below, produces a serial output ID having a value that is base on the particular pattern of measured current differences for all cells of array 46.
If the MOSFET pair 66 and 68 in the selected cell were truly identical, they would produce identical drain currents into AOH and AOL. However since random parametric variations ensure that MOSFETS 66 and 68 will differ somewhat even though we try to make them similar, their drain currents IH and IL will be somewhat mismatched. The amount of mismatch reflects the amount of parametric variations between the two transistors.
MOSFETs may also vary in conductivity as well as threshold, and variations in conductivity would appear in the graph of
MOSFET threshold mismatch
When we interconnect pairs of MOSFETs in the manner illustrated in
When the ICID circuit is behaving properly, error detection circuit 118 produces a logic zero followed by a logic one on each error output ERR during a portion of every identification period. There are eight clock cycles in an identification period. During four of these clock cycles, the output ID of the output selector 122 is driven by the zero and one from the first error output ERR, then subsequently by the zero and one from the second error output ERR, delayed by two clock cycles. During the other four clock cycles, the output ID is driven by the repeated BIT output of the auto-zeroing comparator 120. Under normal circumstances, the output ID sequence for one identification is “0, 1, 0, 1, BIT, BIT, BIT, BIT”. If the error detection circuit detects an error, the “0,1,0,1” output preamble will be different, indicating that the identification may not be trustworthy.
Load and error detection circuits
In the stimulus circuit 48, each ROW select line 60 is linked through a diode-connected bias MOSFET 128 to a switch 126, which may further link the line to either a positive rail or to a current source 124. Switch 126 is connected to current source 124 when the row is selected. The current from current source 124 flows through MOSFET 128, causing it to turn on and to produce a low analog voltage on ROW select line 60. If the row is not selected, switch 126 connects ROW select line 60 to the positive rail, turning off all the transistors in the unselected row. MOSFET 128 is suitable made similar to the MOSFETs in each cell 62, so that substantially similar currents to 124 will flow through array output AOH and AOL, and into the load circuit 114.
In the load circuit 114, the IH and IL currents terminate in matching load devices 136. The load devices include series and parallel combinations of P channel MOSFETs, also similar to the MOSFETs in each cell 62. A square array of MOSFETs connected with equal numbers of MOSFETs in series and in parallel will have substantially the same DC behavior as a single MOSFET. However, such an array will have a smaller statistical variation, so the four MOSFETs illustrated as a series-parallel composite in each half of 136 will behave like a single MOSFET, and the pair of composite MOSFETs will behave like a pair of single MOSFETs with improved matching.
P channel MOSFETs are used as load devices because they have substantially the same relationship between transconductance and current as the MOSFETs of the cell, resulting in the same nonlinearities. This means that a mismatch voltage inside a cell will appear substantially the same at the loads and between the array output lines AOH and AOL and will be independent of the current. The output voltage will therefore be relatively resistant to biasing variations, or common mode noise coupled into the system. The relative sizes of the signal steps, and the resulting identification sequence, will be more constant over time.
Load devices 136 act as source followers from the analog load bias voltage 130. The voltage biasing the load is generated from a current 134 across a diode-connected MOSFET 132. The current 134 is eight times the current 124. Thus the voltage on bias line 130 is lower than the voltage on ROW select line 60, and is low enough to ensure that the voltages on the array output lines AOH and AOL are always low enough to keep the MOSFETs in the selected cell 62 in saturation. Although there are many transistors connected in series, in no case is more than one voltage threshold plus a few saturation voltages necessary to bias the circuit for proper operation. As a result, with appropriate reductions in operating current and clocking frequency, the ICID circuit can be operated at very low voltages, barely exceeding the voltage threshold of a MOSFET. While other circuit topologies may be developed offering improved performance with large power supplies, this circuit topology will perform reasonably over a wide range of supplies. In addition, the voltages across the devices minimize such electrical stresses as hot carrier degradation of gate oxides, further protecting the stability of the identification cell array.
Two of the drains from load transistors 136 divert current into the error detection lines 116. The diverted current is connected to the drains of N channel MOSFET current mirrors 144, which mirror the current that current source 140 outputs through diode connected N channel MOSFET 142. If the current mirror MOSFETs 144 produce more current than the error detection lines 116 get from the load devices 136, the lines are pulled low. This causes buffers 146 to produce low logic levels on error outputs ERR. If the load device currents are higher than the current mirrors 144 produce, the error detection lines 116 are pulled high, incidentally modifying the voltages on array output lines AOH and AOL.
Current source 140 is controlled by TIMING signals to produce a sequence of comparison currents. For most of the identification cycle, this current is set at a high value, causing the error detection lines 116 and error outputs ERR to remain low. During one clock period out of the eight clock long identification period, the comparison current 140 is lowered to a value setting an upper threshold level for the array output line current. If AOH or AOL is pulled up too strongly, due to a defect, one of the error detection lines 116 will be pulled high, indicating the defect on one of the error outputs ERR. Otherwise, the error output will stay low during this period. During the subsequent clock period, the current 140 is lowered further to the lower threshold value for the array output line current. Under normal circumstances, this will cause both error detection lines 116 to be pulled high. However, an array defect may cause either AOH or AOL to pull up too weakly, and one or both of the error detection lines 116 will remain erroneously low. Thus, if the IH and IL currents are within an appropriate range, we will see a logic zero followed by a logic one on each of the error outputs ERR.
A defect in the array causing more than one row or column to be selected, or one of the identification transistors to be egregiously large, will thus cause two logic ones on one of the error outputs ERR. If no rows or columns are being selected, or there is an open in a MOSFET or an interconnection device, we will see two logic zeros. Defects may arise from decoding or logical errors in the address sequencer. Whatever the source of error, most of them may be detected and isolated by observing the error output lines ERR for the correct sequence of pulses. Error detection circuit 118 thus adds to the trustworthiness of the ICID circuit, though due to the small size of the ICID circuit the chances of its encountering any defect at all is quite small, perhaps 100 parts per million.
Auto-zeroing capacitor 120 measures the size of the differential voltage change between two successive values of VX produced by successively selected identification cells. Amplifier 174 amplifies and inverts VX to drive the front end of coupling capacitors 176. The output of capacitors 176 drives the differential line pair 178, the input to amplifier 182. During the autozero portion of the identification period, switches 180 are closed, connecting the output of the second amplifier stage 182 back to its inverted input. This results in forcing the differential line pair 178 to a small difference voltage, approximately the residual input offset of second amplifier 182, and independent of the voltage on amplifier 174. A voltage is impressed across the capacitors 176 equal to the array output voltage VX as amplified by the first amplifier 174. Switches 180 are then opened, and the voltage at nodes 178 remains small. Subsequently, a second identification cell is selected. This produces a new voltage VX on array output lines AOH and AOL, which is amplified by the first amplifier 174 to change the voltage at the input side of the capacitors 176. Because the capacitor outputs 178 have been disconnected by the switches, they are free to follow the change of voltage on their input side, causing the differential voltage on lines 178 to change from their precharged value to a new value proportional to the change in VX multiplied by the gain of the first amplifier stage 174. This change is further amplified by the gain of the second stage amplifier 182, to produce a greatly amplified voltage change on the strobed comparator inputs 184.
After the voltage step has settled on lines 184, the comparator 188 is stored with comparator timing strobe SAMP. This causes the comparator to resolve the positive or negative voltage change into a logic one or zero on comparator output line BIT. Additional switches and control signals may be added to the auto-zeroing comparator circuit to enhance its performance. In particular, large voltage glitches at the input may occur when switching from one identification cell to the next, and switched clamps may help the comparator settle after these large voltage glitches.
The stimulus circuit
Four bits of the latched address are decoded into one of 16 COL select lines 58. The other four bits of the latched address are decoded into one of 16 ROW select lines 60. The COL select lines 58 are asserted positive, while the ROW select lines 60 are asserted negative. For an interval around the address transition, all the COL select lines 58 are precharged low, and all the ROW select lines 60 are precharged high. These de-selects all the identification cells in the identification cell array 46. During the same precharge interval, the disconnected array output lines AOH and AOL are precharged high. When the row and column lines are asserted, one of the identification cells is selected, and the array output lines AOH and AOL change to values reflecting the difference voltage. The voltage change is measured by the auto-zeroing comparator in the measurement circuit, producing the comparator output BIT. The differential array output AOH and AOL will normally produce mid-range load currents as shown during the first segment 234 of the load current waveform. However, a defect may cause either no identification cells to be selected, as illustrated by the lower line of second segment 226, or two identification cells to be selected, as illustrated in the upper line of segment 236. This will cause the current through at least one side of the load cell 114 to be abnormally low or high. This current is compared in the load cell to the error comparison current 140, with the normal range of currents shown by the regions 238.
With the error comparison current as illustrated by waveform 140, we can expect normal cells to produce a zero error output until the last clock period of the selected cycle, when the comparison current 140 is reduced below the minimum expected current to produce a one pulse on the error outputs ERR. However, an excessive current will result in the error outputs ERR pulsing high for both comparisons, and an insufficient current will result in no pulse at all. These errors could all be logically combined into a single logical signal, but in this case, all four error signals are separately multiplexed into the ICID circuit output stream ID by the output selector 122. This is done by delaying the signal from one of the pair of error outputs ERR by two clock periods before multiplexing it into the output stream, while multiplexing the signal from the other line into the output stream directly. By examining the serial bit stream, the validity of the serial output stream can be determined. This is important when the identification portion of the output stream cannot be validated with a checksum or other validating data pattern.
ICID 38 may be adapted to provide an output ID that not only uniquely identifies an IC in which it is installed but also includes a “type code” indicating aspects of the IC that is has in common with other ICs sharing the same photomask, such as its type, source of manufacture, etc. Thus an output ID of ICID 38 would include one field having a value that is unique to the IC in which it is installed and another field having a value that is common to all similar ICs. The type code may be set by replacing each of several of the “random identification” cells 62 of array 46 of
The sequence in which the array cells are addressed influences the nature and value of the ID the ICID circuit 38 produces. Four kinds of IDs will be described, but many other kinds may be readily imagined and this invention is not limited to those described here. The simplest ID is the binary ID generated by counting linearly through all array addresses in sequence, and saving the result of the comparison as a binary bit. The address count proceeds as 0,1,2, . . . , N-1, N and wraps around to 0 again. The serial output bits ID from the measurement circuit directly form the 256 binary bit identity record.
This simple sequence may be modified slightly to better accommodate type identification cells. Sequencing from a logic one-type to logic zero-type identification cell will always produce a deterministic “0” bit out of the auto-zero comparator. Sequencing from a zero-type to a one-type identification will always produce a deterministic “1”. However, sequencing between two zero-type or two one-type cells will produce a non-deterministic “mismatch” transition, useful for individual part identification, but not for type identification. Therefore, arrays with rows of type identification cells may alternately be addressed with a sequence like: 0, M, 0, M+1, 0, M+2, . . . where the type identification cells are M, M+1, and so on. This means that the first part of the bit sequence forming the output ID will have a predictable string of bits representing the type identification.
The actual parametric values are not directly visible to a sorting process; however, all that is readily needed for a sort is the ability to compare values, and this comparison is performed by the auto-zeroing comparator 120. A conventional sorting algorithm, implemented as hardware on an IC, or as software running on an external tester or comparator, may be used to perform the sorting. The sequence of sorted addresses conveys more information than the simple binary ID. A binary ID for the simplified array illustrated can have 2 to 8th power or 256 possible values, while the sorted ID can have 8 factorial or 40320 possible values. Both ID records may be extracted from the very same ICID circuit, simply by using different control sequences and different algorithms.
The sorted value ID may be used in its entirety, but a shorter subset of “reliable” values may be constructed. When a sequence of these reliable values are presented to the ICID circuit, it will tend to produce a more repeatable series of transitions and comparator outputs. This sequence may be used to query the ICID circuit and receive a deterministic response.
Binary ID Analysis
Due to noise and drift, the output of a cell, which happens to nearly match the previously selected cell, may randomly resolve into either a one or a zero whenever the two cells are sequentially addressed. This will make some of the bits of an ID non-repeatable, and slightly different every time it is generated. However if the ID is sufficiently long, the remaining invariant bits will still serve to identify the IC that generated it since it would be unlikely that an ID produced by any other IC would have so many bits in common.
When a binary ID is extracted from an ICID circuit with subsequent drift, perhaps due to random noise, mobile ion contamination, or redistribution of the charges in the transistor channel, the ID may change over time. The bit extraction process is resistant to these changes. If a random drift of 25% (an additional uncorrelated Gaussian with 25% of the magnitude of the original Gaussian) is added to the random values used to produce the binary identity record, the result will be about 7.8% of the bits randomly changing value. The bit error rates are statistically independent for each bit. The average absolute norm, for a given array size and bit error rate, is N′P. For the example with 256 values, 25% drift and P=0.078, the average absolute norm will be about 20. For a trillion drifting samples, there will be less than one part with an absolute norm greater than 56.
The false positive and false negative rates will not be mathematically zero, but they will be immeasurably small when the array is sufficiently large, certainly better than fingerprint identification and other legally acceptable forms of identification. The ICID circuit may be practically applied to identify one part out of a database of one million parts. The IDs of one million parts are extracted, along with other identifying information such as testing date, lot number, wafer number, wafer position, process parameters, test speed, and other useful information. This information may be stored in a computer database. Assume at some later time, with the one million parts in use, that one of these parts needs to be identified. An ID is extracted from the identification circuit on the chip. Because of drift, this ID will probably not be identical to the original ID in the data base. However, if it is compared to every ID in the data base, the result will be 999,999 absolute norms that are probably greater than 90, and almost certainly greater than 73. There will also be a single absolute norm that is probably less than 44, and almost certainly less than 53, if the drift is less than 25%. We can set a threshold in our test of 64, and easily distinguish the correct ID in the data base. In fact, the drift can be as high as 37% before there is more than one chance in a trillion of exceeding the threshold, and erroneously concluding the selected component is not in the database because of excessive drift. Modern semiconductor processes drift far less than this.
If the part is not in the database with an absolute norm of less than 64, the component has either been badly mistreated, it has not been logged, the identification circuit has failed, or the component is a counterfeit produced by some other manufacturer. All of these possibilities can be distinguished with further investigation, and all are of interest to a semiconductor manufacturer. A 256-cell array was employed in the example ICID illustrated herein. However with a lesser maximum drift, or when fewer chips are to be identified, or when the identification may be less reliable, than fewer array cells may be used. For example, with a 10% maximum drift, and a 1 in 1 million allowable error rate, as few as 64 cells will provide adequate identification. For a 1 in 1 quadrillion error rate (10-15) and a drift of 240%, 4096 cells may be needed. For any finite drift, an acceptable error rate may be achieved with a sufficient number of cells.
Cell Array Alternatives
The discussion hereinabove assumed that array cells were implemented in an N-Well CMOS process of 0.5 micron or smaller linewidth, but cell transistors may be either N channel or P channel MOSFETs, and longer channel processes may be used in some circumstances. If the CMOS process is an N-Well process, P channel MOSFETs should be chosen so that the entire array can be placed in an N-Well isolated from the substrate and the electronic noise in it. A P-Well process would use N channel MOSFETs for the same reason. While the preferred embodiment of the invention employs MOSFET pairs with common source and gate connections, with the output signals derived from the drains, it is also possible to connect transistors with common gate and drain, thereby deriving a voltage difference signal from the source. While the array cells of the preferred embodiment make use of the voltage threshold mismatch of a pair of MOSFETs, mismatches of length, width, oxide thickness, or any other parametric variables may be used in alternative embodiments of the invention. Pairs of devices are used for the preferred embodiment, but single devices may be used in applications where the ambient conditions permit it. Resistor mismatches or VBE mismatches could be used with a purely bipolar process. Identification from random parametric variation can be applied to any other semiconductor process producing devices with random but repeatable parametric mismatches.
Although the device array was illustrated as a square, equally useful ICID circuits may be constructed as a rectangular array of any shape or size. To improve statistical usefulness, it is helpful to include the set of “dummy cells” at the edges of the array which are not addressed when an ID is generated. However the such dummy cells along the array edges may be omitted. Row select transistors may be added to isolate the array output lines AOH and AOL from unselected drains. With proper addressing, this allows merging of drain output lines between rows of cells, allowing for a more compact array.
The ICID circuit may be addressed, for example, by a counter, rather than a shift register, generating addresses internally rather than from an input line. The external clock may also be replaced with a free-running oscillator. The enable input may be replaced with a power-on reset cell. Such an alternative design would have a single output line, and be suitable for applications where interconnect count is more important than power or synchronization.
When an ID is computed, it may be stored on the chip itself as a sequence of values in an on-chip Random Access Memory (RAM) which may be non-nonvolatile. The RAM may be part of a microprocessor on-board cache, and available to software executed by that microprocessor. This arrangement allows fast access to the ID during use, and may be required to generate repeatable IDs in very noisy environments. It does, however, require additional chip area for a RAM.
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|U.S. Classification||324/750.15, 702/73, 700/115, 324/762.03, 324/762.09|
|International Classification||G06F19/00, G01R31/02, H01L23/544, G06F17/50|
|Cooperative Classification||H01L2924/3011, H01L2924/0002, H01L2223/5444, H01L2223/54433, H04L9/0866, H01L2223/54473, H01L23/544|
|European Classification||H04L9/08H4, H01L23/544|
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