|Publication number||USRE40339 E1|
|Application number||US 11/004,791|
|Publication date||May 27, 2008|
|Filing date||Dec 3, 2004|
|Priority date||Jan 20, 1998|
|Publication number||004791, 11004791, US RE40339 E1, US RE40339E1, US-E1-RE40339, USRE40339 E1, USRE40339E1|
|Inventors||Ronald J. Bolam, Subhash B. Kulkami, Dominic J. Schepis|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (21), Referenced by (4), Classifications (12), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Reissue Application of U.S. Pat. No. 6,492,684, issued Dec. 10, 2002, which is a continuation-in-part of U.S. patent application Ser. No. 09/859,146, filed on May 16, 2001 (pending) now U.S. Pat. No. 6,563,173, which is a continuation of U.S. patent application Ser. No. 09/148,918, filed on Sep. 4, 1998 (allowed), U.S. Pat. No. 6,281,095 which is a divisional of U.S. patent application Ser. No. 09/009,445; filed on Jan. 20, 1998, now U.S. Pat. No. 6,133,610.
The present invention relates generally to a silicon-on-insulator (SOI) chip and, more particularly, to an SOI chip having an isolation barrier to prevent the diffusion of impurities into active regions of the chip.
As the scale of integration increases in the manufacture of integrated circuits, devices become smaller and more sensitive to impurities. During the packaging of a semiconductor chip, impurities from the packaging environment can enter the chip, diffuse into silicon junctions, and compromise the reliability and performance of the integrated circuit. Semiconductor manufacturers have known this for some time and invest in manufacturing equipment to minimize the introduction of impurities during integrated circuit manufacturing.
Typical impurities include mobile ions such as Na, Fe, or other diffusing species. One conventional process of providing a barrier preventing these impurities from entering the chip includes coating the chip with a passivation layer around the outside and top of the chip. Typical materials used as a passivation layer include silicon nitride or metal levels formed during the chip wiring. Such a barrier works for conventional semiconductor chips which do not have a buried oxide layer (or BOX).
A BOX is endemic to the silicon-on-insulator (SOI) chip structure and represents a path for the migration of impurities if exposed. Indeed, this path is laid open to just such exposure when the individual chips are diced from the wafer before packaging. A conventional SOI chip 1, illustrated in
A gate 18 is deposited above silicon layer 14. A passivation layer 26 is deposited above silicon layer 14 and around gate 18. A barrier material 20 is deposited above passivation layer 26. Barrier material 20 is typically a dielectric material such as phosphosilicate glass (PSG), BPSG, nitride, or other similar material. Gate metal contact 30 is deposited above gate 18, as illustrated in
Unlike other types of semiconductor chips, an SOI chip 1 is not adequately protected from impurities by merely coating the outside and top of the SOI chip 1 with a passivation layer 26. This is because SOI chips 1 are manufactured by dicing, which causes SOI chips 1 to have diced edges, such that edges 42 of oxide layer 12 buried within the SOI chip 1 are exposed to the outside environment. The exposed edges 42 act as an entryway for impurities notwithstanding coating of the outside and top of the SOI chip 1 with a passivation layer 26. Once inside oxide layer 12, the impurities may diffuse into various regions of the SOI chip 1.
The SOI chip 1 is particularly sensitive to contamination from these impurities after chip dicing but before packaging. Contamination at this particular juncture of the manufacturing process can result in loss of manufacturing yield. Accordingly, there is a need for an additional barrier to impurities diffusing into the SOI chip 1 from along the edges 42 of oxide layer 12.
A process of passivating SOI chips 1 to prevent contamination by mobile ions before chip packaging has been described by K. Motonori in Japanese Published Patent Document No. 6-177242. Montonori describes a device in which an ion diffusion barrier is deposited alongside a silicon-buried oxide layer to protect this layer from mobile ion contamination. This device, although it protects the exposed edges of the chip and may fulfill the desired function, has several significant drawbacks.
The process of exposing the edges of SOI chips before dicing involves several potentially defect-producing steps which may reduce the overall manufacturing yield of the integrated circuits. First, the process described by Motonori, for passivating the edges of the SOI integrated circuits, requires two photolithography steps and two etching steps involving reactive ion etching. The etching steps consist of etching through many insulator films, a total thickness of well over 10,000 angstroms, and exposing the completed integrated circuit to charging damage due to the long duration of the reactive ion etching plasma steps.
Second, Motonori describes a process by which the diffusion barrier is removed from the chip dicing area just before dicing, which requires a second photolithography step and alignment to the regions to be removed. The addition of this step increases the size of the dicing region, leaving less area on each wafer for integrated circuits. This leads to larger “footprint” or die sizes. Larger die sizes often decrease the amount of chips available per wafer, causing manufacturing cost to increase.
Finally, the conformality, or ability to deposit a uniform film of the ion diffusion barrier on a vertical surface over 10,000 angstroms deep, is critical to the effectiveness of the barrier. Any break in the film would risk contamination of the final chip by mobile ions.
To overcome the shortcomings of conventional SOI chips, a new SOI chip is provided. An object of the present invention is to provide a mobile ion barrier between the edges of the exposed SOI integrated circuit and the integrated circuits within the exposed SOI integrated circuit. A related object is to provide an integrated diffusion barrier within the SOI chip itself, having a shallow depth, minimal lateral dimensions, and a planar surface. It is another object of the invention to provide an isolation groove structure as the integrated diffusion barrier and to fill the isolation groove with films that are part of the existing semiconductor fabrication sequence. It is a further object of the invention to provide an integrated diffusion barrier, within the integrated circuit area, which does not require additional area in the dicing channels for either a barrier layer or any photolithography steps which would increase the size of the integrated circuit area.
To also overcome the shortcomings of conventional processes of manufacturing SOI chips, a new process of manufacture is provided. An object of the present invention is to reduce processing steps. A related object is to manufacture an integrated diffusion barrier using a single photolithography mask and a single reactive ion step. Another object is to subject the integrated circuit to less charging due to reduced exposure to reactive ion etching.
To achieve these and other objects, and in view of its purposes, the present invention provides an SOI chip including a substrate, a buried oxide layer deposited above the substrate, and a silicon layer deposited above the oxide layer. A gate oxide layer is deposited above the silicon layer. A gate is deposited above the gate oxide layer. A gate metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The SOI chip has an isolation barrier extending through the silicon layer and the buried oxide layer to prevent diffusion of impurities into the buried oxide layer. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact, to define an active chip area inside the isolation barrier.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.
The invention is best understood from the following detailed description when read in connection with the accompanying drawing. It is emphasized that, according to common practice, the various features of the drawing are not to scale. On the contrary, the dimensions of the various features are arbitrarily expanded or reduced for clarity. Included in the drawing are the following Figures:
Referring now to the drawing, wherein like reference numbers refer to like elements throughout, an SOI chip 100 and process of making the SOI chip according to the present invention are illustrated in
A gate oxide layer 17 is deposited above silicon layer 14. A gate 18 is deposited above gate oxide layer 17. A silicide layer 44 is formed over gate 18 and silicon layer 14 (which is the diffusion region). A passivation layer 26 is deposited over SOI chip 100 both as a passivation layer and as an etch stop. Passivation layer 26 covers trenches 34, silicon layer 14, and gate 18 (i.e., the entire top surface of SOI chip 100). Passivation layer 26 typically includes silicon nitride, polysilicon, oxide, nitride, or other suitable passivating materials.
As illustrated in
According to the present invention, after the etching process, resist 28 is removed or stripped. The result of the etching process is shown in FIG. 2B: a physical isolation barrier in the form of a ring or groove 16 which extends completely through passivation layer 26, silicon layer 14 and trench 34, and oxide layer 12. According to the embodiment illustrated in
As illustrated in
As illustrated in
Next, metal contact lithography is performed. A gate metal contact 30 is deposited above gate 18. Gate metal contact 30 extends from the top of SOI chip 100 through barrier material 20, silicide layer 44, and passivation layer 26 to form an electrical contact with gate 18. Metal contacts 40 are deposited above selected areas of silicon layer 14 and extend from the top of SOI chip 100 through barrier material 20 and passivation layer 26 to form electrical contacts with selected areas of silicon layer 14. Finally, the device may be chem-mechanically polished (CMP).
As further illustrated in
The first embodiment of the process of manufacturing SOI chip 100 having a groove 16 as an integrated diffusion barrier includes the following steps (illustrated in FIG. 2D). First, a device having substrate 10, buried oxide layer 12, silicon layer 14 with at least one trench 34, gate 18, and silicide layer 44 is provided (Step 500). Passivation layer 26 is deposited (Step 510), resist is applied (Step 520), groove 16 is etched (Step 530), resist 28 is removed (Step 540), barrier material 20 is deposited (Step 550), barrier material 20 is polished (Step 560), metal contact lithography is performed (Step 570), and a final CMP is done (Step 580). A single photolithography mask or resist 28 is deposited (Step 520). A single reactive ion etching step is applied (Step 530). Finally, the resist 28 is stripped (Step 540).
The first embodiment of the process of manufacturing SOI chip 100 having a groove 16 as an integrated diffusion barrier requires only three extra steps over a conventional SOI chip 1 which is not protected from impurities because of exposed diced edges 42. Moreover, the first embodiment of manufacturing SOI chip 100 requires only three extra steps whereas other processes, such as described in Japanese Patent Reference 6-177242, require at least six extra steps.
The SOI chip 101 illustrated in
The process by which SOI chip 101 is manufactured is similar to the process illustrated in
Thus, the second embodiment of the process of manufacturing SOI chip 101 having a groove 16 as an integrated diffusion barrier includes the following steps. First, a device having a substrate 10, buried oxide layer 12, silicon layer 14 with at least one trench 34, gate 18, and silicide layer 44 is provided (Step 500). Resist is applied (Step 520), groove 16 is etched (Step 530), and resist 28 is removed (Step 540). Then passivation layer 26 is deposited (Step 510). Subsequently, barrier material 20 is deposited (Step 550), barrier material 20 is polished (Step 560), metal contact lithography is performed (Step 570), and a final CMP is done (Step 580).
A third embodiment of the SOI chip 102 of the present invention is illustrated in FIG. 4. SOI chip 102 shown in
Fill material 50 is then deposited in groove 16, filling the remaining void in groove 16. Because the portion of passivation layer 24 along the bottom of groove 16 has been removed, fill material 50 makes a direct contact with substrate 10. Fill material 50 within groove 16, as illustrated in
After the additional steps of an anisotropic etch applied to groove 16 and the deposit of fill material 50 in groove 16, both performed after passivation layers 24 and 26 are deposited (passivation layers 24 and 26 may be, but are not necessarily, the same composition), the remaining steps of the process used to manufacture SOI chip 101 of
Thus, the third embodiment of the process of manufacturing SOI chip 102 having a groove 16 as an integrated diffusion barrier includes the following steps. First, a device having substrate 10, buried oxide layer 12, silicon layer 14 with at least one trench 34, gate 18, and silicide layer 44 is provided (Step 500). Resist is applied (Step 520), groove 16 is etched (Step 530), and resist 28 is removed (Step 540). Then passivation layer 26 is deposited (Step 510). An anisotropic etch is applied to groove 16 and fill material 50 is deposited in groove 16. Then fill material 50 is etched to form a planar structure. Subsequently, barrier material 20 is deposited (Step 550), barrier material 20 is polished (Step 560), metal contact lithography is performed (Step 570), and a final CMP is done (Step 580).
Described above are suitable process steps used to manufacture the SOI chip of the present invention. A large number of variations are possible in those process steps.
As illustrated in
Further variations in the process steps used to manufacture the SOI chip of the present invention are possible. These variations may involve, for example, the location in the process where groove 16 is etched. The location is not critical. Groove 16 may be etched early in the manufacturing process so that formation of groove 16 can be included as part of the formation of trench 34; the etching step may be added later in the process just before metallization. Each approach may have specific advantages depending on process integration demands.
As illustrated in
As illustrated in
Unlike the devices of Montonori, the SOI chips 100, 101, 102, 300, and 300′ of the present invention each have a relatively narrow groove. Typically, grooves 16, 316, and 316′ are on the order of one or two microns wide. Moreover, the groove (or isolation barrier) of the present invention is integrated with structure of the SOI chip itself, rather than on its edge, and provides a continuous boundary to the diffusion of impurities from outside the SOI chip. In addition, the SOI chip according to the present invention does not require any additional processing steps before dicing the chip.
The SOI chip and manufacturing process according to the present invention have additional advantages over prior art devices and techniques such as those described by Motonori. First, manufacturing of SOI chip 100 (for example) only requires one photolithography mask for processing the diffusion barrier; Motonori requires two photolithography masks. The use of a second photolithography mask exposes the chip to possible further defects and damage from the reactive ion etching plasma charging.
Second, SOI chip 100 has a continuous diffusion barrier along all sides and the top of the SOI chip; Motonori only provides a non-continuous diffusion barrier. Third, minimal chip area is occupied by the isolation barrier (specifically, the groove) in SOI chip 100; the depth of the groove will generally not exceed 6-7,000 angstroms. In contrast, the device of Montonori has a much wider and deeper area formed through the metal insulators, the silicon layer, and the buried oxide layer. The area described is well over 10,000 angstroms deep and exposes the finished metallized chip to possible etching damage by charging.
Furthermore, because the groove formed in SOI chip 100 is relatively narrow, SOI chips 100 can be spaced closer together during manufacturing so that more chips can be cut from a single wafer. The device of Motonori requires larger dicing regions to allow the diffusion barrier to be removed. This requires, in turn, that the SOI chips of Montonori be spaced further apart when they are cut, creating alignment tolerance problems. Fourth, because (a) fewer steps are required to manufacture SOI chip 100, and (b) less chip area is occupied, the cost of manufacturing the SOI chip according to the present invention is relatively inexpensive compared to the cost required to manufacture according to Motonori. Fifth, the final structure of the present SOI chip is planarized while the SOI chip by Motonori is not planarized. Sixth, the barrier material used in SOI chip 100 is a “gettering material,” which conforms easily to the shape of the groove. Motonori teaches the use of a sputtered film which does not conform as easily and is more likely to experience breaks. Seventh, the barrier material used in SOI chip 100 is deposited as part of an existing step in the manufacturing process of the chip. In Motonori, an additional film material is required to form the diffusion barrier. Finally, SOI chip 100 of the present invention has a planar final structure; the device of Montonori has a non-planar final structure.
A fourth embodiment of the SOI chip 103 of the present invention is illustrated in FIG. 9A. SOI chip 103 shown in
A fifth embodiment of the SOI chip 104 of the present invention is illustrated in FIG. 9B. SOI chip 104 is similar to SOI chip 103 shown in
Although illustrated and described herein with reference to certain specific embodiments, the present invention is nevertheless not intended to be limited to the details shown. Rather, various modifications may be made in the details within the scope and range of equivalents of the claims and without departing from the spirit of the invention. The isolation barrier of the present invention is applicable, for example, to technologies such as bipolar, bi-complementary metal-oxide-semiconductor (bicmos), dynamic random access memory (DRAM), and the like on SOI substrates.
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|U.S. Classification||257/349, 257/376, 257/350, 257/354, 257/374, 257/353, 257/352, 257/375, 257/347, 257/355, 257/501|
|Apr 22, 2010||FPAY||Fee payment|
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|Jun 10, 2014||FPAY||Fee payment|
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|Sep 3, 2015||AS||Assignment|
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