|Publication number||USRE40411 E1|
|Application number||US 10/857,340|
|Publication date||Jul 1, 2008|
|Filing date||Jun 1, 2004|
|Priority date||Feb 18, 1992|
|Publication number||10857340, 857340, US RE40411 E1, US RE40411E1, US-E1-RE40411, USRE40411 E1, USRE40411E1|
|Inventors||J. Carl Cooper|
|Original Assignee||Cooper J Carl|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (67), Non-Patent Citations (102), Referenced by (2), Classifications (9), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation-in-part of application Ser. No. 08/493,661, filed Jun. 22, 1995, now abandoned which is continuation in part of U.S. patent application Ser. No. 08/165,688 filed Dec. 13, 1993 now U.S. Pat. No. 5,486,869, which is a continuation of application Ser. No. 07/837,323, filed Feb. 18, 1992, now abandoned.
The present invention relates to signal processing systems and, in particularly particular, to video signal processing. A major objective of the present invention is a synchronizing signal processing apparatus and a method that precisely recovers synchronizing signals of a video signal.
Much of modern technology depends on signal processing. A common application of signal processing is for the video type signals. Usually, a video type signal includes an information signal component and picture or data synchronizing information comprised component. The synchronizing information is transmitted for scanning in a receiver in exact synchronism with a camera-tube scanning. The synchronization signal must first be recovered from the video signal.
More particularly, TV (Television) video signals, the an example of the video signal, are processed to obtain desired picture quality. A TV transmitting station modulates video and audio signal component and a synchronizing component which is used to identify the location of segments of the information component. The synchronizing component typically is comprised of a predetermined sequence of characteristics which are repeated periodically. Most commonly, NTSC television signals are comprised of an active video portion with two level sync pulses periodically positioned between the active video portions. In particular, in order to precisely reproduce pictures, synchronizing information is added in the video signal so that the receivers can synchronously perform scanning operation as the TV transmitting station does.
Numerical and graphical criteria which describe essential aspects of a TV system, are employed in the design and operation of equipment to assure that the various parts of the system will operate in cooperative fashion at maximum performance. TV systems have a special need, compared with other communication systems, for definitive standards because television transmitters and receivers must operate in a precise lock-and-key relationship. In particular, the scanning of the image in the camera must be matched by the scanning in every associated receiver within a timing precision of approximately one-tenth of a millionth of a second, and with relative positions of picture details correct to a few hundredths of an inch as viewed on the CRT or other display.
To assure that any television receiver can receive programs from any transmitter within range, it is customary to set up a single set of standards with a group of neighboring countries. The TV transmitting stations of different countries and areas transmit video signals with different formats. For example, U.S.A., Canada and Japan et al. use NTSC (National Television System Committee) system. France, the former Soviet Union countries et. al. use SECAM. Moreover, HDTV (High Definition TV) creates a new system with images of high resolution as well as a new video signal format and new transmission methods. For all of these examples, the synchronizing signals added in their video signals are different, but share similar characteristics.
Picture synchronizing information is obtained from the video signal by means of sync separation circuits. In addition, these circuits must separate this information from noise and interference during the reception of weak signals, particularly if impulse noise is present. To reproduce these different video signals of respective systems, different video signal processing devices are needed to provide required synchronizing signals.
Conventional video signal devices for processing the synchronizing information of the video signals can not be used for different standard video signals for providing reliable synchronizing signals, without affecting the reproduction of the video signals or causing high cost of video signal processing. What is needed is a synchronizing signal processing apparatus and method that precisely recovers synchronizing signals of the video signal and can be applied for processing different video signals.
The present invention provides for detecting a synchronizing portion of a video type signal, and for signals which transmit digital or constrained multilevel analog data providing reference signals fro slicing the data portion of the signal in response to the synchronizing component. As used herein for the purposes of describing and claiming the present invention the video type signal will be described as the type having periodic known patterns which comprise the sync portion with the sync portions being interspersed with video like or other information carrying signals such as data with this information carrying portion being referred to as video and data both terms of which are intended to include any information carrying signal. A group consisting of at least a sync portion and a information carrying portion will be referred to as a data group.
This process of detecting the synchronizing portion of the video type signal involves identifying or detecting the arrangement of the known pattern of the sync or other identifier. For purposes of describing and claiming the present invention detecting shall be understood to encompass, inspecting, identifying, recognizing, distinguishing and any other means or method of ascertaining the presence, occurrence or location of the feature of interest. The present invention provides for such detecting by detecting a first transition of a known direction and amplitude, and inspecting the first transition to see if it occurs in a proper relation to a second known occurrence. The detection of the proper relation of the known occurrences is preferred to be made by delaying a signal marking the first occurrence for an amount equal to the expected arrival of the second occurrence and determining if the two are approximately coincident, thereby indicating the proper relationship. Further checking may be made by including a third or more occurrences to ensure proper relationships, for example by checking to determine if the first or second occurrence takes place an expected time before or after an event.
In order to establish references for data slicing the amplitude and D.C. level of components of the sync portion are used to establish the D.C. level and gain of the reference signals. Because the gain and D.C. levels may change throughout the signal, it becomes necessary to remove these changes from the signal and/or adjust the references accordingly. This capability is provided by establishing or measuring some known parameter at each end of a segment of data or video in order to be able to estimate these changes, or eliminate these changes, during the segment.
In accordance with the present invention, a synchronizing signal processing apparatus includes means for sampling synchronizing type signals and components of a video type signal. The present invention further includes slicing a video type signal in response to the sampled synchronizing signals. The synchronizing signal processing apparatus includes a sampling means that samples synchronizing signal components and provides at least a reference signal. The synchronizing signal processing apparatus also includes a comparing means that slices the video signal in response to at least a reference signal responsive to different levels of components of the synchronizing pulses. Thus, the synchronizing signal processing apparatus generates logic level outputs. The video signal with which the present invention is used may be of a standard type having synchronizing pulses including horizontal synchronizing pulses or may be of the proposed HDTV type or of other type having a sync portion made up of a known sequence of components and a information carrying portion carried therewith.
The video signal may be sliced, before it is sampled, to eliminate noise. The sliced video signal corresponds to the synchronizing pulses. In response to the sliced video signal, the peaks of the synchronizing pulses of the video signal are precisely sampled. Two sampled signals represent the positive and negative peaks of the synchronizing pulses. The two sampled signals further are divided into three reference signals to compare with the video signal. After this comparison, the logic outputs are combined to recover synchronizing pulses that are reliable, precise and without noise.
A combining means couples to the comparing means so that the outputs from the comparing means are combined depending on the type of the video signal. The combining means generates a plurality of synchronizing signals.
To provide a vertical synchronizing signal, the present invention uses an integrating type filtering means that filters one of synchronizing signals output from the combining to provide a vertical synchronizing signal. The filter means shows a good frequency response characteristic for the vertical synchronizing signal.
The synchronizing signal processing method in accordance with the present invention comprises steps of slicing a video signal, sampling the video signal in response to respective leading and trailing edges of the sliced signal, converting the sampled signal into at least a reference signal, comparing the reference signal with the video signals and combining the compared outputs to recover synchronizing pulses.
An advantage of the synchronizing signal processing apparatus and method is that the present invention incorporates several standard functions with superior performance. The synchronizing signal processing apparatus in accordance with the present invention is capable of operating with standard two level synchronizing pulses, for example, NTSC, PAL and SECAM type synchronizing pulses, and three level synchronizing pulses, for example HDTV synchronizing pulses. The present invention may also applied for other video type signals with synchronizing pulses.
Furthermore, the present invention provides good bandwidth properties and time constant in the video amplifier section. The combination of both proper bandwidth and time constant gives considerably noise immunity against high frequency noise, yet maintains sufficient operation speed for high performance. Therefore, no additional compensation or filtering components are needed.
The synchronizing signal processing apparatus in accordance with the present invention may be easily adjusted for either two level or three level synchronizing pulses. The recovered synchronizing levels for video signals are characterized by high precision and reliability.
The logic level outputs of the comprising means are combined, the combination depending on whether the synchronizing pulses are two levels or three levels. In accordance with the present invention, the synchronizing signal processing apparatus may generate a TTL (Transistor-Transistor level) version of the synchronizing pulses.
The synchronizing signal processing apparatus in accordance with the present invention may be used with different video devices, which simplifies the design and manufacture of video devices, and significantly decreases the cost to make these video devices.
Another advantage of the synchronizing signal processing apparatus of the present invention is that it is suitable to be implemented by integrated circuits. Alternatively, the video signal processing can be implemented by software, such as in signal processing applications. These and other features and advantages of the present invention are apparent from the description below with reference to the following drawings.
FIG. 1 is a block diagram of a synchronizing signal processing apparatus in accordance with the present invention.
FIG. 2 illustrates a detailed circuit diagram of a sync pulse processing section of the synchronizing signal processing apparatus of FIG. 1.
FIG. 3 illustrates a detailed circuit diagram including a pulse width adjust and a reference sync generating section of the synchronizing signal processing apparatus of FIG. 1.
FIG. 4 illustrates a detailed circuit diagram of a sync restoring section of the synchronizing signal processing apparatus of FIG. 1.
FIG. 5 shows waveform diagrams of several nodes of the synchronizing signal processing apparatus.
FIG. 6 shows a frequency response characteristic of a filter device of the synchronizing processing apparatus of FIG. 1.
FIG. 7 is a flow chart of a synchronizing signal processing method in accordance with the present invention.
FIGS. 8-11 are four sheets of a detailed schematic of the preferred embodiment in accordance with the present invention.
FIG. 12 shows a prior art HDTV video format waveform which has a two level sync pulse and an 8 level digital data format.
FIG. 13 shows a prior art HDTV video format which utilizes a two level sync pulse and a 16 level digital data format.
FIG. 14 shows an expanded diagram of a typical one of the syncs of FIG. 12 or 13.
FIG. 15 shows a typical expanded diagram of a typical pair of single data segments separated by a single sync pulse.
FIG. 16 shows a diagram of the preferred embodiment of the present invention
FIG. 17 shows a diagram of the preferred embodiment of the present invention for providing thresholds and slicing data.
FIG. 18 shows a digital embodiment of the present invention.
FIG. 19 shows a diagram of the preferred embodiment of the present invention for providing thresholds in response to data.
FIG. 20 shows a diagram of the preferred embodiment of the present invention for detecting edges of known magnitude.
FIG. 21 is a flow chart of a synchronizing signal identifying method in accordance with the present invention.
A synchronizing signal processing apparatus 100 in accordance with the present invention includes an input amplified amplifier 102, a video standard detector 103, a sync pulse processing section 104, a pulse width adjust 106, an offset device 108, a DC (Direct Current) restoration device 110, a reference sync generating section 112 and a sync restoring section 114.
Video signal 116 101 is applied to differential input amplifier 102 where video signal 101 is amplified to improve the ratio of signal/common mode noise. The video signal amplified by input amplifier 102 is fed to sync pulse processing section 104 which includes a sync tip clamp 116, a sync slicer 118 and a sync tip peak detector 120.
The video signal is first clamped by sync tip clamp 116 to generate a clamped signal which has a known DC level of the synchronizing pulses. The clamped signal is then transferred to sync slicer 118 where the clamped signal is sliced, thereby generating a signal that has the same time period as that of the synchronizing pulses but at standard levels as compared to that of the synchronizing pulses, in this example TTL levels. To effectively eliminate interference and noise, the sync slicer 118 slices the synchronizing pulses at a known level which is preferred to be about half of the nominal expected amplitude of the synchronizing pulses. Due to a known level which is approximately half the expected level, the operation of sync slicer 118 may be considered a coarse slicing operation which provides coarse sliced pulses. The sliced signal is coupled to sync tip peak detector 120, in which peaks of synchronizing pulses of the video signal from DC restoration device 110 are sampled in response to the sliced signal.
The clamped signal is also delivered to pulse width adjust 106. This clamped signal activates pulse width adjust 106 to generate a pulse trigger signal coupling to DC restoration device 110. The pulse trigger signal determines the pulse width of the synchronizing pulses. A switch SWp is provided so that this switch is open, which indicates that the video signal is a NTSC TV signal. On the other hand, when the video signal output from the input amplifier 102 is a HDTV signal, the video standard detector 103 will turn switch SWp on. The video standard detector 103 also control switches SWT, SWU, and SWL. The switches may be operated automatically in response to a video standard detector 103 which detects the type of signal 101. Therefore, the synchronizing signal processing apparatus 100 in accordance with the present invention may process different video signals.
Offset device 108 provides a DC reference for DC restoration 110. The amplified video signal from the input amplifier 102 is also coupled to DC restoration 110. In response to the reference from offset device 108, DC restoration 110 clamps the amplified video signal to eliminate DC shift and residual common mode noise.
Other types of DC restoration circuits may be used as is well known in the art. It is desired to have the video signal V0 1 V01 and V0 2 V02 restored to a known value. However, it should be noted that the DC restoration device 110 may be eliminated by directly AC coupling the video signal output from the input amplifier 102 to the reference sync generating section 112 and sync pulse processing section 104. The operation of sync tip peak detector 120 will track the variations in the AC coupled video signal output from the input amplifier 102 and allow the comparator 122 to function properly. However, the use of a DC restoration device is preferred. The DC restoration device 110 produces two output signals V0 1 V01 and V0 2 V02. The clamped video signal V0 2 V02 is delivered to sync tip peak detector 120. In response to the sliced signal from the sync slicer 118, sync tip peak detector 120 samples the positive and negative peaks of synchronizing pulses of the clamped video signal so as to provide two peak sample pulse signals. For purpose purposes of the present example, video is described with respect to positive white with the negative level of sync being that which is farthest from peak white video and the positive level of sync being that which is closest to the peak white value of the video. For two level sync, such as NTSC, the positive peak will correspond to video blanking level. The two peak sample pulse signals define each of the synchronizing pulse pulses. Divider 124 receives them and converts them into three pulse reference signals. The amplitudes of the pulse reference signals represent percentage levels of sync of V0 2 V01 during the respective ones of the peak sample pulses as represented by VH and VI.
Reference sync generating section 112 also includes a comparator 122. The clamped video signal from D.C. restoration 110 and three pulse reference signals are coupled to comparator 122. By comparison, comparator 122 outputs four level signals during each synchronizing pulse of the video signal. Due to the use of references which are responsive to the actual level of the sync pulse, the comparator 122 may be considered a precision comparator, which outputs precision sliced pulses. The four level signals represent different amplitudes of each synchronizing pulse as determined by the video sync being greater than none, one, two or three of the pulse reference signals.
A sync restoring section 114, which includes combination logic 126 and vertical sync filter 128, is arranged to receive the output signals from the comparator 122 of reference sync generating section 112. The combination logic 126 is used to combine the four output signals from comparator 122 to recover reliable synchronizing signals. Switches SWU and SWL are arranged to control the switching between the HDTV video signal and conventional TV video signals, for example NTSC TV video signal.
The opening of switches SWU and SWL indicates that the synchronizing signal processing apparatus operates with conventional video signal. Otherwise, the closing of the switches SWU and SWL shows out that the apparatus operates with HDTV video signal. The position of another switch SWT is also related to the video signal being processed by the apparatus in according accordance with the present invention. Therefore, the apparatus of the present invention is suitable to different video signals by changing status of these switches, which may respond automatically to the video standard detector 103 as well.
The vertical sync filter 128 is coupled to the combination logic 126. A composite synchronizing signal CS from the combination logic 126 is coupled to it. The vertical sync filter 128 filters the composite synchronizing signal CS to provide a vertical synchronizing signal VS. The vertical sync filter 128 may respond to a composite synchronizing signal from other sections as well, for example from 112.
The sync pulse processing section 104 of synchronizing signal processing apparatus 100 is detailed with reference to FIG. 2. Input amplifier 102 includes two operational amplifiers OP1 and OP2. OP1 is used with OP2 to eliminate common mode noise of the video signal 101. The positive input of OP1 receives one of input video signal 101 which is the common one (shield) of the input signals. Resistor R1, 100KΩ, is an input resistor for stabilizing the DC component of the input video signal.
A resistor R2 (75Ω) and a switch SWI are connected between the input lines for terminating video signal 101. When the input is taken from other than the end of a coaxial cable run, SWI is open. While the video signal 101 is applied to input amplifier 102 at the end of a coaxial cable run. SWI is closed so that the input resistance of input amplifier 102 is matching the output resistance of the circuitry providing video signal 101, thereby reducing signal loss. Capacitor C1 (0.1 μf) provides a high frequency bypass from the common to ground. R2 is the terminating resistor (75Ω). OP1 and resistors R3 (1.10KΩ) and R4 (499Ω) constitute a negative feedback amplifier its gain being two approximately. The output of OP1 is coupled to the negative input of OP2 via resistor R5 (2.21KΩ).
The positive input of OP2 receives the signal directly from the input signal 102 101. OP2 and resistors R6, R7 and potentiometer R8 provide another feedback amplifier. Resistor R6 and R7 have the same resistance, 1.0KΩ. The potentiometer R8 has a resistance from 0-10KΩ. Thus, the gain of the input amplifier 102 may be adjusted between 1.5-3. Due to the delay caused by OP1, the common mode component of input signal 102 101 arrives at the positive and negative inputs of OP2 at slightly different moment. Under low frequency, the delay due to OP1 is tolerable. However, high frequency components of the input video signal, after delay by OP1, would severely affect correlation of the common mode signal, causing distortion of the video signal. Therefore, a filter having capacitor C1 of 0.01 μf is utilized to filter the interference and noise to ground.
The output of OP2 is coupled to the sync tip clamp 116 of the sync pulse processing section 104. The sync tip clamp 116 includes buffers OP3 and OP4, and an amplifier OP5. Resistor R9 (5.6KΩ) is used with capacitor C2 to by-pass undesired frequency components. The buffered video signal is coupled to the positive input of another buffer OP4 via an isolating capacitor C3, 0.1 μf.
A negative 12V is applied to the isolating capacitor C3 and the positive input of OP4, via a current limit resistor R10, 147KΩ. R10 effectively constitutes a constant current source. The isolating capacitor C3 is used to isolate the direct current components of the video signal.
The negative 12V applied to the capacitor C3 draws node N1 toward a negative level, pulling the video signal output from OP3 to a negative level. The negative video signal, after buffering by buffer OP4, is coupled to the negative input of the amplifier OPS OP5 via a resistor R11 with resistance of 10KΩ. OPS OP5 and a resistor R12 with resistance of 39KΩ established establishes a negative feedback amplifier. The positive input of OPS OP5 is grounded. The resistance of the resistor R12 determines the maximum gain of amplifier OP5, which my may be lowered if diodes D3, D4 conduct.
Normally, the output of OP5 is negative. Two diodes D1 and D2 are provided to isolate the output of OP5 from the node N1. When the output of OPS OP5 is above a level required to turn the D1 and D2 on, for example 1.2 V, the capacitor C3 is charged positive. The resistor R10 charges C3 negative, but is countered by the current through D1 and D2 when the video signal is below the ground of the positive input of OP5, thus causing N1 to move in a positive direction, which forces the output signal of OPS OP5 to be returned to a negative value. The other two diodes D3 and D4 are arranged between the negative input and output of OP5. When the video signal at the negative input of OP5 is more positive by a level high enough to turn D3 and D4 on, the negative input and output of OP5 are shorted so that OP5 functions as a buffer and prevents large negative excursions at the output, thereby causing OP5 to recover to normal status very quickly, when returning positive.
Sync slicer 118 includes a comparator CP6. The output of OP5 is directed to the positive input of CP6. The output of OP4 is directed to the negative input of CP6. By comparison of the signals at its input. CP6 slices the synchronizing pulses of the video signal at about half of the amplitude. By using both the outputs of OP4 and OP5, the comparison is less sensitive to noise and sync amplitude variations than if a fixed level were used. For the NTSC and HDTV video signals, the output of CP6 has a delay of about 0.1 μS. Comparator CP6 slices the amplitude of the synchronizing pulses without appreciable change of pulse width.
The sliced pulses output from CP6 are directed to the sync tip peak detector 120. The sync tip peak detector 120 includes sample switches SW1 and SW2, and two sample holders consisting of resistors R15 and R16 with the same resistance of 1KΩ, and capacitors C6 and C7 with the same capacitance of 0.1 μf. Resistor R15, capacitor C6 and switch SW1 constitute a sample and hold circuit. Resistor R16 and capacitor C7 and SW2 constitute another sample and hold circuit. Two buffers OP7 and OP8 are respectively coupled to the two sample and hold circuits to output the sampled signals.
The sliced pulsed from CP6 are first inverted by an inverter I1. Thus, the rising edge of the inverted pulses coincide with the trailing edge of the output pulses of CP6. Each of the inverted pulses is then differentiated at its rising edges, by means of a differential capacitor C4 of 0.001 μf and a differential resistor R3 of 330Ω. The switch SW1 is in the receipt of the signal V0 2 V02 output from the DC restoration device 110. Usually, switch SW1 is tied to ground via resistor R13. Only upon the arrival of the rising edges of the inverted pulses, switch SW1 is activated to couple to the hold circuit having R15 and C6. Therefore, corresponding to each falling edge of the sliced pulses output from CP6. R15 and C6 sample the positive peaks of the pulses. Note that the sliced sync from CP6 is opposite in polarity to the sync of V0 2 V02. The sampled positive peak is held for the buffer OP7 to output. The width and amplitude of the differential pulse for sampling the video signal is set by C4 and R13.
The sampling time may also be controlled by the addition of a oneshot in the path from the differential node N2 or N3 and the control input of the respective switch. It is preferred that the sampling start after all ringing which might be present on the preceding edge has had time to die out, or to an acceptable level, and end before any preshoot which may be present on the next edge, for the same reasons. It is also preferred that the sampling time be substantially equal to an integral number of cycles of any coherent or repetitive interference which may be present on the waveform in order that it will average or integrate to zero (if the interference is bipolar and uniformly distributed) or a steady value (if the interference is unipolar or nonuniformly distributed) in the hold circuit.
The amplitude of the pulse applied to the switch control input (or to the oneshot trigger input) is critical. It is desired to select the values of the differential network in relation to the expected amplitude and/or risetime of sync edges and to the switch control or oneshot input threshold to ensure that edges having less than the nominal value of sync edges (40 IRE units for NTSC) amplitude do not cause false sampling. Such low amplitude edges will sometimes occur in response to noise impulses which are so fast that the comparator CP6 is unable to make a full scale transition at its output during the pulse duration. The component values given in FIG. 9 provide such protection.
For example, for the ICs suggested the threshold is set internally at ½ VCC. The differentiation network should be designed so that a 35 IRE edge will result in a ½ VCC pulse which will cross the control threshold. This will guarantee that a proper 40 IRE edge will always generate a sample and a low 30 IRE noise edge will not generate a sample.
Similarly, after inversion twice by inverter I2 and I3, the output of CP6 is differentiated by a differential capacitor C5 of 0.001 μf and a differential resistor R14 of 330Ω. The delay of the inverter I1-3 along with the delay of sync tip clamp 116 ensures that the sample pulses are applied to SW1 and SW2 well after any ringing or other distortion on the sync or blanking level has died out. If desired, delay elements other than the inherent delay of the circuit elements may be introduced to further ensure proper sampling of the video. Thus a differential pulse is coupled to switch SW2. The differential pulses produced by C5 and R14 cause the switch SW2 to close so that a resistor R16 of 1KΩ and a capacitor C7 of 0.1 μf hold the negative peaks of the synchronizing pulses. The two signals which operate sample switch switches SW1 and SW2 can be described as reference taking signals, since they take the instant samples which are in turn held by the hold capacitors to generate the voltage reference signals used by the divider 124 to provide references for comparator 122.
As a result, each of the pair of differential pulses produced by C4, R13, C5 and R14 defines the pulse position of respective synchronizing pulses. The relationship of the output pulses of CP6 and the differential pulses is shown in FIG. 5. Furthermore, buffers OP7 and OP8 deliver the peak sample signals to divider 124 for further processing.
The video signal amplified by the input amplifier 102 is also coupled to the DC restoration device 110, referring to FIG. 3. The DC restoration device 110 includes a voltage comparator CP9, a photosensitive element having a LED (light-emitting diode) DU Du and a photoresistor R59, as amplifier OP10 and a buffer OP11. A positive 5V DC voltage is tied to a resistor R17 of 1.0KΩ, the left part of the photoresistor R59 and the top tap of R59 is connected to ground. Thus, the voltage applied to the positive input of CP9 depends on the resistance of the left part of R59. On the other hand, the positive 5V is tied to a series connection of potentiometer R18 a resistor R19 and to ground. Thus, the reference voltage at the negative input of CP9 is defined by the position of the wiper of potentiometer R18. Therefore, adjusting the position of the wiper of potentiometer R18 may change the input voltage at the negative input of CP9.
At the output of CP9, a positive 5V is applied to the LED Du through a resistor R20 of 200Ω. The positive 5V provides an offset current to LED Du. The light intensity of the LED Du is in proportion to the current flowing through it. The resistance of photoresistor R59 is inversely proportional to the light intensity. Therefore, the higher the output of CP9, the larger the current through the LED Du, the lower the resistance of the photoresistor R59. The lower resistance of R59 makes the voltage applied to the positive input of CP9 go down, thereby causing the output of CP9 to decrease. CP9 thus causes R59 to maintain the voltage at the positive and negative inputs of CP9 to be equal.
The output of the input amplifier 102 is coupled to the positive input of the amplifier OP10 of DC restoration device 110, via a resistor R2 R21 of 330Ω. The output of OP10 is tied to the negative input via a feedback resistor R22, 1.0KΩ and the right part of the photoresistor R59 ties the negative input of OP10 to ground. Because the output of CP9 may change the resistance of R59, the gain of OP10 is also controlled by the output of CP9. Therefore, changing the position of the wiper of potentiometer R18 changes the gain of OP10. It will be understood from the present teachings that the same functions may be performed with other circuit elements, for example multipliers.
The output of OP10 is applied to the positive input of amplifier OP11. Along with a resistor R23 of 1.0KΩ, the operational amplifier OP11 buffers the output of OP10. The video signal from buffer OP11 is transferred to the sync tip peak detector 120 where the video signal is sampled in response to the pulses from the sync slicer 118, as shown in FIG. 2. The video signal output amplified by OP10 is also sent out by an output resistor R24, 71.5Ω for other purposes.
An offset device 108 is arranged to provide a DC offset required by the operational amplified amplifier OP13 of the DC restoration device 110. The offset device 108 includes a resistor network having a resistor R57 (100KΩ), a resistor R55 R56 (100KΩ) and a potentiometer R55. A positive 12V is coupled to resistor R57 and a negative 12V is coupled to resistor R56. A voltage determined by the position of the wiper of potentiometer R55 charges a capacitor C13 of 0.1 μf via a resistor R58 of 100KΩ. The level on the capacitor C13 is applied to the positive input of a buffer OP12.
The offset voltage is delivered to an integrator circuit established by a operational amplifier OP13 and a capacitor C8 (0.1 μf) bridging between the negative input and output of OP13. The positive input of OP13 receives the offset voltage. The offset voltage is also coupled to a switch SW3. The common close status of SW3 couples the offset voltage to the negative input of OP13 via a resistor R25 of 10KΩ. A capacitor C9 of 0.001 μf is tied between ground and SW3 for filtering undesired frequency components and switching transients.
In accordance with the present invention, the pulse width adjust 106 is provided for . The pulse width adjust 106 includes two multivibrators 301 and 302. The output from the sync slicer 118 is coupled to the /A Ā input of 301, as shown in FIG. 3. A positive 5V is tied to the clear input Clr and the B input of 301. Responding to each falling edge of the sliced signal from sync slicer 118, the multivibrator 301 produces a low level pulse at the Q
The output from sync slicer 118 is also coupled to the B input of multivibrator 302 via a delay circuit. This delay circuit includes two RC filters. A capacitor C14 (51 pf) and a resistor R28 (10KΩ) form a RC filter and a capacitor C12 (56 pf) and a resistor R60 (2.5KΩ) provide another one. Two inverters I4 and I5 are arranged between the two RC filters. An inverters I6 is positioned between the B input of 302 and RC filter having C12 and R60. A positive 5V is applied to R28 via a resistor R27 (1KΩ) for providing a DC bias. This delay circuit delays the sliced signal from sync signal 118 about 0.75 μs to 0.9 μs.
The pulses at the /Q
Therefore, the pulse width of Q output of 302 is between 2.0 μs and 2.5 μs for the NTSC video signal. This pulse occurs during blanking and burst portion of the NTSC video signal. On the other hand, the pulse width of the Q output of 302, for the HDTV video signal, is from 0.5 μs to 0.7 μs. The pulse of Q output of 302 coincides with the blanking portion without exceeding it. The waveform at the Q output of 302 is shown in FIG. 5.
The output pulses at the Q output of 302 activate the SW3 so that the output from OP11 is coupled to the negative input of OP13 via the RC filter having the resistor R25 and the capacitor C9. During the high level of the pulses from 302, the capacitor C8 of the integrator OP13 is charged up and down by the video signal from the buffer OP11 depending on whether it is above or below the reference on the plus input of OP13, drawing the input voltage at the positive input of OP10 up or down. As a result, the output of OP10 is drawn up or down. After the Q output of 302 recovers to low level, the switch SW3 is released so that the negative input of the operational amplifier OP13 is coupled to the output of OP12 of the offset device 108. Thus, the output of the operational amplifier OP13 does not change.
The divider 124 of the reference sync generating section 112 includes four resistors R31, R32, R33 and R34. The resistors R31-R34 have the same resistance of 10KΩ. Therefore, the output potential of the sync tip peak detector 120 is equally divided so that three reference potentials are provided. The first reference potential between the resistors R33 and R34 equals half of the output potential from the sync tip peak detector 120. The second reference potential between the resistors R31 and R33 equals three-fourth of the output level from the sync tip peak detector 120. The third reference potential between the resistors R32 and R34 equals one-fourth of the output level from the sync tip peak detector 120. However, different reference potentials may also be obtained by changing the resistance of resistors R31-R34. Different combination of potentials on the positive input of CP14-CP16 can be easily realized.
In accordance with the present invention, the comparator 122 of reference sync generating section 112 includes three comparators CP14, CP15 and CP16. The first reference potential between the resistors R33 and R34 is applied to the positive input of comparator CP14. The second reference potential between the resistors R31 and R33 is applied to the positive input of the comparator CP15. The third reference potential is then applied to the positive input of the comparator CP16. The video signal output V0 1 V01 from the amplifier OP10 of the DC restoration device 110 is coupled to respective negative inputs of three comparators CP14-CP16 via resistors R35, R36 and R37.
As for conventional TV video signals, for example, the NTSC video signal, CP14 compares the first reference potential and the video signal VO1 so as to sense the middle levels of the horizontal and vertical synchronizing pulses. The comparator CP15 then senses the video signal VO1 in response to the second reference potential and the rest of the video signal VO1 is regarded as noise. Because the switch SW1 of sync tip peak detector 120 closes during the blanking-burst period to sample the video signal, the second reference potential is set to a level lower than the blanking level. The switch SW2 of sync tip peak detector 120 closes during the negative synchronizing tip to sample the video signal, the third reference potential is thus set to a level higher than the negative tip. Two complementary output VP3 and VC3 from CP16 are delivered to the combination logic 126.
As a second example, when the apparatus 100 in accordance with the present invention is used for processing the HDTV video signal, the second reference potential represents a value between the blanking and positive peak synchronizing tip for the synchronizing pulses. The rest of the video signal VO1 is considered as noise. The first reference potential is set at the middle of the negative and positive synchronizing tip during synchronizing pulses, meaning at the blanking level. The purpose of this comparator CP14 is to sense transition from the negative synchronizing tip to the positive synchronizing tip. The rest of the video signal VO1 is considered as noise. The reference potential and the output VP3 of CP16 is the same as under the NTSC video signal. Therefore, outputs of comparator 122 are logic levels corresponding to the negative sync for these video signals.
The logic level outputs VP1, VP2, VP3 and VC3 from the comparator 122 are directed to the combination logic 126 of the sync restoring section 114, as shown in FIG. 4. The output VP1 of the comparator CP14 is directed to an input of an AND gate A1. The signal VC3 output from the comparator CP16 is inverted by an inverter I7, and is filtered by a RC filer having a resistor R53 (200Ω) and a capacitor C17 (0.001 μf). Before it is applied to another input of the AND gate A1, the filter signal VC3 is inverted again by an inverter I8. In order to preserve the combination logic generated sync information at the half way crossing, the output VC3 from the comparator CP16 is delayed by the inverter I7 and I8 circuit for 85 ns-200 ns. Thus, the two input pulses are added at the inputs of the AND gate A1 so that the output of A1 is a positive pulse.
Along with the output from the AND gate A1, the output VP2 from the comparator CP15 is directed to an input of an OR gate O1. The positive pulse from A1 and the VP2 activate the OR gate O1, thereby producing a pulse which has a rising edge defined by the positive pulse from A1 and a falling edge defined by VP2. The output of OR gate O1 is directed to another OR gate O2.
The output VC3 is also used to trigger a multivibrator 401 so that a high level is set at the /Q
The ANDed output from A2 is applied to another input of OR gate O2 so that the output from OR gate O1 is ORed with the ANDed output from A2. Particularly, under processing the NTSC video signal, the ORed output of OR gate O1 is completely determined by the ANDed output pulse from A2. The reason is that the negative ANDed output from A2 is narrower than the negative ORed output from O1. The output of O2 is a composite synchronizing output CS.
In order to extract horizontal synchronizing pulses from the out output CS from the OR gate O2, a circuitry including multivibrators 402 and 403, and OR gates O3 and O4 is designed. This circuitry eliminates every second half horizontal pulse from the vertical interval. The signal VC3 output from the comparator CP16 is directed to the multivibrator 402, where VC3 triggers the B input of 402 to set a low level at its /Q
The Q output of 403, along the /Q
A multivibrator 404 is used to generate a horizontal square waveform output HQ. The output HS of the OR gate O4 is coupled to the B input of 404 via the switch SWT. When the apparatus 100 of the present invention operates under the HDTV video signal, the rising edges of output HS triggers 404 at the B input to set a high level output at its Q output. Meanwhile, the switch SWL is closed so that the positive 5V is applied to 404 via shunted resistors R42 and R43 and a capacitor C21. Accordingly, the duration of the high level depends on a capacitor C21 and the resistance of shunted resistors R42 and R43. If the capacitance of C21 is set as 0.001 μf and R42 and R43 are respectively set as 51KΩ, the duration is then 15 μs.
If the apparatus 100 of the present invention operates with NTSC video signal, the output HS is reversed by an inverter I9 so that the B input of 404 is triggered by the falling edges of the synchronizing pulse, setting a high level at its Q output. At the same time, the switch SWL is open so that the positive 5V voltage is applied to 404 via only a resistor R42. Assuming R42 has the resistance of 51KΩ and C21 has the capacitance of 0.001 μf, the duration of the high level of the Q output of 404 is 30 μs.
The output CS of OR gate 02 is also directed to a vertical synchronizing filter circuitry including operational amplifiers OP17 and OP18. A resistor R44 of 37.4KΩ and a capacitor C22 of 0.001 μf bridge across the output and negative input of OP17 to form a first stage integrator type low pass filter. The positive input of OP17 is tied to ground. The composite synchronizing output CS is coupled to the negative input of OP17 via a resistor R52 of 39KΩ. This configuration acts as a current source and leaky integrator such that the integrator is charged by the vertical broad pulses. The output from OP17 is coupled to the negative input of OP18 via a 10KΩ resistor R50. The positive input of OP18 is tied to ground. A resistor R45 (10KΩ) and a capacitor C15 (0.001 μf) are shunted across the negative input and the output of OP18, thereby providing a second stage integrator type low pass filter. Of course, a more traditional low pass filter circuit may be implemented by the addition of source resistors as shown in FIG. 11.
This vertical filter circuitry employs a design which is an integrator and current source type, offsetting conventional optimal design. This design provides a frequency response characteristic without matching standard filter design curves which are commonly known. However, it is this design that provides a frequency response characteristic good for vertical synchronizing separation of the NTSC or HDTV video signal. This frequency response of the filter circuitry is shown in FIG. 6.
Alternatively, other vertical separation circuits which utilize the duty cycle of the vertical sync pulse may be utilized as well.
The filter signal is applied to a positive input of a comparator CP19 via a 38KΩ resistor R51. A resistor R46 of 3.3KΩ is bridged between the positive input and output of CP19 to provide positive feedback hysteresis for CP19. A positive 5V voltage is tied to ground via resistors R47 and R48. R47 has resistance of 20KΩ and R48 has resistance of 10KΩ. A capacitor C16 of 0.1 μf is shunted across resistor R48, thereby providing a stable reference voltage to the negative input of CP19. Furthermore, a positive 5V voltage is applied to the output of CP19 via a resistor R49 (1KΩ). Filter circuitry provides a vertical synchronizing output VS via CP19 and inverted by an inverter I10.
To obtain a field synchronizing output, the vertical synchronizing output from CP19 is directed to a flip-flop 405. The clear input CLR
A processing method 700 for synchronizing pulses of the video signals is shown in FIG. 7. At step 701, the video signal is sliced to produce synchronizing pulses. The video signal is then sampled in response to the sliced sync to precisely sense the sync tip peaks pulses, at step 702, thereby providing two peak signal values representing the positive and negative peak values of each synchronizing pulse.
The peak signal values are further converted, at step 703, into three reference signals which respectively represent the different levels relative to each synchronizing pulse. In particular, the three reference levels respectively represent the middle, upper and lower middle levels of the synchronizing pulse. Comparison of the three reference levels and the video signal is conducted at step 704. As a result of this comparison, the logic pulse outputs are obtained. Step 705 is for restoring synchronizing pulses of the video signal by combining the logic outputs.
FIGS. 8-11 show a more detailed schematic circuit of a preferred embodiment in accordance with the present invention. All of the components in FIGS. 8-11 correspond directly to those presented in FIGS. 2-4. The differences between FIGS. 2-4 and 8-11 include that all of components in FIGS. 8-11 are marked with commercial identification and are therefore more available in market. Therefore, detailed product part numbers and nominal values of components are marked on the components of FIGS. 8-11. The operation principle and interconnection of the components of the circuitry shown in FIGS. 8-11 are corresponding to FIG. 1 and FIGS. 2-4 and one skilled in the art will be able to understand FIGS. 8-11 from the forgoing description and explanation. Thus, the description of FIGS. 8-11 is omitted here.
FIG. 12 shows a prior art HDTV video format waveform which utilizes a two level sync pulse and an 8 level digital data format. The Data+FEC (Forward Error Correction) 1203 is carried in analog form constrained to a number of discrete levels which levels are allowed to change periodically, most usually in response to a clock signal. It may be noted that the sync pulse in this signal is not the same type of sync pulse as formed in typical NTSC or similar prior art systems. The sync pulses in NTSC type systems are used to facilitate horizontal and vertical scanning of the electron beam of the TV display whereas the sync pulses of the present system of FIG. 12 are used to facilitate the location and subsequent recovery of the data segment. It will be appreciated from the present disclosure that the invention described herein may be used to advantage with any type of synchronizing, locating or identifying pulse or arrangement of a known pattern or sequence.
The use of the analog constrained level type of data transmission for video signals was described for example in U.S. Pat. No. 4,665,431 issued May 12, 1987. In the '431 patent such a system is seen in FIGS. 2 and 3 where the constrained data carries audio or other related signals in the video waveform.
The waveform of FIG. 12 is typical of the HDTV terrestrial broadcast transmission system which is proposed for the United States. Note that the 8 possible levels which the data may take on are shown simultaneously, as if the figure were an oscilloscope display repetitively triggered to the sync pulse. In normal operation where only a single one of a data segment is displayed the data will be seen to trace a single pattern among the various levels, such as shown in FIGS. 2 and 3 of the prior art '431 patent.
FIG. 13 shows a prior art HDTV video format which utilizes a two level sync pulse and a 16 level digital data format. This waveform is typical of the terrestrial HDTV cable TV transmission system which is proposed for the United States. It will be understood that the combination of analog constrained level data and two level sync pulses as shown in FIGS. 12 and 13 is provided herein as examples of prior art video type signals with which the present invention may be used to facilitate improved synchronizing pulse separation, however the invention is not intended to be limited to only these two examples and may be utilized to advantage with any other system which utilizes two or more level synchronizing or identifying type pulses with analog or digital information carried therewith.
For the video signals of both FIG. 12 and 13, it is preferred to establish a known D.C. reference level for the signal and to provide data reference levels with which the particular level that a data bit occupies may be determined. Alternatively, it is possible to measure the D.C. level of the video type signal and adjust the reference levels accordingly. As the video type signal level changes the data reference levels will change in response thereto in order to maintain the proper relationship. It will be recognized that establishing a proper reference level is preferred to be accomplished by use of known components of the synchronizing portion of the signal, such as a sync tip or a sync blanking level. The use of the sync components is preferred, since those are the best known and most easily identified levels of the signal by virtue of the defined arrangement and known pattern of the waveform the pattern having a repetitive nature. It will also be recognized that for the signal of FIGS. 12 and 13 establishing proper reference levels is best performed by using both the sync tip and sync blanking level. The function of determining which particular level that a data bit occupies will be referred to herein as slicing and may be determined by establishing data reference levels to which the data waveform or signal may be compared by multiple comparators, although the term slicing as used herein will be used to encompass all circuits, steps and functions for performing this task of determining which data reference levels a data bit falls between or matches.
As an example, with respect to FIG. 12 it is seen that there are 8 possible data levels identified on the left scale as occurring at levels labeled −7, −5, −3, −1, +1, +3, +5, and +7. In order to identify which of these eight levels the video signal occupies at a particular time it can be seen that establishing data reference levels between the video levels, and comparing the video to those reference levels is desired. For the present example it can be seen that the reference levels may be established at −6, −4, −2, 0, +2, +4, and +6. In addition it may be desired to detect that video has exceeded the allowable range by adding thresholds of −8 and +8. The capability of such detection will allow data to be flagged as suspect for example in the event of noise impulses. The establishment of such reference levels is often complicated by the fact that the areas of information between sync pulses may very well change in amplitude and D.C. offset level during the segment.
In order to overcome this problem it is necessary to first establish or measure some known parameter at each end of the segment in order to be able to estimate the change during the segment. This process first requires identifying the segment by identifying or detecting the arrangement or sequence of the known occurrences or patterns of the sync or other identifier. The present invention provides for such identification by locating or detecting a first transition of a known direction and amplitude, and inspecting the first transition to see if it occurs in a proper relation to a second known occurrence. The second known occurrence may be another transition of a known direction and level, or the occurrence of a known level for a known time. The detection of the proper relation of the known occurrences is preferred to be made by delaying a signal marking the first occurrence for an amount equal to the expected arrival of the second occurrence and determining if the two are approximately coincident, thereby indicating the proper relationship. Further inspection may be made by including a third or more occurrences in the inspection to ensure proper relationships.
Once the locations of segments of video, data or other information are known by the above determination of the locations of arrangements of known patterns of identifiers, the levels of known parts of the patterns may be utilized to establish the levels of one or more references at the start and end of the segments. Once the start and end levels are known the references may be adjusted throughout the segment in order to facilitate recovery of the information for example by data slicing.
FIG. 14 shows an expanded diagram of a typical one of the syncs of FIG. 12 or 13, showing data segment ending data 1401, leading sync blanking 1402, sync falling or leading edge 1406, sync tip 1403 with sync tip level 1408, sync rising or trailing edge 1407, sync trailing blanking 1404 and data segment beginning data 1405. Note in particular that the 50% level of the sync pulse is identified for each of the leading and trailing edge by 1406 and 1407 respectively. It may also be noted that the sync pulse is corrupted by the presence of residual carrier pilot and other interference shown as the broadening of the waveform. FIG. 15 shows a typical expanded diagram of a typical pair of single data segments separated by a single sync pulse. FIG. 15 shows the first data segment ending data 1501 which happens to occur at the lowest level, leading sync blanking 1502, sync falling or leading edge 1506, sync tip 1503 with leading sync tip level 1508 and average sync tip level 1509, sync rising or trailing edge 1507, sync trailing blanking 1504 and the second data segment beginning data 1505 which happens to occur at the highest level. Note in particular that the 50% level of the sync pulse is identified for each of the leading and trailing edge by 1506 and 1507 respectively, and that they are not the same level as shown in FIG. 14. It may also be noted that the sync pulse of FIG. 15 is also corrupted by the presence of residual carrier pilot and other interference shown as the broadening of the waveform. The presence of the residual carrier pilot is of particular concern since if not properly accounted for it can upset the measurement of sync blanking and tip. It is desired that any sample and hold which is utilized to sample the level of a sync component have a sample period which is an integral multiple of cycles of this carrier in order that the effect of the carrier will be integrated out by the hold circuit. Alternatively, filtering of the sync component may be utilized.
It may be noted that the waveform of FIG. 15 is corrupted in a relatively low frequency manner, which is demonstrated for purposes of example by the tilt in the sync tip and the associated different levels of 1502 and 1504, and also 1506 and 1507. It will also be recognized that the amplitude of the overall waveform may be affected such as to change the overall amplitude, or to compress or expand portions of the amplitude in a nonlinear fashion. All of these various distortions may be experiences simultaneously in a static or time varying fashion.
Tilt will be used herein to signify any type of distortion of the video signal whereby the position of sync components and/or data components are disturbed within a single sync period or from period to period. This distortion may be caused for example by capacitive coupling of the video waveforms with the resulting average level which changes due to the data in the different data segments being at different levels. Other causes of distortion may include interference from unwanted signals being introduced into the video signal, or reflections of the signal itself from terrestrial objects or imperfect transmission either over the air, in the cable system or in the video transmitting, receiving or processing circuitry.
In establishing the reference levels for subsequent slicing of the data, it will be necessary to either first remove the tilt from the waveform, or to generate reference levels having the same tilt as the waveform. It is preferred to remove the tilt by clamping the waveform to a known D.C. level and to generate the required reference values in response to the amplitude of the sync pulse. It is further preferred to adjust the amplitude of individual ones of the reference values in response to the data itself in order to optimally place said reference values between the data levels. In this fashion the reception of the transmitted data of the video signal may be optimized.
FIG. 16 shows a diagram of the preferred embodiment of the present invention having a video input 1601 for receiving the video type signal, a processing circuit 1602 for receiving and processing the video type signal. Circuit 1602 is preferred to include common mode rejection capability and filtering to remove unwanted interference signals which are of a fixed frequency nature. The output of 1602 is coupled to a falling edge detector 1614 to a rising edge detector 1615, and to a D.C. level adjustment circuit shown in this preferred embodiment as a resistor network 1604 and 1605. It will be recognized that the output of 1602, as well as any other of the signals at any other stage utilized in the invention, may be coupled in any fashion known to those of ordinary skill in the art, including capacitively coupled as shown by 1603.
The falling edge detector 1614 operates to detect when a falling edge is present in the signal, such as the edge 1506 of FIG. 15. The output of the falling edge detector may be considered a marking signal and the marking signal is delayed by an edge to edge delay 1616 where the delay is slightly shorter than the time period or number of clocks from the leading edge 1506 to the trailing edge 1507. The rising edge detector 1615 operates to detect when a rising edge is present in the signal, such as the edge 1506 of FIG. 15. It will be recognized that by the addition of a window level comparator to the coincidence detect 1617 that the presence and duration of a particular level of the sync signal may be detected. The detection of the duration of the sync tip 1503 is described above, and if the window detector is combined to verify that the level of sync tip is between two known levels then the level and duration of sync tip may be detected. Such detection is also possible for other levels such as the sync blanking level 1502 or 1504.
It will thus be appreciated that events of transitions of known direction and amount as well as events of levels of known amount and time may be detected as well as the relationships of the events, including the sequence and timing of such events may be detected and utilized to detect or verify the occurrence of sync or other types of timing signals in the video type signal.
The edge detectors are preferred to take into account the distance the edge falls or rises such as by differentiating the edge to generate a spike, and comparing the amplitude of the spike to a reference such that edges which occur due to data transitions from one level to another which are smaller than the distance from sync pulse blanking 1502 to sync tip 1508 may be discarded. Thus only edge transitions equal to or greater than the substantial amplitude of sync edges are detected. Such an edge detector is implemented in 120 of FIG. 2 as previously described and is also shown in FIG. 20.
As previously mentioned the delay 1616 delays the leading sync pulse by slightly less than the expected period of a legitimate sync pulse. The coincidence and period detector 1617 then checks to see if a leading pulse is followed at substantially the proper time or number of clocks by a trailing pulse. If so, the period detector then checks to see if this set of pulses occurred at the proper time or number of clocks after the preceding received set of pulses, which preceding set is delayed by period delay 1620. In other words, 1617 checks for proper sync pulse width and period. It will be recognized that the detection of periods and delays may be performed by the use of time delays or clock period delays as one skilled in the art will be able to choose to fit a particular implementation of the invention without departing from the scope of the invention. In particular, the delays may be implemented with clock counters in order that they track transmission rate variations of the video type signal.
It is preferred that 1617 utilize some amount of windowing in checking for proper sync pulse period and width in order to allow for small variations which may occur to legitimate syncs due to noise, time base errors, transmission imperfections and the like. This is the reason that delay 1616 is preferred to delay an amount slightly less than the width of a sync pulse and detect as proper pulses which arrive between that time and a time slightly more than that of a proper sync pulse. In particular it is preferred that both the pulse width and pulse period detectors operate to detect within a window of 95% to 105% of the expected value.
While the pulse period delay is shown as being separately connected to 1616 to represent that it presents the previously detected pulse from 1616 and presents it to 1617 after a delay, it will be recognized that it may also be connected to the output of 1617. The former case will allow quicker startup and acquisition and the latter will provide better noise immunity since any pulse out of 1617 will need to have been preceded by a pulse which occurred a pulse period earlier. It will be recognized however that if there is never a pulse out of 1617 upon initial startup, that there will never be a pulse from 1620, thus causing 1617 to latch up. This condition must be detected and prevented. For example, 1620 can be connected to 1616 if there is no previous output from 1617 stored in 1620, and then connected to 1617 as soon as there is an output from 1617. This function may be performed by a simple retriggerable oneshot which sets when a pulse is received from 1617 and times out if no pulse is received after 1½ pulse periods. As long as the oneshot is triggered, the output of 1617 is used to feed 1620. If the oneshot times out the output of 1616 feeds 1620.
The output of 1617 is coupled to a sample pulse generator and PLL 1618. The PLL is utilized to provide sample clocks and other clocking signals for subsequently sampling and clocking the data from the video signal, and for other clocking and timing functions as will be apparent to one of ordinary skill in the art. The sample pulse generator 1619 operates to provide properly times sample signals to the various sample and hold circuits to take samples of the video signal level at known times, for example to the sample switches 1608, 1609 and 1610 to take samples of the sync pulse blanking levels 1502 and 1504 with switch 1608, the high reference level which in the preferred embodiment is also 1502 and 1504 with switch 1609, and sync tip level 1509 with switch 1610. Other sample signals may be provided as well as will be discussed below.
Sample switch 1608 along with reference 1621, negative integrator 1607 and current providing resistor 1605 operate to D.C. restore the video signal the same as that of circuit 110. While not shown in FIG. 16, it will be recognized that any of the additional functions provided in FIG. 1 may also be included in the circuit of FIG. 16 as desired.
Sample switches 1609 and 1610 operate in conjunction with high and low level hold circuits 1611 and 1612, respectively, to sample and hold the levels of the sync pulse. In that the level of the sync pulse is directly related to the levels of the reference between each of the data levels of the data segment, the data reference level circuit 1613 receives the levels from 1611 and 1612 in order to establish reference levels for data slicing, as shown in FIG. 17.
In FIG. 17 the high level signal and low level signals from 1611 and 1612 are coupled to the reference level circuit at 1701 and 1702, respectively. These levels are translated to the upper reference level and lower reference level by amplifiers 1703 and 1704 having respective gains A1 and A2. This translation may be appreciated by inspecting FIG. 13 where it can be seen that the upper level needs to be between the upper two data levels corresponding to 14 on the left scale whereas the high level of the sync pulse corresponds to level 9. Correspondingly, the sync tip is at level −9 and the lower reference level should be at −14.
The upper and lower reference levels are then divided into the multiple data reference levels necessary for data slicing by resistors 1705a-n as shown by way of example in FIG. 17. As related to FIG. 13, these reference levels would correspond to 15 values of 14, 12, 10, 8, 6, 4, 2, 0, −2, −4, −6, −8, −10, −12 and −14 on the left scale which values define 16 possible data words. It will be understood that while the operation of FIG. 17 is shown by way of example with respect to voltages and resistances, it may be provided by equivalent use of currents and current ratios as will be known to one of ordinary skill in the art.
Each reference level from the resistor network 1705 is coupled to a comparator 1706 with the data & FEC (Forward Error Correction) portion of the video signal coupled to the other inputs of all of the comparators via 1708. The outputs of the 15 comparators are coupled to the combination logic 1707 which provides a combined digital output 1709 which represents a particular one of 16 words corresponding to the data level of the video at a particular time.
FIG. 18 shows a digital embodiment of the present invention. It will be recognized that many of the functions of the present invention may be performed in the digital domain rather than the analog domain which is described in respect to the preferred embodiment. The video is received at 1801, processed by 1802 and coupled from 1802 to a sync separator 1812 which provides a coarse separation of sync, and may be comprised of appropriate portions of FIG. 16. The sync separator provides separator sync pulses to the PLL 1811 which generates clocks for the A-D 1805 and Processor 1806. Alternatively, the clocks may be generated from the data as is well known in the art, in which case 1812 will be replaced with a clock or data extraction circuit.
The processor 1806 may be of a general purpose type, for example a microprocessor which is programmed to perform the steps or equivalent functions described herein via software control, or may be of a more dedicated type such as a DSP IC or dedicated IC designed specifically for the task. All of these embodiments will be known to be of use to one of ordinary skill in the art from the teachings herein.
The video data and FEC from 1802 is coupled to a processing circuit 1802 where it is prepared for coupling to an A-D convertor 1805 via a D.C. restoration circuit comprised of 1803 and 1804 and portions of a processor circuit 1806. The A-D 1805 receives the D.C. restored video and a sampling clock from PLL 1811. The video is digitized by 1805 with the digital video being coupled to the processor 1806.
The processor includes circuitry for sampling the sync blanking levels and sync tip, comparing the level to a reference and generating a correction for providing D.C. offset via connection 1809. Alternatively, the output of the comparison within 1806 may be coupled to an integrator 1810 as previously described.
Processor 1806 further provides establishing thresholds and slicing the data in response to the thresholds as previously described in order to provide the data out 1807 corresponding to 1709 of FIG. 17. The processor may also provide sync separation or data or clock separation as previously described with respect to 1812. Additionally, 1806 may be configured to provide additional functions such as those connected with the utilization of the data.
It will be appreciated that if an A-D convertor having sufficient range is employed, with suitable coupling such as capacitive coupling, that the D.C. restoration may be eliminated and thresholds for slicing may be computed on the fly within processor 1806 in order that the thresholds are dynamically adjusted as data is received in order to accommodate various tilt distortions. In particular, the level of the thresholds may be computed at both ends of a data block and adjusted throughout the data block to facilitate slicing.
As an example, if the data block is 100 clocks long, and a given threshold starts at value 50 units and ends at value 60 units the threshold value may be adjusted upward by 0.1 unit per clock thus causing the threshold to ramp up to track the tilt in the data. Another threshold might start at value 200 units and ends at value 180 units with this threshold value being adjusted downward by 0.2 unit per clock thus causing the threshold to ramp down to track the tilt in the data. This ramping threshold may then also be further finely adjusted in response to the data itself within and even continuously throughout the data block in addition to adjustment just at the ends. Accordingly, all thresholds may be simultaneously adjusted in different amounts and in different patterns. This approach provides not only for handling overall tilt of the data block, but will inherently compensate for any nonlinear distortion since the actual data may be utilized and the thresholds independently adjusted throughout the data block.
As a further example of the usefulness of 1806, the tilt of the data block may be corrected before or as part of the data slicing. As with the previous example where the given threshold starts at value 50 units and ends at value 60 units the data values may be adjusted downward by 0.1 unit per clock thus causing the tilt to be removed from the data in order that a fixed threshold may be used. Combinations of the two approaches may be utilized as well.
FIG. 19 shows an analog circuit for providing fine adjustment to the thresholds which are utilized by comparators 1706 of FIG. 17 in response to the data of the video type signal. The high level and low level signals are coupled to 1703 and 1704 to provide the top and bottom levels however each data value of the video from 1620 is sampled as soon as that data level is determined by 1707.
For example, a given data level N is detected as being between two thresholds N and N−1 by 1707, and the sample and hold corresponding to that level is caused to operate to sample and hold the actual data level. This operation continues for all data levels as the corresponding data is received, including for samples of data at levels N+1. It will be seen that by splitting the resistors 1705 corresponding to the thresholds above and below a particular data level, and coupling the actual sampled and held data level to the split resistors, that adjustment of the threshold values immediately above and below may be had. In this fashion, the threshold values may be adjusted to lie precisely in the middle of the data levels. This operation may of course be included in processor 1806 discussed above.
FIG. 20 shows a sync edge detection circuit which may be utilized for 1614 and 1615 of FIG. 16. The video signal having a sync pulse characteristic such as shown by 2002 is coupled to a differential 2001 which outputs pulses shown as 2003 which have an amplitude which is in proportion to the amplitude of the edge of 2002. The pulses are compared to two references which are preferred to be set at 85% of the amplitude of the pulse corresponding to a legitimate sync edge. The comparator, upon receiving a pulse equal to or in excess of the reference outputs a pulse the presence of which indicates a sync edge or possibly a data transition having a magnitude equal to or greater than that of the corresponding reference level. If desired, a second set of comparators may be included which have references of 115% of the amplitude of the pulse corresponding to a legitimate sync edge. The comparator, upon receiving a pulse equal to or in excess of this second reference outputs a pulse the presence of which indicates an edge having too large an amplitude, most likely resulting from a noise pulse or a data transition. This second set of comparators would then be used to inhibit or flag the output of the first set of comparators in order to prevent these invalid edges from being further processed.
One skilled in the art will recognize that the above described functions and components are somewhat more complex than represented by the present block diagrams, however from the disclosure and teachings herein, taken with the available applications literature available from the manufacturers of the suggested components, or from other components which may be substituted as will be known from the above disclosure, the construction of a practical and operable device will be well within the capability of one or ordinary skill in the art without resorting to further invention or undue experimentation.
FIG. 21 is a flow chart of a synchronizing signal identifying method in accordance with the present invention. The video type signal is first received, followed by the detection of a first event and the detection of a second event. The relationship between the first and second event is determined and if the relationship matches known parameters the occurrence of the sync is identified.
It will be understood that the previous descriptions and explanations are given by way of example, and that numerous changes in the combinations of elements and functions as well as changes in design of the above may be made without departing from the spirit and scope of the invention as hereinafter claimed. In particular, will be useful to combine the functions of the invention with other functions in a fashion so that such functions may be shared between devices or methods. These and other modification to and variations upon the embodiments described above are provided for by the present invention, the scope of which is limited only by the following claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
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|US6141057||Jun 2, 1999||Oct 31, 2000||Pixel Instruments Corp.||Apparatus and method for maintaining synchronization of multiple delayed signals of differing types|
|US6191407||Dec 2, 1998||Feb 20, 2001||J. Carl Cooper||Apparatus and method for spatially stabilizing projected or viewed images with a locating symbol position detection|
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|GB1143241A *||Title not available|
|GB2200011A *||Title not available|
|JPS5797274A *||Title not available|
|JPS58178669A *||Title not available|
|JPS58186270A *||Title not available|
|1||[Proposed] Claim Construction Order dated Sep. 2002.|
|2||[Proposed] Order Granting Gennum's Motions for Summary Judgement On The '250 Patent for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|3||[Proposed] Pretrial Order dated Mar. 12, 2004.|
|4||Addendum To Expert Reports of Richard Kupnicki For Defendant Gennum Corporation for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|5||Claim Construction Order dated Nov. 14, 2002.|
|6||Compiation re: Element c) of Claim 33 of U.S. Patent No. 5,754,250 (1 page).|
|7||Confirmation of Notice Pursuant to 35 U.S.C. § 282, dated Dec. 4, 2003.|
|8||Consent Decree And Order for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|9||Cooper Rebuttal to Kupnicki Exhibit A-2, undated.|
|10||Cooper Rebuttal to Kupnicki Exhibit B-2, undated.|
|11||Cooper Rebuttal to Kupnicki Exhibit B-4, undated.|
|12||Cooper Rebuttal to Kupnicki Exhibit B-6, undated.|
|13||Cooper Rebuttal to Kupnicki Exhibit C-2, undated.|
|14||Cooper Rebuttal to Kupnicki Exhibit D-2, undated.|
|15||Cooper Rebuttal to Kupnicki Exhibit E-2, undated.|
|16||Cooper Rebuttal to Kupnicki Exhibit F-2, undated.|
|17||Cooper Rebuttal to Kupnicki Exhibit G-2, undated.|
|18||Cooper, J. Cart, "Viewer Stress from Audio/Visual Sync Problems", SMPTE Journal, vol. 97, No. 2, pp. 140-142, Feb. 1988.|
|19||Data Package 9505-Color Black Sync Pulse Generator Module Assembly Number: 066582-00-1977.|
|20||Declaration of Richard Kupnicki (II) for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|21||Declaration of Richard Kupnicki for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|22||Declaration of Todd R. Miller In Support of Gennum's Opposition To TLC's Renewed Motion To Stay for Case No. CV-01-4204 RS in U.S. District Court for the Northern District of California, San Francisco Division, Sep. 12, 2006.|
|23||Defendant Gennum Corporation's Preliminary Invalidity Contentions for U.S. Patent No. 5,754,250 dated May 16, 2003.|
|24||Defendant Videotek Inc.'s Brief in Support of Its Proposed Claim Construction dated Sep. 27, 1002.|
|25||Defendant Videotek, Inc.'s Final Invalidity Contentions Under PLR 3-6(b) for U.S. Patent No. 5,754,250 dated Jan. 7, 2003.|
|26||Defendant Videotek's Preliminary Invalidity Contentions for U.S. Patent No. 5,754,250 dated May 9, 2002.|
|27||Digital Video System Input Sync Separator 5179 Circuit Schematic dated 1979.|
|28||Digital Video Systems Input Clock Generator 7051 Circuit Schematic dated 1981.|
|29||Document entitled "Validity '250 Patent" (32 pages).|
|30||Document entitled "Validity '869 Patent" (26 pages).|
|31||Elantec EL4581 Sync Separator, 50% Slice, S-H, filter Data Sheet dated 2003.|
|32||*||Elantec EL4581C Data Sheet May 1993 Rev A.|
|33||Elantec EL4581C/EL4583C Video Sync Separator Data Sheet, pp. 4-136 to 4-151, dated 1993.|
|34||Elantec EL4583 Sync Separator, 50% Slice, S-H, Filter, H<SUB>out </SUB>Data Sheet dated 2003.|
|35||*||Elantec EL4583C Nov. 1993 Rev. A.|
|36||Enlargement of Schematic for Sync/Color Bars Generator, Sheet 1 of 66 dated May 30, 1989.|
|37||Exhibit B-4-Claim Chart Comparing U.S. Patent No. 5,754,250 and Digital Video Systems Input Clock Generator 7051, undated.|
|38||Exhibit B-6-Claim Chart Comparing U.S. Patent No. 5,754,250 and U.S. Patent No. 4,097,896, undated.|
|39||Exhibit C-2-Claim Chart Comparing U.S. Patent No. 5,754,250 and U.S. Patent No. 4,097,896, undated.|
|40||Exhibit D-2-Claim Chart Comparing U.S. Patent Nos. 5,486,869//5,754,250 and U.S. Patent No. 4,233,629, undated.|
|41||Exhibit E-2-Claim Chart Comparing U.S. Patent Nos. 5,486,869/5,754,250 and Grass Valley Group SCB-200N Sync/Color Bar Generator, undated.|
|42||Exhibit F-2-Claim Chart Comparing U.S. Patent Nos. 5,486,869/5,754,20 and National Semiconductor LM1881, undated.|
|43||Exhibit G-2-Claim Chart Comparing U.S. Patent Nos. 5,486,869/5,754,250 and U.S. Patent No. 5,260,790, undated.|
|44||Exhibit H-2-Claim Chart Comparing U.S. Patent No. 5,754,250 and Elantec EL4581C/EL4583C, undated.|
|45||Exhibit I-2-Claim chart Comparing Claim 39 of U.S. Patent No. 5,754,250 and U.S. Patent No. 5,432,559, undated.|
|46||Exhibits A-1, A-2, B-1, B-2, B-3, B-4, B-5, B-6, C-1, C-2, D-1, D-2, E-1, E-2, F-1, F-2, G-1, G-2, H-1, H-2, I-1, I-2, J, K, L, M, and N accompanying Expert Report of Richard Kupnicki for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|47||Expert Report of J. Carl Cooper in Rebuttal to the Expert Report of Richard Kupnicki for Defendant Gennum Corporation dated Aug. 15, 2003.|
|48||Expert Report of J. Carl Cooper in Rebuttal to the Expert Report of Richard Kupnicki for Defendant Gennum Corporation, dated Aug. 15, 2003.|
|49||Expert Report Of Richard Kupnicki For Defendant Gennum Corporation for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|50||Gennum's Notice of Motion and Motion for Summary Judgement of Noninfringement and Invalidity of U.S. Patent No. 5,754,250 for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|51||Gennum's Opposition To TLC's Renewed Motion To Stay pending the Outcome of Reissue Proceedings for Case No. CV-01-4204 RS in U.S. District Court for the Northern District of California, San Francisco Division, Sep. 12, 2006.|
|52||Gennum's Reply in Support of Its Motion for Summary Judgment on Non-Infringement and Invalidity of U.S. Patent No. 5,754,250, for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|53||Gennum's Trial Brief dated Apr. 1, 2004.|
|54||GS1881, GS4881, GS4981 Monolithic Video Sync Separators-Data Sheet, dated Oct. 1995.|
|55||GS4882, GS4982 Video Sync Separators with 50% Sync Slicing-Data Sheet, undated.|
|56||Infrigement of US 5,754,250 by Elantec EL1882-Video Sync Separator IC-dated Dec. 9, 1998.|
|57||Infringement of US 5,754,250 by Elantec EL4581-Video Sync Separator IC-dated Dec. 10, 1998.|
|58||Infringement of US 5,754,250 by Elantec EL4583-Video Sync Separator IC-dated Dec. 10, 1998.|
|59||Instruction Manual for Grass Valley Group SCB-200N Sync/Color Bar Generator, pp. 4-1 to 4-7 and Circuit Schematic dated 1989.|
|60||Instruction Manual-DPS-1 Operations Manual (Digital Video Systems) dated Nov. 22, 1977.|
|61||Instruction Manual-DTG-1000N Digital Test Generator (Leitch Video Limited).|
|62||Instruction Manual-DVL 2002 Video Processor Operation and Maintenance Manual (Digital Video Systems) dated Aug. 1976.|
|63||Leitch Video Technology 1000GG Circuit Schematic dated 1981.|
|64||Letter to J. Carl Cooper (Technology Licensing Corporation) from John Mackie (Gennum corporation), Jun. 30, 2004.|
|65||LM1881 Video Sync Separator Application (Preliminary)-National Semiconductor Corporation dated May 1987.|
|66||Millman, Jacob and Grabel, Arvin, Microelectronics(Second Edition), (McGraw-Hill Book Company, 1987), pp. 675-667.|
|67||Millman, Jacob, Ph.D. and Halkias, Christos C., Ph.D., Integrated Electronics: Analog and Digital Circuits and Systems(McGraw-Hill Book Company, 1972), pp. 99, 100, 568.|
|68||National Semiconductor Databook for LM1881, pp. 3-88 to 3-94 dated 1989.|
|69||National Semiconductor LM1881 Video Sync Separator, undated.|
|70||Plaintiff Technology Licensing Corporation's Opening Brief on Claim Constructions dated Sep. 12, 2002.|
|71||Plaintiff Technology Licensing Corporation's Opposition To Gennum's Motions For Summary Judgement Of Noninfringement Of U.S. Patent No. 5,754,250 for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|72||Plaintiff Technology Licensing Corporation's Reply Brief on Claim Construction dated Oct. 4, 2002.|
|73||Rebuttal Expert Report of J. Carl Cooper Regarding U.S. Pat. No. 5,754,250 dated Aug. 15, 2003.|
|74||Rebuttal to Kupnicki Exhibit J, undated.|
|75||Rebuttal to Kupnicki Exhibit K, undated.|
|76||Revised Joint Claim Construction and Pre-Hearing Statement Pursuant to Patent L.R. 403 dated Sep. 10, 2002.|
|77||Schematic for Sync/Color Bars Generator, Sheet 1 of 6 dated May 30, 1989.|
|78||Schematic for Sync/Color Bars Generator, Sheet 2 of 6 dated May 30, 1989.|
|79||Schematic for Sync/Color Bars Generator, Sheet 3 of 6 dated May 30, 1989.|
|80||Schematic for Sync/Color Bars Generator, Sheet 4 of 6 dated May 30, 1989.|
|81||Schematic for Sync/Color Bars Generator, Sheet 5 of 6 dated May 30, 1989.|
|82||Schematic for Sync/Color Bars Generator, Sheet 6 of 6 dated May 30, 1989.|
|83||Sept. 6, 2006 email from Timothy J. Vezeau to J. Donald McCarthy, Mitch Mitchell, and Gloria C. Perez with a copy sent to Michael A. Dorfman, which is attached to a Sep. 6, 2006 email from J. Donald McCarthy to Mitch Mitchell and Gloria C. Perez with a copy sent to Michael A. Dorfman and Timothy J. Vezeau.|
|84||Supplemental Confirmation of Notice Pursuant to 35 U.S.C. § 282 dated Mar. 5, 2004.|
|85||Technology Licensing Corporation v. Gennum Corporation, E-Filed Jun. 1, 2007, Document No. 930, Case No. C 01-4204 RS, "Order re Entry of Final Judgment", Honorable Richard Seeborg-Judge, in the U.S. District Court for the Northern District of California, San Jose Division, pp. 1-3.|
|86||Technology Licensing Corporation v. Gennum Corporation, E-Filed Jun. 1, 2007, Document No. 931, Case No. C 01-4204 RS, "Judgment", Honorable Richard Seeborg-Judge, in the U.S. District Court for the Northern District of California, San Jose Division, pp. 1-3.|
|87||Technology Licensing Corporation v. Gennum Corporation, E-Filed May 4, 2007, Document No. 925, Case No. C 01-04204 RS, "Opinion and Order", Honorable Richard Seeborg-Judge, in U.S. District Court for the Northern District of California, San Jose Division, pp. 1-43.|
|88||Technology Licensing Corporation vs. Gennum Corporation, Filed Nov. 21, 2006, Document 904, Case No. C 01-4204-RS, "Gennum's Post Trial Brief", Honorable Richard Seeborg-Judge, in the U.S. District Court for the Northern District of California, San Jose Division, pp. 1-41.|
|89||Technology Licensing Corporation vs. Gennum Corporation, Filed Nov. 21, 2006, Document 905, Case No. C 01-4204-RS, "Gennum's Proposed Findings of Fact and Conclusions of Law", Honorable Richard Seeborg-Judge, in the U.S. District Court for the Northern District of California, San Jose Division, pp. 1-111.|
|90||Technology Licensing Corporation vs. Gennum Corporation, Filed Nov. 21, 2006, Document 906, Case No. CV-01-4204 RS, "Technology Licensing Corporation's Post-Trial Brief", Honorable Richard Seeborg-Judge, in the U.S. District Court for the Northern District of California, San Jose Division, pp. 1-44.|
|91||Technology Licensing Corporation vs. Gennum Corporation, Filed Nov. 21, 2006, Document 907, Case No. CV-01-4204 RS, "Technology Licensing Corporation's Proposed Findings of Fact and Conclusions of Law", Honorable Richard Seeborg, in the U.S. District Court for the Northern District of California, San Jose Division, pp. 1-274.|
|92||Technology Licensing Corporation vs. Gennum Corporation, Oct. 17, 2006, Morning Session, Case No. C-01-4204 RS, Transcript of Proceedings before the Honorable Richard Seeborg, United States Magistrate Judge, in U.S. District Court for the Northern District of California, San Jose Division, vol. 2, pp. 242-355.|
|93||Technology Licensing Corporation vs. Gennum Corporation, Oct. 17, 2006, PM Session, Case No. C-01-4204 RS, Transcript of Proceedings before the Honorable Richard Seeborg, United States Magistrate Judge, in U.S. District Court for the Northern District of California, San Jose Division, vol. 2, pp. 356-454.|
|94||Technology Licensing Corporation vs. Gennum Corporation, Oct. 18, 2006 Case No. C-01-4204 RS, Transcript of Proceedings before the Honorable Richard Seeborg, United States Magistrate Judge, in U.S. District Court for the Northern District of California, San Jose Division, vol. 3, pp. 455-716.|
|95||Technology Licensing Corporation vs. Gennum Corporation, Oct. 19, 2006, Case No. C-01-4204 RS, Transcript of Proceedings before the Honorable Richard Seeborg, United States Magistrate Judge, in U.S. District Court for the Northern District of California, San Jose Division, vol. 4, pp. 717-980.|
|96||Technology Licensing Corporation vs. Gennum Corporation, Oct. 20, 2006, Case No. C-01-4204 RS, Transcript of Proceedings before the Honorable Richard Seeborg, United States Magistrate Judge, in U.S. District Court for the Northern District of California, San Jose Division, vol. 5, pp. 981-1228.|
|97||Technology Licensing Corporation vs. Gennum Corporation, Oct. 23, 2006, Case No. C-01-4204 RS, Transcript of Proceedings before the Honorable Richard Seeborg, United States Magistrate Judge, in U.S. District Court for the Northern District of California, San Jose Division, vol. 6, pp. 1229-1454.|
|98||Technology Licensing Corporation vs. Gennum Corporation, Trial Day 1, Oct. 16, 2006, Case No. C-01-4204 RS, Transcript of Proceedings before the Honorable Richard Seeborg, United States Magistrate Judge, in U.S. District Court for the Northern District of California, San Jose Division, vol. 1, pp. 1-241.|
|99||Third-Party Defendant Gennum's First Amended Claims Against Plaintiff Technology Licensing Corporation and Third Party Claim Defendant J. Carl Cooper for: (1) Declaratory Judgment (2) § 43(a) of the Lanham Act (3).|
|100||Third-Party Defendant Gennun's Claims Against Plaintiff Technology Licensing Corporation, and Statement of Third-Party Plaintiff's Defenses Against Plaintiff dated Jan. 6, 2003.|
|101||Trial Exhibit 296 for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Rebuttal of Invalidity Assertions Re U.S. Patent No. 5,754,250.|
|102||*||TV Technology "And the Winner is VSB . . . Maybe" Weiss, Apr. 1994.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8471835 *||Sep 3, 2009||Jun 25, 2013||Fujitsu Component Limited||Receiver and signal transmission system|
|US20100053454 *||Sep 3, 2009||Mar 4, 2010||Fujitsu Component Limited||Receiver and signal transmission system|
|U.S. Classification||348/525, 348/529, 348/530, 348/521, 348/E05.017, 348/524, 348/531|
|International Classification||H04N5/10, H04N5/08|