|Publication number||USRE40412 E1|
|Application number||US 10/857,341|
|Publication date||Jul 1, 2008|
|Filing date||Jun 1, 2004|
|Priority date||Feb 18, 1992|
|Also published as||US5486869|
|Publication number||10857341, 857341, US RE40412 E1, US RE40412E1, US-E1-RE40412, USRE40412 E1, USRE40412E1|
|Inventors||J. Carl Cooper|
|Original Assignee||Cooper J Carl|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (66), Non-Patent Citations (99), Referenced by (8), Classifications (10)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 07/837,323, filed Feb. 18, 1992, now abandoned.
The present invention relates to signal processing systems and, in particularly particular, to video signal processing. A major objective of the present invention is a synchronizing signal processing apparatus and a method that precisely recovers synchronizing signals of a video signal.
Much of modern technology depends on signal processing. A common application of signal processing is for the video signal. Usually, a video signal includes picture synchronizing information. The synchronizing information is transmitted for scanning in a receiver in exact synchronism with a camera-tube scanning. The synchronizing signal must first be recovered from the video signal.
More particularly, TV (Television) video signals, the an example of the video signal, are processed to obtain desired picture quality. A TV transmitting station modulates video and audio signals and transmits them out by an antenna so that TV receivers may receive them to produce the pictures. In order to precisely reproduce pictures, synchronizing information is added in the video signal so that the receivers can synchronously perform scanning operation as the TV transmitting station does.
Numerical and graphical criteria which describe essential aspects of a TV system, are employed in the design and operation of equipment to assure that the various parts of the system will operate in cooperative fashion at maximum performance. TV systems have a special need, compared with other communication systems, for definitive standards because television transmitters and receivers must operate in a precise “lock-and-key” relationship. In particular, the scanning of the image in the camera must be matched by the scanning in every associated receiver within a timing precision of approximately one-tenth of a millionth of a second, and with relative positions of picture details correct to a few hundredths of an inch as viewed on the CRT or other display.
To assure that any television receiver can receive programs from any transmitter within range, it is customary to set up a single set of standards with a group of neighboring countries. The TV transmitting stations of different countries and areas transmit video signals with different formats. For example, U.S.A., Canada and Japan et al. use the NTSC (National Television System Committee) system. France, Soviet Union et al. use the SECAM (Sequential Couleura Memoire) system. Germany and United Kingdom et al. then use the PAL (Phase Alternation Line) system. Moreover, HDTV (High Definition TV) creates a new system with images of high resolution. For all of these examples, the synchronizing signals added in their video signals are different.
Picture synchronizing information is obtained from the video signal by means of sync separation circuits. In addition, these circuits must separate this information from noise and interference during the reception of weak signals, particularly if impulse noise is present. To reproduce these different video signals of respective systems, different video signal processing devices are needed to provide required synchronizing signals.
Conventional video signal devices for processing the synchronizing information of the video signals can not be used for different standard video signals for providing reliable synchronizing signals, without affecting the reproduction of the video signals or causing high cost of video signal processing. What is needed is a synchronizing signal processing apparatus and method that precisely recovers synchronizing signals of the video signal and can be applied for processing different video signals.
In accordance with the present invention, a synchronizing signal processing apparatus includes means for sampling synchronizing signals and slicing a video signal in response to the sampled synchronizing signals. The synchronizing signal processing apparatus includes a sampling means that samples the synchronizing signals and provides at least a reference signal. The synchronizing signal processing apparatus also includes a comparing means that slices the video signal in response to the at least a reference signal representing different levels of each of the synchronizing pulses. Thus, the synchronizing signal processing apparatus generates logic level outputs. The video signal with which the present invention is used may be of a standard type having synchronizing pulses including horizontal synchronizing pulses.
The video signal may be sliced, before it is sampled, to eliminate noise. The sliced video signal corresponds to the synchronizing pulses. In response to the sliced video signal, the peaks of the synchronizing pulses of the video signal are precisely sampled. Two sampled signals represent the positive and negative peaks of the synchronizing pulses. The two sampled signals further are divided into three reference signals to compare with the video signal. After this comparison, the logic outputs are combined to recover synchronizing pulses that are reliable, precise and without noise.
A combining means couples to the comparing means so that the outputs from the comparing means are combined depending on the type of the video signal. The combining means generates a plurality of synchronizing signals.
To provide a vertical synchronizing signal, the present invention uses a filtering means that filters one of synchronizing signals output from the combining to provide a vertical synchronizing signal. The filter means shows a good frequency response characteristic for the vertical synchronizing signal.
The synchronizing signal processing method in accordance with the present invention comprises steps of slicing a video signal sampling the video signal in response to respective leading and trailing edges of the sliced signal, converting the sampled signal into at least a reference signal, comparing the reference signal with the video signals and combining the compared outputs to recover synchronizing pulses.
An advantage of the synchronizing signal processing apparatus and method is that the present invention incorporates several standard functions with superior performance. The synchronizing signal processing apparatus in accordance with the present invention is capable of operating with standard two level synchronizing pulses, for example, NTSC, PAL and SECAM type synchronizing pulses, and three level synchronizing pulses, for example HDTV synchronizing pulses. The present invention may also applied for other video type signals with synchronizing pulses.
Furthermore, the present invention provides good bandwidth properties and time constant in the video amplifier section. The combination of the both proper bandwidth and time constant gives considerably noise immunity against high frequency noise, yet maintains sufficient operation speed for high performance. Therefore, no additional compensation or filtering components are needed.
The synchronizing signal processing apparatus in accordance with the present invention may be easily adjusted for either two level or three level synchronizing pulses. The recovered synchronizing levels for video signals are characterized by high precision and reliability.
The logic level outputs of the comparing means are combined, the combination depending on whether the synchronizing pulses are two levels or three levels. In accordance with the present invention, the synchronizing signal processing apparatus may generate a TTL (Transistor-Transistor level) version of the synchronizing pulses.
The synchronizing signal processing apparatus in accordance with the present invention may be used with different video devices, which simplifies the design and manufacture of video devices, and significantly decreases the cost to make these video devices.
Another advantage of the synchronizing signal processing apparatus of the present invention is that it is suitable to be implemented by integrated circuits. Alternatively, the video signal processing can be implemented by software, such as in signal processing application. These and other features and advantages of the present invention are apparent from the description below with reference to the following drawings.
A synchronizing signal processing apparatus 100 in accordance with the present invention includes an input amplifier 102, a video standard detector 103, a sync pulse processing section 104, a pulse width adjust 106, an offset device 108, a DC (Direct Current) restoration device 110, a reference sync generating section 112 and a sync restoring section 114.
Video signal 116 101 is applied to differential input amplifier 102 where video signal 101 is amplified to improve the ratio of signal/common mode noise. The video signal amplified by input amplifier 102 is fed to sync pulse processing section 104 which includes a sync tip clamp 116, a sync slicer 118 and a sync tip peak 15 detector 120.
The video signal is first clamped by sync tip clamp 116 to generate a clamped signal which has a known DC level of the synchronizing pulses. The clamped signal is then transferred to sync slicer 118 where the clamped signal is sliced, thereby generating a signal that has the same time period as that of the synchronizing pulses but at standard levels as compared to that of the synchronizing pulses, in this example TTL levels. To effectively eliminate interference and noise, the sync slicer 118 slices the synchronizing pulses at a known level which is preferred to be about half of the nominal expected amplitude of the synchronizing pulses. Due to the a known level which is approximately half the expected level, the operation of sync slicer 118 may be considered a coarse slicing operation which provides coarse sliced pulses. The sliced signal is coupled to sync tip peak detector 120, in which peaks of synchronizing pulses of the video signal from DC restoration device 110 are sampled in response to the sliced signal.
The clamped signal is also delivered to pulse width adjust 106. This clamped signal activates pulse width adjust 106 to generate a pulse trigger signal coupling to DC restoration device 110. The pulse trigger signal determines the pulse width of the synchronizing pulses. A switch SWP is provided with pulse width adjust 106. Changing the status of the switch SWP may adjust the width of the pulse trigger signal.
The video standard detector 103 is provided for determining the video signal output from the input amplifier 102. When the video signal, for example, is a NTSC video signal, video standard detector 103 controls switch SWL, so that this switch is open, which indicates that the video signal is a NTSC TV signal. On the other hand, when the video signal output from the input amplifier 102 is a HDTV signal, the video standard detector 103 will turn switch SWP on. The video standard detector 103 also control switches SWT, SWU and SWL. The switches may be operated automatically in response to a video standard detector 103 which detects the type of signal 101. Therefore, the synchronizing signal processing apparatus 100 in accordance with the present invention may process different video signals.
Offset device 108 provides a DC reference for DC restoration 110. The amplified video signal from the input amplifier 102 is also coupled to DC restoration 110. In response to the reference from offset device 108, DC restoration 110 clamps the amplified video signal to eliminate DC shift and residual common mode noise.
Other types of DC restoration circuits may be used as is well known in the art. It is desired to have the video signal VO1 and VO2 restored to a known value. However, it should be noted that the DC restoration device 110 may be eliminated by directly AC coupling the video signal output from the input amplifier 102 to the reference sync generating section 112 and sync pulse processing section 104. The operation of sync tip peak detector 120 will track the variations in the AC coupled video signal output from the input amplifier 102 and allow the comparator 122 to function properly. However, the use of a DC restoration device is preferred.
The DC restoration device 110 produces two output signals VO1 and VO2. The clamped video signal VO2 is delivered to sync tip peak detector 120. In response to the sliced signal from the sync slicer 118, sync tip peak detector 120 samples the positive and negative peaks of synchronizing pulses of the clamped video signal so as to provide two peak sample pulse signals. For purpose purposes of the present example, video is described with respect to positive white with the negative level of sync being that which is farthest from peak white video and the positive level of sync being that which is closest to the peak white value of the video. For two level sync, such as NTSC, the positive peak will correspond to video blanking level. The two peak sample pulse signals define each of the synchronizing pulse pulses. Divider 124 receives them and converts them into three pulse reference signals. The amplitudes of the pulse reference signals represent percentage levels of sync of VO2 during the respective ones of the peak sample pulses as represented by Vh and VI.
Reference sync generating section 112 also includes a comparator 122. The clamped video signal from DC restoration 110 and three pulse reference signals are coupled to comparator 122. By comparison, comparator 122 outputs four level signals during each synchronizing pulse of the video signal. Due to the use of references which are responsive to the actual level of the sync pulse, the comparator 122 may be considered a precision comparator, which outputs precision sliced pulses. The four level signals represent different amplitudes of each synchronizing pulse as determined by the video sync being greater than none, one, two or three of the pulse reference signals.
A sync restoring section 114, which includes combination logic 126 and vertical sync filter 128, is arranged to receive the output signals from the comparator 122 of reference sync generating section 112. The combination logic 126 is used to combine the four output signals from comparator 122 to recover reliable synchronizing signals. Switches SWU and SWL are arranged to control the switching between the HDTV video signal and conventional TV video signals, for example NTSC TV video signal.
The opening of switches SWU and SWL indicates that the synchronizing signal processing apparatus operates with conventional video signal. Otherwise, the closing of the switches SWU and SWL shows out that the apparatus operates with HDTV video signal. The position of another switch SWT is also related to the video signal being processed by the apparatus in according accordance with the present invention. Therefore, the apparatus of the present invention is suitable to different video signals by changing status of these switches, which may respond automatically to the video standard detector 103 as well.
The vertical sync filter 128 is coupled to the combination logic 126. A composite synchronizing signal CS from the combination logic 126 is coupled to it. The vertical sync filter 128 filters the composite synchronizing signal CS to provide a vertical synchronizing signal VS. The vertical sync filter 128 may respond to a composite synchronizing signal from other sections as well, for example from 112.
The sync pulse processing section 104 of synchronizing signal processing apparatus 100 is detailed with reference to FIG. 2. Input amplifier 102 includes two operational amplifiers OP1 and OP2. OP1 is used with OP2 to eliminate common mode noise of the video signal 101. The positive input of OP1 receives one of input video signal 101 which is the common one (shield) of the input signals. Resistor R1, 100 KΩ, is an input resistor for stabilizing the DC component of the input video signal.
A resistor R2 (75 Ω) and a switch SWl are connected between the input lines for terminating video signal 101. When the input is taken from other than the end of a coaxial cable run, SWI is open. While the video signal 101 is applied to input amplifier 102 at the end of a coaxial cable run, SWL is closed so that the input resistance of input amplifier 102 is matching the output resistance of the circuitry providing video signal 101, thereby reducing signal loss. Capacitor C1 (0.1 μf) provides a high frequency bypass from the common to ground. R2 is the terminating resistor (75 Ω). OP1 and resistors R3 (1.10 k KΩ) and R4 (499 Ωconstitute Ω) constitute a negative feedback amplifier its gain being two approximately. The output of OP1 is coupled to the negative input of OP2 via resistor R5, 2.21 KΩ.
The positive input of OP2 receives the signal directly from the input signal 116 101. OP2 and resistors R6, R7 and potentiometer R8 provide another feedback amplifier. Resistor R6 and R7 have the same resistance, 1.0 KΩ. The potentiometer R8 has a resistance from 0-10 KΩ. Thus, the gain of the input amplifier 102 may be adjusted between 1.5-3. Due to the delay caused by OP1, the common mode component of input signal 101 arrives at the positive and negative inputs of OP2 at slightly different moment. Under low frequency, the delay due to OP1 is tolerable. However, high frequency components of the input video signal, after delay by OP1, would severely affect correlation of the common mode signal, causing distortion of the video signal. Therefore, a filter having capacitor C1 of 0.01 μf is utilized to filter the interference and noise to ground.
The output of OP2 is coupled to the sync tip clamp 116 of the sync pulse processing section 104. The sync tip clamp 116 includes buffers OP3 and OP4, and an amplifier OP5. Resistor R9 (5.6 KΩ) is used with capacitor C2 to by-pass undesired frequency components. The buffered video signal is coupled to the positive input of another buffer OP4 via an isolating capacitor C3, 0.1 μf. A negative 12 V is applied to the isolating capacitor C3 and the positive input of OP4, via a current limit resistor R10, 147 KΩ. R10 effectively constitutes a constant current source. The isolating capacitor C3 is used to isolate the direct current components of the video signal.
The negative 12 V applied to the capacitor C3 draws node N1 toward a negative level, pulling the video signal output from OP3 to a negative level. The negative video signal, after buffering by buffer OP4, is coupled to the negative input of the amplifier OP5 via a resistor R11 with resistance of 10 KΩ. OP5 and a resistor R12 with resistance of 39 KΩ establishes a negative feedback amplifier. The positive input of OP5 is grounded. The resistance of the resistor R12 determines the maximum gain of amplifier OP5, which may be lowered if D3, D4 conduct.
Normally, the output of OP5 is negative. Two diodes D1 and D2 are provided to isolate the output of OP5 from the node N1. When the output of OP5 is above a level required to turn the D1 and D2 on, for example 1.2 V, the capacitor C3 is charged positive. The resistor R10 charges C3 negative, but is countered by the current through D1 and D2 when the video signal is below the ground of the positive input of OP5, thus causing N1 to move in a positive direction, which forces the output signal of OP5 to be returned to a negative value. The other two diodes D3 and D4 are arranged between the negative input and output of OP5. When the video signal at the negative input of OP5 is more positive by a level high enough to turn D3 and D4 on, the negative input and output of OP5 are shorted so that OP5 functions as a buffer and prevents large negative excursions at the output, thereby causing OP5 to recover to normal status very quickly, when returning positive.
Sync slicer 118 includes a comparator CP6. The output of OP5 is directed to the positive input of CP6. The output of OP4 is directed to the negative input of CP6. By comparison of the signals at its inputs, CP6 slices the synchronizing pulses of the video signal at about half of the amplitude. By using both the outputs of OP4 and OP5, the comparison is less sensitive to noise and sync amplitude variations than if a fixed level were used. For the NTSC and HDTV video signals, the output of CP6 has a delay of about 0.1 μs. Comparator CP6 slices the amplitude of the synchronizing pulses without appreciable change of pulse width.
The sliced pulses output from CP6 are directed to the sync tip peak detector 120. The sync tip peak detector 120 includes sample switches SW1 and SW2, and two sample holders consisting of resistors R15 and R16 with the same resistance of 1 KΩ, and capacitors C6 and C7 with the same capacitance of 0.1 μf. Resistor R15, capacitor C6 and switch SW1 constitute a sample and hold circuit. Resistor R16 and capacitor C7 and SW2 constitute another sample and hold circuit. Two buffers OP7 and OP8 are respectively coupled to the two sample and hold circuits to output the sampled signals.
The sliced pulses from CP6 are first inverted by an invertor I1. Thus, the rising edge of the inverted pulses coincide with the trailing edge of the output pulses of CP6. Each of the inverted pulses is then differentiated at its rising edges, by means of a differential capacitor C4 of 0.001 μf and a differential resistor R13 of 330Ω. The switch SW1 is in the receipt of the signal VO2 output from the DC restoration device 110. Usually, switch SW1 is tied to ground via resistor R13. Only upon the arrival of the rising edges of the inverted pulses, switch SW1 is activated to couple to the hold circuit having R15 and C6. Therefore, corresponding to each falling edge of the sliced pulses output from CP6, R15 and C6 sample the positive peaks of the pulses. Note that the sliced sync from CP6 is opposite in polarity to the sync of VO2. The sampled positive peak is held for the buffer OP7 to output. The width of the differential pulse for sampling the video signal is set by C4 and R13.
Similarly, after inversion twice by invertors I2 and I3, the output of CP6 is differentiated by a differential capacitor C5 of 0.001 μf and a different differential resistor R14 of 330Ω. Thus a differential pulse is coupled to switch SW2. The differential pulses produced by C5 and R14 cause the switch SW2 to close so that a resistor R16 of 1 KΩ and a capacitor C7 of 0.1 μf hold the negative peaks of the synchronizing pulses. The two signals which operate sample switches SW1 SW1 and SW2 SW2 can be described as reference taking signals, since they take the instant samples which are in turn held by the hold capacitors to generate the voltage reference signals used by the divider 124 to provide reference for comparator 122.
As a result, each of the pair of differential pulses produced by C4, R13, C5 and R14 defines the pulse position of respective synchronizing pulses. The relationship of the output pulses of CP6 and the differential pulses is shown in FIG. 5. Furthermore, buffers OP7 and OP8 deliver the peak sample signals to divider 124 for further processing.
The video signal amplified by the input amplifier 102 is also coupled to the DC restoration device 110, referring to FIG. 3. The DC restoration device 110 includes a voltage comparator CP9, a photosensitive element having a LED (light-emitting diode) Du and a photoresistor R59, an amplifiers amplifier OP10 and a buffer OP11. A positive 5 V DC voltage is tied to a resistor R17 or 1.0 KΩ, the left part of the photoresistor R59 and the tap of R16 R59 is connected to ground. Thus, the voltage applied to the positive input of the CP9 depends on the resistance of left part of R59. On the other hand, the positive 5 V is tied to a series connection of potentiometer R18 and a resistor R19 and to ground. Thus, the reference voltage at the negative input of CP9 is defined by the position of the wiper of potentiometer R18. Therefore, adjusting the position of the wiper of potentiometer R18 may change the input voltage at the negative input of CP9.
At the output of CP9, a positive 5 V is applied to the LED Du through a resistor R20 of 200Ω. The positive 5 V provides an offset current to LED Du. The light intensity of the LED Du is in proportion to the current flowing through it. The resistance of photoresistor R59 is inversely proportional to the light intensity. Therefore, the higher the output of CP9, the larger the current through the LED Du, the lower the resistance of the photoresistor R59. The lower resistance of R59 makes the voltage applied to the positive input of CP9 go down, thereby causing the output of CP9 to decrease. CP9 thus causes R59 to maintain the voltage at the positive and negative inputs of CP9 to be equal.
The output of the input amplifier 102 is coupled to the positive input of the amplifier OP10 of DC restoration device 110, via a resistor R1 R21 of 330Ω. The output of OP10 is tied to the negative input via a feedback resistor R22, 1.0 KΩ and the right part of the photoresistor R59 ties the negative input of OP10 to ground. Because the output of CP9 may change the resistance of R59, the gain of OP10 is also controlled by the output of CP9. Therefore, changing the position of the wiper of potentiometer R18 changes the gain of OP10.
The output of OP10 is applied to the positive input of amplifier OP11. Along with a resistor R23 of 1.0 KΩ, the operational amplifier OP11 buffers the output of OP10. The video signal from buffer OP11 is transferred to the sync tip peak detector 120 where the video signal is sampled in response to the pulses from the sync slicer 118, as shown in FIG. 2. The video signal output amplified by OP10 is also sent out by an output resistor R24, 71.5Ω for other purposes.
An offset device 108 is arranged to provide a DC offset required by the operational amplifier OP13 of the DC restoration device 110. The offset device 108 includes a resistor network having a resistor R57 (100 KΩ), a resistor R57 R56 (100 Ω) and a potentiometer R55. A positive 12 V is coupled to resistor R57 and a negative 12 V is coupled to resistor R25 R56. A voltage determined by the position of the wiper of potentiometer R55 charges a capacitor C13 of 0.1 μf via a resistor R58 of 100 KΩ. The level on the capacitor C13 is applied to the positive input of a buffer OP12.
The offset voltage is delivered to an integrator circuit established by a operational amplifier OP 13 and a capacitor C8 (0.1 μf) bridging between the negative input and output of OP13. The positive input of OP13 receives the offset voltage. The offset voltage is also coupled to a switch SW3. The common close status of SW3 couples the offset voltage to the negative input of OP13 via a resistor R25 of 10 KΩ. A capacitor C9 of 0.001 μf is tied between ground and SW3 for filtering undesired frequency components and switching transients.
In accordance with the present invention, the pulse width adjust 106 is provided for . The pulse width adjust 106 includes two multivibrators 301 and 302. The output from the sync slicer 118 is coupled to the A Ā input of 301, as shown in
The output from sync slicer 118 is also coupled to the B input of multivibrator 302 via a delay circuit. This delay circuit includes two RC filters. A capacitor C14 (51 pf) and a resistor R28 (10 KΩ) form a RC filter and a capacitor C12 (56 pf) and a resistor R60 (2.5 KΩ) provide another one. Two invertors I4 and I5 are arranged between the two RC filters. An invertor I6 is positioned between the B input of 302 and RC filter having C12 and R60. A positive 5 V is applied to R28 via a resistor R58 R27 (1 k KΩ) for providing a DC bias. This delay circuit delays the sliced signal from sync slicer 118 about 0.75 μs to 0.9 μs.
The pulses at the
Therefore, the pulse width of Q output of 302 is between 2 μs and 2.5 μs for the NTSC video signal. This pulse occurs during blanking and burst portion of the NTSC video signal. On the other hand, the pulse width of the Q output of 302, for the HDTV video signal, is from 0.5 μs to 0.7 μs. The pulse of Q output of 302 coincides with the blanking portion without exceeding it. The waveform at the Q output of 301 is shown in FIG. 5.
The output pulses at the Q output of 302 activate the SW3 so that the output from OP11 is coupled to the negative input of OP13 via the RC filter having the resistor R25 and the capacitor C9. During the high level of the pulses from 302, the capacitor C8 of the integrator OP13 is charged up and down by the video signal from the buffer OP11 depending on whether it is above or below the reference on the plus input of OP13, drawing the input voltage at the positive input of OP10 up or down. As a result, the output of OP10 is drawn up or down. After the Q output of 302 recovers to a low level, the switch SW3 is released so that the negative input of the operational amplifier OP13 is coupled to the output of OP12 of the offset device 108. Thus, the 10 output of the operational amplifier OP13 does not change.
The divider 124 of the reference sync generating section 112 includes four resistors R31, R32, R33 and R34. The resistors R31-R34 have the same resistance of 10 KΩ. Therefore, the output potential of the sync tip peak detector 120 is equally divided so that three reference potentials are provided. The first reference potential between the resistors R33 and R34 equals half of the output potential from the sync tip peak detector 120. The second reference potential between the resistors R31 and R33 equals three-fourth of the output level from the sync tip peak detector 120. The third reference potential between the resistors R32 and R34 equals one-fourth of the output level from the sync tip peak detector 120. However, different reference potentials may also be obtained by changing the resistance of resistors R31-R34. Different combination of potentials on the positive inputs of CP14-CP16 can be easily realized.
In accordance with the present invention, the comparator 122 of reference sync generating section 112 includes three comparators CP14, CP15 and CP16. The first reference potential between the resistors R33 and R34 is applied to the positive input of comparator CP14. The second reference potential between the resistors R31 and R33 is applied to the positive input of the comparator CP15. The third reference potential is then applied to the positive input of the comparator CP16. The video signal output VO1 from the amplifier OP10 of the DC restoration device 110 is coupled to respective negative inputs of three comparators CP14-CP16 via resistor R35, R36 and R37.
As for conventional TV video signals, for example, the NTSC video signal, CP14 compares the first reference potential and the video signal VO1 so as to sense the middle levels of the horizontal and vertical synchronizing pulses. The comparator CP15 then senses the video signal VO1 in response to the second reference potential and the rest of the video signal VO1 is regarded as noise. Because the switch SW1 of sync tip peak detector 120 closes during the blanking-burst period to sample the video signal, the second reference potential is set to a level lower than the blanking level. The switch SW2 of sync tip peak detector 120 closes during the negative synchronizing tip to sample the video signal, the third reference potential is thus set to a level higher than the negative tip. Two complementary outputs VP3 and VC3 from CP16 are delivered to the combination logic 126.
As a second example, when the apparatus 100 in accordance with the present invention is used for processing the HDTV video signal, the second reference potential represents a value between the blanking and positive peak synchronizing tip for the synchronizing pulses. The rest of the video signal VO1 is considered as noise. The first reference potential is set at the middle of the negative and positive synchronizing tip during synchronizing pulses, meaning at the blanking level. The purpose of this comparator CP14 is to sense transition from the negative synchronizing tip to the positive synchronizing tip. The rest of the video signal VO1 is considered as noise. The reference potential and the output VP3 of CP16 is the same as under the NTSC video signal. Therefore, outputs of comparator 122 are logic levels corresponding to the negative sync for these video signals.
The logic level outputs VP1, VP2, VP3 and VC3 from the comparator 122 are directed to the combination logic 126 of the sync restoring section 114, as shown in FIG. 4. The output VP1 of the comparator CP14 is directed to an input of an AND gate A1. The signal VC3 output from the comparator CP16 is inverted by an invertor I7, and is filtered by a RC filer having a resistor R53 (200Ω) and a capacitor C17 (0.001 μf). Before it is applied to another input of the AND gate A1, the filter signal VC3 is inverted again by an invertor I8. In order to preserve the combination logic generated sync information at the half way crossing, the output VC3 from the comparator CP16 is delayed by the invertor I7 and I8 circuit for 85 ns-200 ns. Thus, the two input pulses are anded at the inputs of the AND gate A1 so that the output of A1 is a positive pulse.
Along with the output from the AND gate A1, the output VP2 from the comparator CP15 is directed to an input of an OR gate O1. The positive pulse from A1 and the VP2 active the OR gate O1, thereby producing a pulse which has a rising edge defined by the positive pulse from A1 and a falling edge defined by V′P2. The output of OR gate O1 is directed to another OR gate O2.
The output VC3 is also used to trigger a multivibrator 401 so that a high level is set at the
The ANDed output from A2 is applied to another input of OR gate O2 so that the output from OR gate O1 is ORed with the ANDed output from A2. Particularly, under processing the NTSC video signal, the ORed output of OR gate O1 is completely determined by the ANDed output pulse from A2. The reason is that the negative ANDed output from A2 is narrower than the negative ORed output from O1. The output of O2 is a composite synchronizing output CS.
In order to extract horizontal synchronizing pulses from the output CS from the OR gate O2, a circuitry including multivibrators 402 and 403, and OR gates O3 and O4 is designed. This circuitry eliminates every second half horizontal pulse from the vertical interval. The signal VC3 output from the comparator CP16 is directed to the multivibrator 402, where VC3 triggers the B input of 402 to set a low level at its
The Q output of 403, along with the
A multivibrator 404 is used to generate a horizontal square waveform output HQ. The output HS of the OR gate O4 is coupled to the B input of 404 via the switch SWT. When the apparatus 100 of the present invention operates under the HDTV video signal, the rising edges of output HS triggers 404 at the B input to set a high level output at its Q output. Meanwhile, the switch SWL is closed so that the positive 5 V is applied to 404 via shunted resistors R42 and R43 and a capacitor C21. Accordingly, the duration of the high level depends on a capacitor C21 and the resistance of shunted resistors R42 and R43. If the capacitance of C21 is set as 0.001 μf and R42 and R43 are respectively set as 51 KΩ, the duration is then 30 μs.
If the apparatus 100 of the present invention operates with the NTSC video signal, the output HS is reversed by an invertor I6 I9 so that the B input of 404 is triggered by the falling edges of the synchronizing pulse, setting a high level at its Q output. At the same time, the switch SWL is open so that the positive 5 V voltage is applied to 404 via only a resistor R42. Assuming R42 has the resistance of 51 KΩ and C31 C21 has the capacitance of 0.001 μf, the duration of the high level at the Q output of 404 is 30 μs.
The output CS of OR gate O2 is also directed to a vertical synchronizing filter circuitry including operational amplifiers OP17 and OP18. A resistor R44 of 37.4 KΩ and a capacitor C22 of 0.001 μf bridge across the output and negative input of OP17 to form a first stage low pass filter. The positive input of OP17 is tied to ground. The composite synchronizing output CS is coupled to the negative input of OP17 via a resistor R52 of 39 KΩ. The output from OP17 is coupled to the negative input of OP18 via a 10 Ω resistor R50. The positive input of OP18 is tied to ground. A resistor R45 (10 KΩ) and a capacitor C15 (0.001 μf) are shunted across the negative input and the output of OP18, thereby providing a second stage low pass filter.
This vertical filter circuitry employs a design 25 offsetting conventional optimal design. This design provides a frequency response characteristic without matching standard filter design curves which are commonly known. However, it is this design that provides a frequency response characteristic good for vertical synchronizing separation of the NTSC or HDTV video signal. This frequency response of the filter circuitry is shown in FIG. 6.
The filtered signal is applied to a positive input of a comparator CP19 via a 330Ω resistor R51. A resistor R46 of 3.3 k KΩ is bridged between the positive input and output of CP19 to provide positive feedback hysteresis for CP19. A positive 5 V voltage is tied to ground via resistors R47 and R48. R47 has resistance of 20 KΩ and R48 has resistance of 10 KΩ. A capacitor C16 of 0.1 μf is shunted across resistor R48, thereby providing a stable reference voltage to the negative input of CP19. Furthermore, a positive 5 V voltage is applied to the output of CP19 via a resistor R49 (1 KΩ). Filter circuitry provides a vertical synchronizing output VS via CP19 and inverted by an invertor 110.
To obtain a field synchronizing output, the vertical synchronizing output from CP19 is directed to a flip-flop 405. The clear input CLR and set input PR of 405 are coupled to a positive 5 V. The CK input of 405 receives vertical sync and the D input of 405 is coupled to H sync square waveform the
A processing method 700 for synchronizing pulses of the video signals is shown in FIG. 7. At step 701, the video signal is sliced to produce synchronizing pulses. The video signal is then sampled in response to the sliced sync to precisely sense the sync tip peaks pulses, at step 702, thereby providing two peak signal values representing the positive and negative peak values of each synchronizing pulse.
The peak signal values are further converted, at step 703, into three reference signals which respectively represent the different levels relative to each synchronizing pulse. In particular, the three reference levels respectively represent the middle, upper and lower middle levels of the synchronizing pulse. Comparison of the three reference levels and the video signal is conducted at step 704. As a result of this comparison, the logic pulse outputs are obtained. Step 705 is for restoring synchronizing pulses of the video signal by combining the logic outputs.
One skilled in the art will recognize that the above described functions and components are somewhat more complex than represented by the present block diagrams, however from the disclosure and teachings herein, taken with the available applications literature available from the manufacturers of the suggested components, or from other components which may be substituted as will be known from the above disclosure, the construction of a practical and operatable device will be well within the capability of one or ordinary skill in the art without resorting to further invention or undue experimentation.
It will be understood that the previous descriptions and explanations are given by way of example, and that numerous changes in the combinations of elements and functions as well as changes in design of the above may be made without departing from the spirit and scope of the invention as hereinafter claimed. In particular, it will be useful to combine the functions of the invention with other functions in a fashion so that such functions may be shared between devices or methods. These and other modification to and variations upon the embodiments described above are provided for by the present invention, the scope of which is limited only by the following claims.
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|US4573070||May 31, 1984||Feb 25, 1986||Cooper J Carl||Noise reduction system for video signals|
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|US4703355||Sep 16, 1985||Oct 27, 1987||Cooper J Carl||Audio to video timing equalizer method and apparatus|
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|US4816830||Sep 14, 1987||Mar 28, 1989||Cooper James C||Waveform shaping apparatus and method|
|US4829257||Feb 20, 1987||May 9, 1989||Cooper J Carl||Method and apparatus for continuously shifting phase of an electronic signal|
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|US4872070||Sep 11, 1987||Oct 3, 1989||Electro Sound, Inc.||System and method for high speed video tape reproduction|
|US4882624||Mar 11, 1988||Nov 21, 1989||Kabushiki Kaisha Toshiba||Synchronizing signal separation circuit for a television receiver|
|US5097218||Sep 8, 1989||Mar 17, 1992||Cooper James C||Apparatus and method for multiplying the frequency of complex time varying signals|
|US5202761||May 28, 1991||Apr 13, 1993||Cooper J Carl||Audio synchronization apparatus|
|US5260790||Aug 5, 1991||Nov 9, 1993||Canon Kabushiki Kaisha||Synchronizing signal separation device|
|US5424780||Sep 13, 1993||Jun 13, 1995||Cooper; James C.||Apparatus and method for spacial scan modulation of a video display|
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|US5635725||Oct 16, 1996||Jun 3, 1997||Cooper; J. Carl||Apparatus and method for positionally stabilizing an image|
|US5675277||May 23, 1996||Oct 7, 1997||Pixel Instruments||Phase shifting apparatus and method with frequency multiplication|
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|US5793053||Dec 30, 1996||Aug 11, 1998||Cooper; J. Carl||Apparatus and method for positionally enhancing an image|
|US5834747||Feb 19, 1997||Nov 10, 1998||Pixel Instruments||Universal credit card apparatus and method|
|US5874910||Dec 14, 1996||Feb 23, 1999||Cooper; J. Carl||Analog signal coding and transmission apparatus and method capable of operation with multiple types of analog and digital signals|
|US5920842||Oct 12, 1994||Jul 6, 1999||Pixel Instruments||Signal synchronization|
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|US5949087||May 6, 1998||Sep 7, 1999||Cooper; J. Carl||Apparatus and method for positionally enhancing an image|
|US5996906||Jan 5, 1998||Dec 7, 1999||Cooper; J. Carl||Hose nozzle cover|
|US6078038||May 10, 1999||Jun 20, 2000||Cooper; J. Carl||Apparatus and method for displaying a high resolution image with relatively lower resolution display device|
|US6098046||Jun 29, 1998||Aug 1, 2000||Pixel Instruments||Frequency converter system|
|US6141057||Jun 2, 1999||Oct 31, 2000||Pixel Instruments Corp.||Apparatus and method for maintaining synchronization of multiple delayed signals of differing types|
|US6191407||Dec 2, 1998||Feb 20, 2001||J. Carl Cooper||Apparatus and method for spatially stabilizing projected or viewed images with a locating symbol position detection|
|US6308890||Jun 30, 1998||Oct 30, 2001||Pixel Instruments, Inc.||Universal credit card apparatus and method|
|US6330033||Mar 21, 1996||Dec 11, 2001||James Carl Cooper||Pulse detector for ascertaining the processing delay of a signal|
|US6351281||Jul 21, 1998||Feb 26, 2002||James Carl Cooper||Delay tracker|
|US6392707||Jul 28, 2000||May 21, 2002||Pixel Instruments Corp.||Apparatus and method for maintaining synchronization of multiple delayed signals|
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|US6469741||May 2, 2001||Oct 22, 2002||Pixel Instruments Corp.||Apparatus and method for processing television signals|
|US6529637||Mar 3, 1995||Mar 4, 2003||Pixel Instruments Corporation||Spatial scan replication circuit|
|USRE33535||Oct 23, 1989||Feb 12, 1991||Audio to video timing equalizer method and apparatus|
|GB1143241A||Title not available|
|GB2200011A||Title not available|
|JPS5797274A||Title not available|
|JPS58178669A||Title not available|
|JPS63186270A||Title not available|
|1||[Proposed] Claim Construction Order dated Sep. 2002, 17 pages.|
|2||[Proposed] order Granting Gennum's Motions for Summary Judgement On The '869 Patent And On The Reasonable Royalty Measure Of Damages for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|3||[Proposed] Pretrial Order Mar. 12, 2004.|
|4||Addendum To Expert Reports of Richard Kupnicki For Defendant Gennum Corporation for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|5||Advance Product Information/DTG-1000 Digital Test Generator, Leitch.|
|6||Brochure entitled DPS-1 Frame Store dated Mar. 1979.|
|7||Claim Constructiiion Order dated Nov. 14, 2002.|
|8||Complaint by Defendent and Third Party Plaintiff Videotek, Inc. Against Third Party Defendant Gennum Corporation for Breach of Warranty dated Sep. 3, 2002.|
|9||Confirmation of Notice Pursuant to 35 U.S.C. § 282, dated Dec. 4, 2003.|
|10||Consent Decree And Order for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|11||Cooper Rebuttal to Kupnicki Exhibit A-2, undated.|
|12||Cooper Rebuttal to Kupnicki Exhibit B-2, undated.|
|13||Cooper Rebuttal to Kupnicki Exhibit B-4, undated.|
|14||Cooper Rebuttal to Kupnicki Exhibit B-6, undated.|
|15||Cooper Rebuttal to Kupnicki Exhibit C-2, undated.|
|16||Cooper Rebuttal to Kupnicki Exhibit D-2, undated.|
|17||Cooper Rebuttal to Kupnicki Exhibit E-2, undated.|
|18||Cooper Rebuttal to Kupnicki Exhibit F-2, undated.|
|19||Cooper Rebuttal to Kupnicki Exhibit G-2, undated.|
|20||Cooper, J. Carl, "Second generation audio-to-video synchronization", Broadcast Engineering, pp. 68-72, Sep. 1995.|
|21||Cooper, J. Carl, "Sine Squared Shaping of Sync and Drive Pulses", IEEE Transactions on Broadcasting, vol. 36, No. 2, pp. 162-169, Jun. 1990.|
|22||Cooper, J. Carl, "Video-to-Audio Synchrony Monitoring and Correction", SMPTE Journal, vol. 97, No. 2, pp. 695-698, Sep. 1988.|
|23||Cooper, J. Carl, "Viewer Stress from Audio/Visual Sync Problems", SMPTE Journal, vol. 97, No. 2, pp. 140-142, Feb. 1988.|
|24||Data Package 9505-Color Black Sync Pulse Generator Module Assembly No.: 066582-00-1977.|
|25||Declaration of Richard Kupnicki (II) for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|26||Declaration of Richard Kupnicki for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|27||Declaration of Todd R. Miller In Support of Gennum's Opposition To TLC's renewed Motion To Stay for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Sep. 12, 2006.|
|28||Defendant Gennum Corporation's Preliminary Invalidity Contentions for U.S. Patent No. 5,486,869, dated May 16, 2003.|
|29||Defendant Videotek Inc.'s Brief In Support of Its Proposed Claim Construction dated Sep. 27, 1002.|
|30||Defendant Videotek, Inc.'s Final Invalidity Contentions Under PLR 3-6(b) for U.S. Patent No. 5,486,869 dated Jan. 7, 2003, 31 pages.|
|31||Defendant Videotek's Preliminary Invalidity Contentions for U.S. Patent No. 5,486,869 dated May 9, 2002, 17 pages.|
|32||Digital Video System Input Sync Separator 5179 Circuit Schematic dated 1979.|
|33||Digital Video Systems Input Clock Generator 7051 Circuit Schematic dated 1981.|
|34||DPS-1 Digital Processing System price list dated Oct. 1978.|
|35||Elantec EL4581 Sync Separator, 50% Slice, S-H, filter Data Sheet dated 2003, 10 pages.|
|36||Elantec EL-4581C/EL4583C Video Sync Separator Data Sheet, pp. 4-146 to 4-151, dated 1993.|
|37||Elantec EL4583 Sync Separator, 50% Slice, S-H, Filter, H<SUB>oout</SUB>Data Sheet dated 2003, 10 pages.|
|38||Enlarged version of Exhibit 388, dated 1979.|
|39||Enlargement of Schematic for Sync/Color Bars Generator, Sheet 1 of 66 dated May 30, 1989.|
|40||Exhibit A-2-Claim Chart Comparing U.S. Patent No. 5,486,869 and U.S. Patent No. 3,819,859, undated.|
|41||Exhibit B-2-Claim Chart Comparing U.S. Patent No. 5,486,869 and Digital Video System Input Sync Separator 5179, undated.|
|42||Exhibit D-2-Claim Chart Comparing U.S. Patent Nos. 5,486,869/5, 754,250 and U.S. Patent No. 4,233,629, undated.|
|43||Exhibit E-2-Claim Chart Comparing U.S. Patent Nos. 5,486,869/5,754,250 and Grass Valley Group SCB-200N Sync/Color Bar Generator, undated.|
|44||Exhibit F-2-Claim Chart Comparing U.S. Patent Nos. 5,486,869/5,754,250 and National Semiconductor LM1881, undated.|
|45||Exhibit J-Claim Chart Comparing U.S. Patent No. 5,486,869 and U.S. Patent No. 4,233,629, undated.|
|46||Exhibit K-Claim Chart Comparing U.S. Patent No. 5,486,869 and U.S. Patent Nos. 5,560,790, 4,680,633, Digital Video Systems ISS-5179, and National Semiconductor LM1881, undated.|
|47||Exhibits A-1, A-2, B-1, B-2, B-3, B-4, B-5, B-6, C-1, C-2, D-1, D-2, E-1, E-2, F-1, F-2, G-1, G-2, H-1, H-2, I-1, I-2, J, K, L, M, and N accompanying the Expert Report of Richard Kupnicki for Case CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|48||Expert Report of J. Carl Cooper in Rebuttal to the Expert Report of Richard Kupnicki for Defendant Gennum Corporation dated Aug. 15, 2003, 31 pp.|
|49||Expert Report of J. Carl Cooper in Rebuttal to the Expert Report of Richard Kupnicki for Defendant Gennum Corporation, dated Aug. 15, 2003.|
|50||Expert Report Of Richard Kupnicki For Defendant Gennum Corporation for Case CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division.|
|51||Gennum's Notice of Motions and Motions for Summary Judgement of Noninfringement of U.S. Patent No. 5,486,869, and for Partial Summary Judgement Limiting Any Patent Damages to a Reasonable Royalty Based on Genum's.|
|52||Gennum's Notice of Motions for Summary Judgement of Noninfringement of U.S. Patent No. 5,486,869 and For Partial Summary Judgement Limiting Any Patent Damages to a Reasonable Royalty Based Upon Gennum's Revenue for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|53||Gennum's Notice Of Motions For Summary Judgement Of Noninfringement Of U.S. Patent No. 5,486,869, And For Partial Summary Judgement Limiting Any Patent Damages To A Reasonable Royalty Based On Gennum's Revenue for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|54||Gennum's Opposition To TLC's Renewed Motion To Stay pending the Outcome of Reissue Proceedings for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Sep. 12, 2006.|
|55||Gennum's Reply in Support of Its Motions for Summary Judgement on Non-Infringement of U.S. Patent No. 5,486,869, and for Partial Summary Judgement Limiting Any Patent Damages to a Reasonable Royality Based Upon Gennum's Revenue for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|56||Gennum's Trial Brief dated Apr. 1, 2004.|
|57||GS1881, GS4881, GS4981 Monolithic Video Sync Separators-Data Sheet, dated Oct. 1995.|
|58||GS4882, GS4982 Video Sync Separators with 50% Sync Slicing-Data Sheet, undated.|
|59||Input Clock Generator (ICG 7051-1) Preliminary Circuit Description and test Procedures-Prepared by Joseph Yu dated Sep. 1977.|
|60||Instruction Manual for Grass Valley Group SCB-200N Sync/Color Bar Generator, pp. 4-1 to 4-7 and Circuit Schematic dated 1989.|
|61||Instruction Manual-DPS-1 Operations Manual (Digital Video Systems) dated Nov. 22, 1977.|
|62||Instruction manual-DTG 1000N Digital Test Generator, Leitch.|
|63||Instruction Manual-DTG-1000N Digital Test Generator (Leitch Video Limited).|
|64||Instruction Manual-DVL 2002 Video Processor Operation and Maintenance Manual (Digital Video Systems) dated Aug. 1976.|
|65||Leitch Video Technology 1000GC Circuit Schematic dated 1981.|
|66||Letter to J. Carl Cooper (Technology licensing Corporation) from John Mackie (Gennum Corporation), Jun. 30, 2004.|
|67||LLM1881 Video Sync Separator Application (Preliminary)-National Semiconductor Corporation dated May 1987.|
|68||Millman, Jacob and Grabel, Arvin, Microelectronics (Second Edition), (McGraw-Hill Book Company, 1987), pp. 675-687, 7 pages.|
|69||Millman, Jacob, Ph.D. and Halkias, Christos C., Ph.D,, Integrated Electronics: Analog and Digital Circuits and Systems (McGraw-Hill Book Company, 1972), pp. 99, 100, 568.|
|70||National Semiconductor Databook for LM1881, pp. 3-88 to 3-94 dated 1989.|
|71||National Semiconductor LM1881 Video Sync Separator, undated, 8 pages.|
|72||Plaintiff Technology Licensing Corporation's Opening Brief on Claim Constructions dated Sep. 12, 2002.|
|73||Plaintiff Technology Licensing Corporation's Opposition To Gennum's Motions For Summary Judgement Of Noninfringement Of U.S. Patent No. 5,486,869 And For Partial Summary Judgement Limiting Any Patent Damages To A Reasonable Royalty Based On Gennum's Revenue for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Nov. 7, 2003.|
|74||Plaintiff Technology Licensing Corporation's Reply Brief on Claim Construction dated Oct. 4, 2002.|
|75||Product brochure -DPS-1 by Digital Video Systems-"Setting a new standard for the Industry/The Third Generation Time Base Corrector".|
|76||Product brochure-DPS-1 by Digital Video Systems-"First in a new advanced class of digital processors!".|
|77||Product brochure-DVL 2002 Video Processor-"Maximizing Printer Quality".|
|78||Promotional Brochure entitled Phaser dated Mar. 1979.|
|79||Propreitary Information/DTS-2000N Digital Television Scrambler & DTD-2000N Digital Television Descrambler, Preliminary Instruction Manual dated May 26, 1982.|
|80||Rebuttal Report of Richard Kupnicki for Defendant Gennum Corporation, undated.|
|81||Rebuttal to Kupnicki Exhibit J, undated.|
|82||Rebuttal to Kupnicki Exhibit K, undated.|
|83||Revised Joint Claim Coonstruction and Pre-Hearing Statement Pursuant to Patent L.R. 403 dated Sep. 10, 2002.|
|84||Schematic for an electronic circuit-Digital Video Systems Drawing No. 1DS-5179-1 dated Sep. 21, 1976.|
|85||Schematic for circuit design for Digital Video Systems dated 1979.|
|86||Schematic for IGC 7051-Input Clock Generator-Drawing No. 743H72, Digital Video Systems.|
|87||Schematic for Sync/Color Bars Generator, Sheet 1 of 6 dated May 30, 1989.|
|88||Schematic for Sync/Color Bars Generator, Sheet 2 of 6 dated May 30, 1989.|
|89||Schematic for Sync/Color Bars Generator, Sheet 3 of 6 dated May 30, 1989.|
|90||Schematic for Sync/Color Bars Generator, Sheet 4 of 6 dated May 30, 1989.|
|91||Schematic for Sync/Color Bars Generator, Sheet 5 of 6 dated May 30, 1989.|
|92||Schematic for Sync/Color Bars Generator, Sheet 6 of 6 dated May 30, 1989.|
|93||Schematic for the 1000GG drawn by Susan Van Nood dated Dec. 2, 1984.|
|94||Sep. 6, 2006 email from Timothy J. Vezeau to J. Donald McCarthy, Mitch Mitchell, and Gloria C. Perez with a copy sent to Michael A. Dorfman, which is attached to a Sep. 6, 2006 email from J. Donald McCarthy to Mitch Mitchell and Gloria C. Perez with a copy sent to Michael A. Dorfman and Timothy J. Vezeau.|
|95||Supplemental Confirmation of Notice Pursuant to 35 U.S.C. § 282 dated Mar. 5, 2004, 7 pag.|
|96||Technology Licensing Corporationvs. Gennum Corporation,Trial Day 1, Oct. 16, 2006, Case No. C-01-4204 RS, Transcript of Proceedings before the Honorable Richard Seeborg, United States Magistrate Judge, in U.S. District Court for the Northern District of California, San Jose Division, vol. 1, pp. 1-241.|
|97||Third-Party Defendant Gennum's Claims Against Plaintiff Technology Licensing Corporation, and Statement of Third-Party Plaintiff's Defenses Against Plaintiff dated Jan. 6, 2003.|
|98||Third-Party Defendant Gennum's First Amended Claims Against Plaintiff Technology Licensing Corporation and Third Party Claim Defendant J. Carl Cooper for: (1) Declaratory Judgement (2) § 443(a) of the Lanham Act (3) Intentional Interference (4) Statutory Unfair Competition (5) Common Law Unfair Competion (6) Trade Libel, dated Oct. 22, 2003.|
|99||Trial Exhibit 295 for Case No. CV-01-4204 CRB in U.S. District Court for the Northern District of California, San Francisco Division, Rebuttal of Invalidity Assertions Re U.S. Patent No. 5,486,869.|
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|U.S. Classification||348/525, 348/529, 348/530, 348/531, 348/521, 348/E05.017|
|International Classification||H04N5/08, H04N5/10|