US RE40424 E1 Abstract The present invention relates to a structure of a delta-sigma fractional type divider. The divider structure adds an external input value and an output value of a delta-sigma modulator to modulate a value of a swallow counter. Therefore, the present invention can provide a delta-sigma fractional type divider the structure is simple and that can obtain an effect of a structure of a delta sigma mode while having a wide-band frequency mixing capability.
Claims(15) 1. A delta-sigma fractional type divider, comprising:
a delta-sigma modulator for receiving a clock signal and a first digital value to perform a delta-sigma modulation, said first digital value being used to program a fractional ratio frequency of a frequency synthesizer;
a swallow adder group for receiving an output value of said delta-sigma modulator and a second digital value to add an integer dividing ratio of a swallow counter and said output value of said delta-sigma modulator, said second digital value being used to program an integer ratio frequency of the frequency synthesizer;
a program register group for storing an output value of said swallow adder group; and
a pulse swallow counter group having a dual modulus prescaler, a program counter and said swallow counter, for dividing an input frequency depending on said value stored by said program register group.
2. The delta-sigma fractional type divider as claimed in
a first adder for adding the integer dividing ratio of the swallow counter and a sign value; and
a second adder for adding the output value of said delta-sigma modulator and an output value of said first adder.
3. The delta-sigma fractional type divider as claimed in
4. The delta-sigma fractional type divider as claimed in
a swallow register for storing said output value of said swallow adder group; and
a main division register for storing the integer dividing ratio.
5. A delta-sigma fractional type divider, comprising:
a modulator configured to use a first digital value to program a fractional ratio frequency of a frequency synthesizer; an adder group configured to use an output value of said modulator and a second digital value, said second digital value being used to program an integer ratio frequency of the frequency synthesizer; a program register group configured to store an output value of said adder group; and a counter group configured to divide an input frequency depending on said value stored by said program register group. 6. The delta-
sigma fractional type divider as claimed in , wherein said adder group comprises: a first adder operable to add an integer dividing ratio of a counter and a sign value; and a second adder operable to add the output value of said modulator and an output value of said first adder. 7. The delta-sigma fractional type divider as claimed in
8. The delta-sigma fractional type divider as claimed in
a register operable to store said output value of said adder group; and a main division register operable to store the integer dividing ratio. 9. The delta-sigma fractional type divider as claimed in
10. The delta-sigma fractional type divider as claimed in
11. A method for delta-sigma fractional type dividing comprising:
receiving a clock signal and a first digital value to perform a delta-sigma modulation, said first digital value being used to program a fractional ratio frequency of a frequency synthesizer; adding an integer dividing ratio of a counter and an output value of said modulator to produce a second output value; receiving a second digital value to program an integer ratio frequency of the frequency synthesizer; storing the second output value using a program register group; and dividing an input frequency depending on said value stored by said program register group. 12. The method of
adding an integer dividing ratio of the counter and a sign value; and adding the output value of said modulator and an output value of said adding an integer dividing ratio of the counter and a sign value. 13. The method of
14. The method of
storing said second output value in a register; and storing the integer dividing ratio in a main division register. 15. The method of
Description This application is reissue application of U.S. patent application 1. Field of the invention The invention relates generally to a delta-sigma fractional type divider, and more particularly to, a structure of a delta-sigma fractional type divider which is simple, has a wide-band frequency mixing capability and can obtain a delta-sigma mode by maximum. 2. Description of the Prior Art A frequency synthesizer is a circuit for obtaining necessary frequencies depending on a digital code value. The frequency synthesizer is mainly divided into an integer type frequency synthesizer for producing an output frequency of an integer times using an input frequency of a frequency-phase detector, and a fractional type frequency synthesizer improved in phase, synchronizing time, etc. compared to the integer type frequency synthesizer. The fractional type frequency synthesizer has a high spur in process of being implemented even though it's various advantages. Thus, the fractional type frequency synthesizer has a current compensation structure using digital-analog converter, a phase interpolation structure, and a delta-sigma structure in order to remove the spur. The delta-sigma structure disperses the energy of spur generated in a pulse swallowing fraction ratio N frequency synthesizer and transforms the shape of the energy (noise shaping) to implement a high performance frequency synthesizer. [Dual Modulus Fractional N] FIG. The structure of the basic fractional type divider in FIG. In this process, however, variations in the phase generated in period of 1(.f)*f The spur can be generated by a control voltage as follows. When the output of the oscillator is V Therefore, spur is generated at to ω [Multi-Modulus Fractional N] The dual modulus fractional ratio N can be implemented into a first order delta-sigma. As the dual modulus fractional ratio N has the quantization level of /P and /(P+1) by one bit control, at this time, the energy of spur can be effectively dispersed and reduced. In general, the dual modulus fractional ratio N is implemented into a delta sigma of over third order. In case of designing the dual modulus fractional ratio N having a delta sigma of over third order, a delta-sigma modulator of a mash type that can obtain an effect of transformation of energy shape and can obtain high stability is usually applied to a frequency synthesizer. As an output of the modulator of a mash type is multi-bit, a multi-modulus prescaler is required in order for the dividing circuit to accept it. As a result, the dividing circuit requires complicated dividing unit and control unit. A process of inducing the mash type structure is first described, and problems in the conventional multi-modulus dividing circuit is then described. At first, over-sampling (quantization) is described. If quantization errors are white noise, the mean square value is:
And if the quantized signal is sampled to f Noise power of a signal band 0≦f≦f From the above results, it could be seen that over-sampling reduces the in-bands rms quantization noise(n Referring now to FIGS. FIGS. Therefore,
In other words, the delta-sigma shown in In order to obtain the spectral density of n Therefore, it could be seen that the noise component of a low frequency can be reduced. The noise power at the signal band is:
Also, the rms value is:
Thus, it could be seen that a noise is reduced by about 9 dB (corresponding to 1.5 bit resolution) if the over-sampling ratio is doubled. If the input of the delta sigma is a direct current (DC), repetitive noise patterns appear, which is called a patterned noise. And the above equation can be easily obtained through a closed-loop transfer function of a Z-domain model shown in FIG. The delta sigma performs a noise shaping by which the energy of modulation noise is pushed out to the signal band by a feedback using the integrator. At this time, the characteristic of the integrator determines the shape of the noise spectrum. Generally, in case that a L-order loop is formed and system is stable, the spectral density is:
In case of OSR>2, the rms noise at the signal band is: The delta-sigma modulator of this high order can further reduce the quantization noise of a signal band while the delta-sigma structure shown in At this time, K is a constant of the modulator input and M is the modulus of the modulator adder. Now, mash type delta-sigma modulator will be described. The mash structure where a stable first order delta-sigma structure is cascaded has a high-order noise-shaping characteristic and also allows an stable structure to be implemented. Most of conventional frequency synthesizers requires a multi-modulus dividing circuit since it uses a mash type modulator having a multi-bit output so that the above stability and a noise shaping effect of a high order can be satisfied. The present invention is contrived to solve the above problems and an object of the present invention is therefore to provide a structure of a delta-sigma fractional type divider by which an external input value and an output value of a delta-sigma modulator are added to modulate values of a swallow counter. In order to accomplish the above object, the present invention is characterized in that is comprises a delta-sigma modulator for receiving a clock signal and a first digital value to perform a delta-sigma modulation, the first digital value being used to program a fractional ratio frequency of a frequency synthesizer, a swallow adder group for receiving an output value of the delta-sigma modulator and a second digital value to add an integer dividing ratio of a swallow counter and the output value of the delta-sigma modulator, the second digital value being used to program an integer ratio frequency of the frequency synthesizer; a program register group for storing an output value of the swallow adder group; and a pulse swallow counter group having a dual modulus prescaler, a program counter and the swallow counter, for dividing an input frequency depending on the value stored by the program register group. Further, the program register group further comprises a swallow register for storing output value of the swallow adder group; and a main division register for storing the integer dividing ratio. The aforementioned aspects and other features of the present invention will be explained in the following description, taken in conjunction with the accompanying drawings, wherein: FIG. FIG. FIG. FIG. The present invention will be described in detail by way of a preferred embodiment with reference to accompanying drawings, in which like reference numerals are used to identify the same or similar parts. The modulator includes registers In the third order delta-sigma structure, a block for giving offset in order to obtain an exact frequency resolution of 5 KHz against an input frequency 9.84 MHz of a phase frequency detecter (hereinafter PFD) is added. As an adder of a delta sigma has a modulus of 2 The present invention can implement a structure in which frequency of the fractional ratio of the wide band can be mixed and the in-band noise can vary by maximum, by simply applying all the range of 3 bit width outputted from the mash-type structure shown in The pulse swallow counter group The program register group The swallow adder group In the frequency synthesizer of the present invention, an input frequency (f The pulse swallow counter group FIG. FIG. In the mash-type structure, a carry output of a first adder determines an average fractional value of the entire division N structure. Second and third adders take an average from an error period occurring at the first adder and then further disperse the noise as the order is higher to send the result to a high frequency region. Therefore, it could be seen that the frequency mixing of the fractional ratio can be found by monitoring swallow control of the first order modulator. As shown in FIG. Through the above equation, the driving circuit having the dual modulus prescaler, the swallow counter and the program counter is constituted and the fractional ratio N can be obtained by a software method. This allows data of delta-sigma to be made by a software programming and data is updated by synchronizing it to the swallow register at a clock of f As an existing delta-sigma fractional type divider requires a multi-modulus dividing circuit, the divider is complicated and is difficult to design in order to control the dividing circuit using multi-bit. As mentioned above, however, the present invention modulates the values of the swallow counter by adding an external input value to the output value of the delta-sigma modulator. Therefore, the present invention can obtain an effect of a delta-sigma mode while having a wide-band frequency mixing capability. More particularly, the present invention has the following advantages while using an existing mash-type delta-sigma modulator. First, the design can be simplified by simply applying multi-bit outputs of the modulator to the pulse swallow counter used in a integer type division mode. Second, an existing pulse swallow counter can be used as the fractional type frequency synthesizer by controlling it in software, and Third, the spur of an oscillator can be reduced by maximum using the multi-bit output range of the mash type delta-sigma while having an precise frequency resolution. The present invention has been described with reference to a particular embodiment in connection with a particular application. Those having ordinary skill in the art and access to the teachings of the present invention will recognize additional modifications and applications within the scope thereof. It is therefore intended by the appended claims to cover any and all such applications, modifications, and embodiments within the scope of the present invention. Patent Citations
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