|Publication number||USRE40532 E1|
|Application number||US 11/034,444|
|Publication date||Oct 7, 2008|
|Filing date||Jan 11, 2005|
|Priority date||Jul 22, 2002|
|Also published as||CN1249808C, CN1503352A, CN101197326A, DE10328577A1, DE10328577B4, US6734063, US20040014280|
|Publication number||034444, 11034444, US RE40532 E1, US RE40532E1, US-E1-RE40532, USRE40532 E1, USRE40532E1|
|Inventors||Josef Willer, Franz Hofmann, Armin Kohlhase, Christoph Ludwig|
|Original Assignee||Qimonda Flash Gmbh|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (4), Classifications (15), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention lies in the field of electrically writable and erasable non-volatile flash memories comprising NROM-type memory cells preferably arranged in a virtual-ground NOR array.
Extremely small non-volatile memory cells are required for very large-scale integration densities in multimedia applications. However, while the minimum feature size, which is determined by lithography, continues to decrease, other parameters can no longer be scaled accordingly.
NROM-type memory cells are described in B. Eitan et al., “NROM: A novel localized trapping, 2-Bit nonvolatile memory cell”, IEEE Electron Device Letters 21, 543-545 (2000). Currently, NROM cells are fabricated as planar-type MOS transistors using a triple layer of oxide-nitride-oxide both as gate dielectric and as memory or programming layer. The intermediate nitride layer is used as a storage layer for trapping charge carriers, preferably electrons. Due to the specific properties of the used materials, typical source/drain voltages of 4 V to 5 V are necessary during program and erase operations.
At these comparatively high voltages, a punch-through occurs that impedes further scaling down of transistor channel lengths to values below 200 nm. Punching is supposed to take place between the n+-junctions of the source/drain regions through the semiconductor material below the channel region. Recent research in the physics of semiconductor devices demonstrated a superior punching behavior as well as an improvement of short channel properties when the channel is confined below by a buried oxide layer at a certain distance from the gate electrode.
MOSFETs on SOI substrates are described in the book by Jean-Pierre Colinge, “Silicon-on-insulator Technology: Materials to VLSI”, 2nd ed., Kluwer Academic Publishers, Dordrecht 1997, Chapter 5: “The SOI MOSFET”. The vertical extension of the channel region of SOI MOSFETs is limited by the insulating layer of the SOI substrate. The channel is partially or fully depleted, depending on the thickness of the channel region, which determines, inter alia, whether the space-charge regions adjacent to the gate-oxide and adjacent to the insulating layer are separated or join each other. The SOI MOSFET is completely electrically insulated towards the bulk substrate, unless there is a via provided through the insulating layer so that the bulk substrate can be electrically contacted from the upper surface.
At the 3rd European Workshop on Ultimate Integration of Silicon (ULIS 2002), Munich 2002, Thomas Skotnicki presented a NANO CMOS with 16 nm gate length. This type of transistor structure provides a backside channel isolation that is essentially confined to the channel region and is formed by removing an about 15 nm thick epitaxially grown SiGe layer and substituting it with electrically insulating material. The vertical dimension of the undoped and fully depleted channel is comparable to state of the art SOI MOSFETs. The heavily doped source and drain regions extend below the insulating layer level and are provided with LDD (lightly doped drain) regions as channel junctions. The channel structure is called SON, Silicon On Nothing.
It is accordingly an object of the invention to provide a non-volatile memory cell and a fabrication method which overcome the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provide for a SONOS-type transistor memory cell having a minimum cross-sectional area of the active channel, at the same time allowing for an at least partial depletion of the channel region, and a method of producing such a memory cell and memory cell array.
It is a further object of the invention to disclose a method of fabricating NROM memory cells without using SOI substrates.
It is a yet a further object to provide an isolation of the memory cell that is self-aligned to the word line and suitable for an array of memory cells.
It is still a further object of the invention to provide an isolated channel transistor memory cell that can be arranged in a virtual-ground array, and a method of producing such a memory cell and memory cell array.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method of producing a non-volatile memory cell having a semiconductor structure (a semiconductor body or a semiconductor layer on a substrate); buried bit lines formed at the surface of the semiconductor structure and conductor strips on the surface applied to the bit lines; a source region and a drain region each connected by one of the bit lines; a gate dielectric formed on the surface at least between the source region and the drain region; a gate electrode disposed on the gate dielectric; and a word line electrically connected to the gate electrode, the word line crossing the bit lines and being electrically insulated from the bit lines.
The method comprises the following steps:
The NROM cell according to this invention is arranged at the surface of a semiconductor body or semiconductor layer supplied with electrically insulating regions extending vertically with respect to this surface straight down into the semiconductor body or semiconductor layer between bit lines and on both sides of a corresponding word line provided for addressing the memory cell, the electrically insulating regions being arranged self-aligned to the word line and possibly also self-aligned to the bit lines and extending at least to a lower boundary level of the source region and the drain region. The electrically insulating regions preferably comprise an undercut region or buried layer underneath the channel region that is situated between the regions of source and drain. Punching of the transistor is avoided or at least impeded by means of the electrically insulating regions.
The structure is produced by anisotropically etching between the word lines and bit lines after word line delineation at least to the level of the lower junctions of the source/drain regions and preferably by isotropically underetching the channel region of the transistor. This etching process takes place from both sides of the word line and is performed self-aligned to the word line. The etch holes and eventually the undercut are filled with the electrically insulating material. The gate reoxidation step can be used to grow a thermal oxide around the transistor body and to passivate the semiconductor surface. Additionally, boron dopant or another p-dopant species can be implanted for improved electrical insulation beneath the electrically insulating material filling the undercut.
A preferred embodiment comprises a deposition of a CVD oxide in combination with a dielectric material of a small value of the relative dielectric constant into the space between neighboring word lines.
The method is applicable to future memory devices appertaining to lithography generations with a word line half pitch of about 90 nm and less.
The method according to the invention of producing a non-volatile memory cell comprises the following steps: A storage layer is applied on a surface of a semiconductor body or semiconductor layer, and a layer provided for a gate electrode is applied on this storage layer. In the regions provided for the bit lines, openings are etched in the gate electrode layer and used to implant a dopant to form buried bit lines comprising regions for source and drain. Bit line stacks are applied on the buried bit lines to reduce the electrical resistance of the bit lines and are covered with an electrically insulating material. A word line crossing the bit lines and electrically connected to the gate electrode is applied and structured together with the gate electrode to form a word line stack. A number of bit lines arranged in parallel and word lines crossing there bit lines can be applied in the described manner to form a whole cell array of a memory device.
The word line stack is used as a mask to etch the semiconductor material on both sides of the world line, first anisotropically and, in a preferred embodiment, subsequently isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the storage layer. The undercut is filled with an electrically insulating material, particularly oxide, to form an insulating buried layer, having a maximum thickness, i.e., a maximum dimension in the direction orthogonal to the surface of the semiconductor body or semiconductor layer, of at least 20 nm, in some embodiments more than 100 nm, underneath the channel region.
The source/drain regions are preferably of n-type conductivity, whereas the channel is of p-type conductivity. The channel is preferably doped at a density of at least 1017 cm−3. The threshold voltage of the cell transistor can be set to values between 0.5 V and 2.0 V in the erased state, and can be adjusted to typically about 1.5 V by a suitable choice of the device parameters.
An accomplishment of the inventive method is to provide a non-volatile cell transistor with isolated channel without using an SOI substrate. It provides means to reduce the effective channel length of the cell device, especially with the aim of further scaling down the device dimensions. An electrical insulation between the source region and the drain region laterally or immediately beneath the channel impedes a punch-through in this area.
With the above and other objects in view there is also provided, in accordance with the invention, a non-volatile memory cell, comprising:
In accordance with an added feature of the invention, the electrically insulating undercut region extends continuously across the word line.
In accordance with an additional feature of the invention, the electrically insulating undercut region has a maximum thickness in a direction orthogonal to the surface of the semiconductor structure of at least 20 nm or of at least 100 nm.
In accordance with a concomitant feature of the invention, there is provided a channel region between the source region and the drain region. The channel region has a preferred doping density of at least 1017 cm−3.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a non-volatile memory cell and method of fabricating such a memory cell, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
In the following, a detailed description of the preferred embodiments of the invention will be given referring to the steps of preferred methods of manufacture. In any of the embodiments, the fabrication process can start with steps that are known in themselves from the fabrication process of memory cells according to the state of the art. These steps may comprise depositing layers of pad oxide and/or pad nitride grown on a surface of a semiconductor body or semiconductor layer, especially a p-doped semiconductor wafer. All the known steps to form oxide-filled shallow trench isolations can be added, including the application of lithography for trench definition, and planarization. Standard implants may be carried out to form wells in the periphery region provided for the CMOS control integrated circuits.
Next, the storage layer, preferably an ONO-layer (oxide-nitride-oxide layer), is grown on a surface of the semiconductor body or semiconductor layer. A lithography step can follow to remove the storage layer in the periphery and to replace it there by one or more different gate oxides. On the storage layer, an electrically conductive layer is deposited, which is provided for the gate electrode to be produced.
Referring now to the figures of the drawing in detail and first, particularly, to
Bit line conductor strips 6 to reduce the electrical resistance are deposited on the surface of the buried bit lines 5. The bit line conductor strips 6 can be formed of CoSi and/or polysilicon. When using a silicide, the bit line conductor strips 6 can partly be merged into the semiconductor material of the semiconductor body 1 as shown in FIG. 1B. Bit line cover layers 7 are applied on the bit line conductor strips 6. These cover layers 7 can be formed by depositing TEOS (tetraethylorthosilicate) or by growing silicon oxide on top of the bit line conductor strips 6, if they were made of polysilicon. The cover layers 7 are planarized, and the hard mask layer of nitride is removed.
Next, a layer sequence is deposited that includes at least one word line layer provided for the formation of word lines. In the exemplary embodiment of
As shown in the cross-sections of
After this anisotropic etching, the sidewalls of the bit line stacks and the word line stacks can be covered by a thin nitride cover 11. Alternatively, cover 11 can be a thin oxide layer resulting from a word line reoxidation step. The cover 11 is removed from the surface of the semiconductor body 1 at least at the bottom of the etched holes. In a preferred embodiment, the etching process continues isotropically by using either a dry etchant such as SF6 or, in the embodiment of
The maximum thickness 19, i.e., the maximum dimension in the direction orthogonal to the surface of the semiconductor body or semiconductor layer, of the undercut is usually present in the elongation of the plane of the lateral flanks of the word line stack, as indicated in the FIGS.
The upper limit of the area of cover 11 in
The insulating layer in the undercut beneath the channel region 17 is formed with a maximum thickness 19 of at least 100 nm in the embodiment shown in FIG. 5A. In the embodiment shown in
It will be understood that variations and deviations from the exemplary embodiments of the disclosed method due to special requirements of the manufactured memory devices lie within the scope of this invention.
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|1||*||Colinge, J.P.: "Silicon-on-insulator Technology: Materials to VLSI", Kluwer Academic Publishers, 2<SUP>nd </SUP>edition, 1997, pp. 123-192.|
|2||*||Eitan, B. et al.: "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell", IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.|
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|U.S. Classification||438/257, 257/E21.66, 257/390, 257/391|
|International Classification||H01L27/112, H01L29/94, H01L21/336, H01L21/8247, H01L21/8239, H01L27/115, H01L21/8246|
|Cooperative Classification||H01L27/11568, H01L27/115|
|European Classification||H01L27/115, H01L27/115G4|
|Sep 24, 2007||AS||Assignment|
Owner name: QIMONDA FLASH GMBH, GERMANY
Free format text: CHANGE OF NAME;ASSIGNOR:INFINEON TECHNOLOGIES FLASH GMBH & CO. KG;REEL/FRAME:019883/0635
Effective date: 20060908
|Jul 1, 2010||AS||Assignment|
Owner name: QIMONDA AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA FLASH GMBH;REEL/FRAME:024629/0532
Effective date: 20080808
Owner name: QIMONDA AG,GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA FLASH GMBH;REEL/FRAME:024629/0532
Effective date: 20080808
|Nov 7, 2011||FPAY||Fee payment|
Year of fee payment: 8
|May 8, 2015||AS||Assignment|
Owner name: INFINEON TECHNOLOGIES AG, GERMANY
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:QIMONDA AG;REEL/FRAME:035623/0001
Effective date: 20141009