|Publication number||USRE40567 E1|
|Application number||US 10/080,958|
|Publication date||Nov 11, 2008|
|Filing date||Feb 21, 2002|
|Priority date||Aug 19, 1996|
|Also published as||US5742543, WO1998008226A1|
|Publication number||080958, 10080958, US RE40567 E1, US RE40567E1, US-E1-RE40567, USRE40567 E1, USRE40567E1|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (29), Classifications (15), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation of application Ser. No. 08/699,490, filed Aug. 19, 1996, now abandoned.
The present invention relates generally to memory devices and more particularly to a nonvolatile memory device having a page mode of operation.
Nonvolatile memory devices such as Electrically Programmable Read Only Memories (“EPROMs”), Electrically Erasable Programmable Read Only Memories (“E2PROMs”), and flash EEPROMs include an array of nonvolatile memory cells and supporting periphery circuitry for accessing the array. A nonvolatile memory cell typically behaves like a field effect transistor and includes a select (or control) gate that controls the reading and writing of data to the memory cell and a floating gate that traps charge to alter the datum or data stored by the memory cell.
As charge is added to the floating gate of a memory cell, the threshold voltage Vt of the memory cell increases, and the memory cell drain current ID (“cell current”) decreases. The memory cell threshold voltage Vt is related to the memory cell drain current ID by the expression:
wherein Gm is the transconductance of the memory cell; VG is the memory cell gate voltage; VD is the memory cell drain voltage; and Vt is the memory cell threshold voltage.
Given this relationship, there are a number of prior art methods for sensing the amount of charge stored on of the floating gate of the memory cell, including the following:
Once sensed, the amount of charge determined to be stored on the floating gate is decoded to correspond to one of n possible states, n being two or more, and the binary representation (log2n) of the determined state is output. One disadvantage of the above-described methods, all of which require an active cell current, is that a relatively large amount of current is required for sensing each cell, which reduces the maximum number of cells that may be sensed in parallel.
As shown, the prior art sensing system 5 detects the amount of cell drain current ID that results from applying a read voltage VG to the select gate SG of memory cell 10. Depending upon the amount of charge stored on the floating gate FG of memory cell 10, the cell current ID may vary anywhere from zero to approximately 100 microamperes when the read voltage VG is applied to select gate SG.
The select gate SG of memory cell 10 is coupled to a wordline (not shown) to receive the read voltage VG, the drain of memory cell 10 is coupled to a bitline (not shown) to which sensing system 5 is coupled to detect the strength of the cell current ID, and the source of memory cell 10 is coupled to a ground potential VSS to give rise to the cell current ID that flows from the drain to the source as shown. Thus, memory cell 10 operates as a pull-down device.
A corresponding pull-up device is found in column load circuit 19. Column load circuit 19 is shown as including a transistor 20 that is biased to operate as a pull up device by a gate voltage Vbias. A drain bias circuit 12 is coupled between the drain D of memory cell 10 and column load circuit 19 to ensure that the drain D of memory cell 10 does not drop below a predetermined voltage (e.g. approximately one volt). Drain bias circuit 12 is shown as including a cascode transistor 15 and feedback circuitry 17. Feedback circuitry 17 provides a necessary voltage to the gate of transistor 15 such that the drain D of memory cell 10 does not drop below the predetermined voltage.
Once the read voltage VG is applied to the select gate SG of memory cell 10, the amount of charge trapped on floating gate FG determines the strength of the cell current ID and the strength of the pull-down provided by memory cell 10. Typically, if the memory cell 10 is erased, memory cell 10 acts as a strong pull-down device to overcome the pull-up provided by column load circuit 19 such that the negative input of a differential sense amplifier 25 is discharged towards ground. Sense amplifier 25 compares the voltage at its negative input to the voltage at its positive input, which is supplied by a reference circuit 30. According to common prior techniques, reference circuit 30 includes a reference cell (not shown) that has its floating gate charged to a predetermined level coupled to a drain bias circuit and column load circuit identical to those shown of sensing system 5.
Using the sensing scheme embodied by sensing system 5 requires a relatively large amount of current to read memory cell 10. For example, each of the memory cell 10, the drain bias circuit 12, and the sense amplifier 25 require current for operation and therefore result in power consumption. The amount of power consumption required by these components of sensing system 5 results in the ability of sensing system 5 to sense relatively few memory cells (e.g. 16 or 32) in parallel.
Therefore, it is one object of the present invention to provide a method for sensing more nonvolatile memory cells in parallel than previously allowed by typical prior art methods.
It is a further object of the present invention to use the method to provide a page mode of operation for a nonvolatile memory device.
It is a further object of the present invention to provide a method for sensing the cell threshold of memory cell rather than the cell current of the memory cell.
It is a further object of the present invention to provide a method for sensing a memory cell without using a drain bias circuit or a differential sense amplifier.
A method for determining data stored by a memory cell is described. The memory cell has a select gate coupled to a wordline, a first electrode coupled to a bitline, and a second electrode coupled to a conductor. The method comprises: floating the bitline; applying a first voltage to the wordline; applying a second voltage to the conductor such that the bitline is set to a third voltage that is equal to the first voltage minus a threshold voltage of the memory cell; and sensing the third voltage to determine the data stored by the memory cell. For one embodiment, the memory cell is a nonvolatile memory cell.
Other objects, features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description which follows below.
The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
A method and associated apparatus are described herein that provide for sensing the data stored by an entire wordline of a memory device in parallel without the excessive consumption of current. The advantages of the present described method and apparatus are provided, in part, by performing read operations of the memory cells without requiring an active cell current ID (i.e. approximately zero DC cell current). Because no cell current is required to sense the data stored by the nonvolatile memory, the amount of power required to read each cell is reduced sufficiently to allow for an entire selected wordline of memory cells to be read simultaneously. Wherein the amount of time required to form a single read operation using the described methods may, under some circumstances, be longer than the amount of time required to read a memory cell using some prior at schemes, the fact that many more memory cells can be sensed in parallel allows the sensing time to be amortized over many more cells so that the average amount of time to read each cell is significantly reduced and performance is increased.
The sensing system that operates according to present embodiments, as described with respect to
Applying the source voltage VS to memory cell 35 actually results in the functions of the “drain” and “source” of memory cell 35 reversing such that what was formerly the “drain” of memory cell 35 now operates as the “source” of memory cell 35, and vice versa.
The method and system shown in
When memory cell 35 is a flash memory cell, the cell threshold voltage Vt determines the cell current ID. Therefore, in order to reduce the variability of the sensed data stored in memory cells, it is preferable to sense the cell threshold voltage Vt rather than the cell current ID. Additionally, many of a flash memory cell's parameters rely on the cell threshold voltage Vt, not the cell current ID. For instance, the programming of a flash memory cell is directly proportional to the cell threshold voltage Vt, not the cell current ID. In addition, disturb mechanisms (charge loss and charge gain) are related to the cell threshold voltage Vt. Therefore, it is preferable to sense the cell threshold voltage Vt rather than the cell current ID.
The scheme illustrated in
According to the present embodiments, both the read voltage VG applied to the wordline 40 and the source voltage VS are selected in view of the operating characteristics of the memory cell 35. Specifically, for the example wherein memory cell 35 is a flash memory cell, the range of possible cell threshold voltages Vt provides a programming window that may be subdivided into a number of distinct states. The number of states into which the programming window is divided determines the number of bits stored by the memory cell 35. For example, if a programming window is subdivided into only two states, memory cell 35 is capable of storing only one bit of data. Alternatively, if a programming window is subdivided into eight distinct states, memory cell 35 is capable of storing 3 bits of data.
According to the present embodiments, the read voltage VG is selected to be greater than the maximum threshold voltage Vt,max. The source voltage VS is selected to be equal to (Vt,max−Vt,min), which is the maximum possible swing of the bitline. When these constant voltages are applied to wordline 40 and the source S of a memory cell 35, bitline 45 coupled to the drain D of memory cell 35 will eventually achieve a DC value proportional to (VG−Vt). For one embodiment, the read voltage VG is approximately 5.5 volts and the source voltage VS is approximately 3.0 volts.
Memory cell carry 75 of
At process block 165, the read voltage VG is applied to the selected wordline, and deselected wordlines are grounded to prevent the switching on of the memory cells attached to the deselected wordlines. Again, the read voltage VG that is applied to the selected wordline is selected to be greater than the maximum threshold voltage Vt,max obtainable by a memory cell of memory cell array 75.
At process block 170, a source voltage VS is applied to all the sources of all the memory cells in memory array 75 by coupling the source voltage VS to the source straps of the memory cell array. For other layouts of memory cell array 75, the source voltage VS may not necessarily be applied to all the sources of the memory cells; however, the present scheme will work so long as all of the memory cells of the memory cell array 75 that are to be read have their sources set to the appropriate source voltage VS.
A predetermined period of time is allowed to elapse so that the bitlines coupled to the selected memory cells are allowed to achieve a steady state voltage proportional to (VG−Vt). Each of bitlines 120-122 may have a different voltage as determined by the threshold voltages Vt of each of memory cells 101-103. At process block 175 bitline voltages for each of bitlines 120-122 of the memory cell array 75 are sensed. The bitlines may be sensed in parallel or subsets of the bitlines may be sensed sequentially. For example, given 1024 bitlines, the periphery circuitry 80 of the memory device 70 may be configured to sense the voltages of all the bitlines in parallel or to sense a subset of the bitlines at a time (e.g. sixteen). So long as the read voltage VG and the source voltage VS are applied to the memory cells of the selected wordline, the bitline voltages on bitlines 120-122 will maintain a DC value proportional to (VG−Vt).
Providing sufficient time to allow bitlines 120-122 to achieve a DC voltage may require a longer period of time than normally required by prior art sensing schemes; however, the fact that all of the memory cells of an entire wordline may be sensed in parallel allows the time to be amortized over all of the memory cells of a wordline such that the average time to access the data of each memory cell is significantly reduced over the prior art. Under this scheme no drain bias circuit is required because no cell current is required. Similarly, a differential sense amplifier is also not required. Because, the value of the read voltage VG and the maximum swing of the threshold voltage Vt are known, an analog to digital converter may be used to convert the voltage of a bitline into a digital value, therefore not requiring a sense amplifier.
Periphery circuitry 80 is also shown as including an optional control engine 200 that includes a read algorithm “R” 201 and a write algorithm “W” 202 that control engine 200 uses to control the periphery circuitry 80 for accessing the memory cell array 75. Control engine 200 may alternatively be provided externally to the memory device 70. Control engine 200 is coupled to receive the address and control signals such that it can appropriately control the voltage regulation circuitry 205, voltage switches 210, and the row and column decoders 215.
The voltage regulation circuitry 205 is coupled to receive the external supply voltages VCC, VPP, and VSS. Typically, values of VCC and VPP are 5 volts and 12 volts, respectively. However, for some embodiments VCC and VPP may be the same voltage, (e.g. 5.0 volts or 3.3 volts). The voltage regulation circuitry 205 may include charge pumps, DC-to-DC converters, and/or voltage dividers for producing the read voltage VG and the source voltage VS.
The voltage switches 210 are coupled to the voltage regulation circuitry 205 and to the wordlines, bitlines, and source straps of memory cell array 75. Voltage switches 210 selectively provides the desired voltages (e.g. source voltage VS) to the memory cell array in response to control signals provided by the control engine 200.
The row decoders of row and column decoders 215 are coupled to the voltage switches 210 for receiving the read voltage VG and supplying the read voltage VG to a wordline of memory cell array 75 indicated by the address transmitted received from the address lines ADDR. As previously mentioned, column decoders are optional and may be used merely to multiplex sensing circuitry 220 to sense specific subsets of bitlines 120-122 of the memory cell array 75. If no column decoders are provided, sensing circuitry 220 will sense all of the bitlines of the memory cell array 75 in parallel.
Sensing circuitry 220 is shown as including analog to digital converter “ADC” 221 that translates the voltages sensed at bitlines 120-122 to digital values. Sensing circuitry 220 may include latches for storing the sensed voltages such that all of the voltages on bitlines 120-122 may be dumped into the latches and sequentially output in smaller subsets to data bus 85.
The memory device architecture shown in
In the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense.
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|U.S. Classification||365/185.21, 365/185.26, 365/185.12, 365/185.24, 365/185.18|
|International Classification||G11C11/34, G11C16/26, G11C7/12, G11C7/00|
|Cooperative Classification||G11C7/00, G11C7/12, G11C16/26|
|European Classification||G11C7/00, G11C16/26, G11C7/12|