|Publication number||USRE40579 E1|
|Application number||US 09/694,051|
|Publication date||Nov 25, 2008|
|Filing date||Oct 20, 2000|
|Priority date||Nov 30, 1993|
|Publication number||09694051, 694051, US RE40579 E1, US RE40579E1, US-E1-RE40579, USRE40579 E1, USRE40579E1|
|Inventors||Frank Randolph Bryant, Tsiu Chiu Chan|
|Original Assignee||Stmicroelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Classifications (7), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation in part of an application entitled “METHOD OF MAKING TRANSISTOR DEVICES IN AN SRAM CELL”, Ser. No. 08/390,117, filing date Feb. 17, 1995 now abandoned, which is a divisional of Ser. No. 08/159,462 filed Nov. 30, 1993, now U.S. Pat. No. 5,426,065.
Applicant incorporates said application Ser. No. 08/159,462 by reference herein and claims the benefit of said application for all purposes pursuant to 37 C. F. R. § 1.78.
1. Field of the Invention
The present invention relates to integrated the circuit devices and more specifically to field effect transistors (FET) for use in integrated circuits.
2. Description of the Prior Art
Memories are devices that respond to operational orders, usually from a central processing unit. Memories may store large quantities of information in a digital format. In a memory system or unit, addresses are used to access the contents of the memory unit. A binary digit, also called a bit, is the basic information element stored in a memory unit. The smallest subdivision of a memory unit into which a bit of information can be stored is called a memory cell. A memory on a chip is physically arranged as a two-dimensional array of cells, wherein rows of cells are connected by row lines, also called word lines. A column of cells are connected by a column line, also called a bit line. These memory cells may be constructed by various configurations of transistors and/or capacitors.
A semiconductor memory is a memory that is implemented in a semiconductor material such as silicon. Metal-oxide semiconductor (MOS) memories are common in the industry. A number of different types of MOS memories exist, such as a dynamic random access memory (DRAM) which is a metal oxide semiconductor memory that stores a bit of information as a charge on a capacitor, and a static random access memory (SRAM) which includes a bistable flipflop circuit requiring only a DC voltage applied to it to retain its memory. Normally, an SRAM contains four transistors plus either two transistors or two polysilicon load resistors as pull-up devices.
SRAMs have a disadvantage over a memory such as a DRAM. The components in an SRAM typically require the SRAM to have a larger basic cell than a DRAM. In SRAM memory cells, the data transfer gate transistor to pull-down transistor ON resistance ratio is typically required to be about 2.6× or greater to provide stability to the memory cell. Currently, the width of the pull-down transistor is required to be larger than the width of the transfer gate transistor to achieve the ratio requirement. This requirement places limitations on how small the memory cell may be made. Therefore, it would be desirable to have a transistor structure that would allow for a reduction in the area that a memory cell requires.
An SRAM memory cell having first and second transfer gate transistors. The first transfer gate transistor includes a first source/drain connected to a bit line and the second transfer gate transistor has a first source/drain connected to a complement bit line. Each transfer gate transistor has a gate connected to a word line. The SRAM memory cell also includes first and second pull-down transistors configured as a storage latch. The first pull-down transistor has a first source/drain connected to a second source/drain of said first transfer gate transistor; the second pull-down transistor has a first source/drain connected to a second source/drain of said second transfer gate transistor. Both first and second pull-down transistors have a second source/drain connected to a power supply voltage node. The first and second transfer gate transistors each include a gate oxide layer having a first thickness, and the first and second pull-down transistors each include a gate oxide layer having a second thickness, wherein the first thickness is different from the second thickness.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections and layouts of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention.
Transistor TG1 has a source/drain connected to bit line A, and transistor TG2 has a source/drain connected to bit line B. Bit line B is a complement of bit line A. The gates of transistors TG1 and TG2 are connected to word line C. As can be seen, transistors PD1 and PD2 are connected in a cross-coupled configuration. In addition, the source/drain of transistor TG1 and transistor PD1 is connected to one end of resistor R1 while the source/drain of transistor PD2 and transistor TG2 are connected to one end of resistor R2. The other ends of resistors R1 and R2 are connected to power supply voltage VCC while transistors PD1 and PD2 each have a source/drain connected to power supply voltage VSS.
Typically, the power supply voltage VCC is at a higher voltage than power supply voltage VSS. In a typical SRAM cell, transistors PD1 and PD2 typically have a width of 2.1μ and a length of 0.7μ. Transistors PG1 and PG2 TG1 and TG2 typically have a width of 0.9μ and a length of 0.8μ.
Referring now to
As can be seen in
Transfer gate transistor 28 in
Thereafter, the gate of pull-down transistor 28 is formed as illustrated in FIG. 3E. The gate of pull-down transistor 28 includes gate oxide layer 48 and polysilicon layer 50. Source/drains 52 also are implanted in substrate 30. Source/drains 52 include LDDs 54, which are again defined using sidewall oxide spacers 56. The thickness of gate oxide 32 is greater than the thickness of gate oxide 48. This type of processing is employed to create transfer gate transistors and pull-down transistors with different gate oxide thicknesses, which allows for a reduction in the width of pull-down transistors in an SRAM cell.
Although the depicted embodiment illustrates completely etching away the gate oxide of pull-down transistor 28, then producing a gate oxide of the desired thickness, other methods of producing different gate oxides may be employed according to the present invention. For example, a gate oxide layer may be grown for transfer gate transistor 28 first, and then an additional gate oxide layer can be grown on both pull-down transistor 26 and transfer gate transistor 28 to produce gate oxide layers of different thicknesses for each of the transistors. Transfer gate transistor 28 is completely masked from processing after completion, and remains in the form depicted in
According to the present invention, a reduced width pull-down transistor dimension may be employed by adjusting the ratio of the gate oxide thickness between the transfer gate transistors and the pull-down transistors in the SRAM cell. The needed thicknesses of the two gate oxides may be selected using the following equation:
where RATIO is the desired ratio of the transfer gate transistor and the pull-down transistor, TOXtg is the gate oxide thickness of the transfer gate transistor, TOXpd is the gate oxide thickness of the pull-down transistor, Wpd is the width of the pull-down transistor, Lpd is the length of the pull-down transistor, Wtg is the width of the transfer gate transistor, Ltg is the length of the transfer gate transistor, Vcc is the upper power supply voltage, Vttg is the threshold voltage of the transfer gate transistor, and Vtpd is the threshold voltage of the pull-down transistor.
In the depicted example, RATIO is 2.6, VCC is equal to 3.3 volts, Vttg is 0.9 volts with a back bias, and Vtpd is equal to 0.7 volts. If 0.5μ feature design rules are utilized (L equal 0.5μ, W equal 0.6μ), the pull-down transistor width is 1.56μ. If the pull-down gate oxide thickness is 120 Å, a 36% reduction in pull-down transistor width (1.0μ feature), will require a 134 Å transfer gate oxide thickness. A 50% reduction in pull-down transistor width (0.8μ feature) requires a 165 Å transfer gate oxide thickness. By reducing the width (Wpd) of the pull-down transistor, the overall area of SRAM cell may be reduced.
Thus, the present invention provides a method and structure for reducing the overall cell area of a memory cell. The present invention provides an ability to reduce the area of a memory cell by allowing the widths of the pull-down transistors to be reduced. The reduction in width is accomplished according to the present invention by selecting different gate oxide thicknesses for the pull-down transistor and the transfer gate transistor to maintain the desired ratio.
Although the depicted embodiment defines specific numbers for ratios, widths, lengths, in other parameters may be utilized by those of ordinary skill in the art following this disclosure. In addition, the different gate oxide thicknesses for transistors in the SRAM memory cell may be applied to other types of memory cells in which widths or lengths of transistors can affect the area that a cell requires.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4866002 *||Mar 21, 1988||Sep 12, 1989||Fuji Photo Film Co., Ltd.||Complementary insulated-gate field effect transistor integrated circuit and manufacturing method thereof|
|US5285096 *||Sep 11, 1992||Feb 8, 1994||Nec Corporation||High stability static memory device having metal-oxide semiconductor field-effect transistors|
|US5373170 *||Mar 15, 1993||Dec 13, 1994||Motorola Inc.||Semiconductor memory device having a compact symmetrical layout|
|U.S. Classification||257/392, 257/904, 257/903, 257/379|
|International Classification||H01L29/76, H01L29/94, H01L31/00|