|Publication number||USRE40660 E1|
|Application number||US 11/652,469|
|Publication date||Mar 10, 2009|
|Filing date||Jan 10, 2007|
|Priority date||Jul 31, 2001|
|Also published as||US6842816, US20040260858|
|Publication number||11652469, 652469, US RE40660 E1, US RE40660E1, US-E1-RE40660, USRE40660 E1, USRE40660E1|
|Inventors||Donald R. Primrose|
|Original Assignee||Primrose Donald R|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Classifications (7), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a reissue application for U.S. Pat. No. 6,842,816 issued on Jan. 11, 2005.
1. Field of the Invention
The present invention relates to the field of electronic circuits. More specifically, the present invention relates to a configurable glueless microprocessor interface.
2. Background Information
The Internet may be considered a global network of networks interconnected through countless numbers of network switching devices. These switching devices typically direct and/or route data from transmitting devices logically located within a first datacom/telecom network to receiving devices logically located within one or more additional datacom/telecom networks, regardless of their respective geographic locations. The Internet has undergone remarkable growth in recent years. Whether this rapid growth has resulted in the advancement of network processing technologies, or advancements in network processing technologies have in turn spurred the Internet's rapid growth, the fact remains that modern day network switching devices are continually being called upon to direct greater amounts of increasingly complex data. Accordingly, it is becoming increasingly important that network communications be carried efficiently at high speed across a wide variety of local, regional, and wide area networks, including those comprising the Internet.
When switching or routing network traffic, a need often arises to divert a portion of the data packets being routed/switched onto a particular routing path to perform additional processing (or to drop the packets), or to insert additional packets into the packet streams being received off a routing path. To provide the desired packet diversion and/or insertion functionality, one or more companion processors (also referred to as host processors) are sometimes provided. Basic implementations of these switches/routers typically route all packets through the host processor(s) to enable the host processor(s) to selectively divert some of the packets of selected ones of the various routing paths (for additional processing or dropping the packets), or to selectively inject additional packets into the packet streams of selected ones of the various routing paths. In other more advanced implementations, additional switching/routing resources (such as programmable switching/routing tables) may be employed to facilitate routing of some of the packets of selected ones of the routing paths to the host processor(s) for “processing” (“diversion”), and routing of the packets injected by the host processor(s) onto the routing paths of their selection (“insertion”). In addition to facilitating the diversion and/or insertion of packets, the host interface also allows the host processor to control the operational mode of the device, query the operational status of the device, and gain access to statistics, such as byte and packet counters, required by certain networking standards.
Host processors are often interfaced with network switching devices through various amounts of glue logic. Manufacturers and system integrators choose to utilize certain microprocessor architectures depending upon the specific functionality and features desired. For example, a first type of processor architecture (commonly available from Intel Corp., of Santa Clara, Calif.) uses a separate address and data bus for memory addressing, whereas a second type of processor architecture (commonly available from Motorola Inc., of Schaumburg, Ill.), uses a multiplexed address/data bus. A multiplexed address and data bus allows for a reduced pin count enabling a smaller component package size and therefore lower cost. The downside of a multiplexed address and data bus is that additional clock cycles are required to complete a transaction. For example, an address is typically driven onto the bus on a first clock edge, with the next clock edge signaling the beginning of one or more data phases in which data is to be transferred over the same bus. Separate address and data paths on the other hand dedicate bandwidth to each phase of the data transfer, speeding internal data handling, and resulting in higher system performance. Processors may also differ in the way they signal transactions. For example, certain types of processors utilize a transfer start indication signal in cooperation with a read/write signal to indicate the start of a read/write cycle, whereas other types of processors utilize separate read/write strobes to indicate the start of a read/write cycle.
Typically, network switching devices are designed to operate with host processors having a fixed architecture type. For example, if a network switch were designed to operate in cooperation with an Intel class processor functioning as a host processor, then simple substitution of a Motorola class host processor would not be possible without additional, and perhaps extensive glue logic being added. Accordingly, interoperability amongst processors and network switching devices is limited due to the proprietary signaling requirements of the various processors.
The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which:
The present invention includes a host control interface for use in interfacing an external host processor with internal control/status registers of an integrated circuit. In accordance with the teachings of the present invention, the control interface selectively couples the integrated circuit with an interchangeable one of a variety of host processor types. In one embodiment, the control interface supports processors having a multiplexed address/data port as well as processors having separate address and data ports. Similarly, in one embodiment, the control interface supports processors utilizing a transfer start indication signal in cooperation with a read/write signal, as well as processors utilizing separate read/write strobes. In the following description, various aspects of the present invention will be described. However, the present invention may be practiced with only some aspects of the present invention. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the present invention. Further, the description repeatedly uses the phrase “in one embodiment”, which ordinarily does not refer to the same embodiment, although it may.
As will be discussed in further detail below, host processor 102 represents one or more processors having an identified architecture type. In one embodiment, host processor 102 is identified as corresponding to one of a variety of architecture types including those that utilize a multiplexed address and data bus, those that utilize separate address and data buses, those that utilize a transfer start indication signal in cooperation with a read/write indicator, those that utilize separate read and write strobes, and those utilizing various combinations there between. In the illustrated embodiment of the invention, control interface 105 includes mode selection logic 107 to configure control interface 105 to operate in one of a plurality of operational modes based at least in part upon the identified architecture type of host processor 102. In the illustrated embodiment, control interface 105 further includes delay circuitry 109 to provide programmable write latencies based at least in part upon the operating characteristics of host processor 102.
As illustrated in
Delay circuitry 109A (as well as 109B) represents circuitry and/or logic to programmably delay transmission of signals from the host interface to the IC interface in order to interchangeably accommodate various timing requirements of a variety of processors.
In one embodiment, the amount of latency desired is determined based upon the architecture of host processor 102. For example, in processors utilizing a multiplexed address/data bus, address information is typically driven on the multiplexed bus during a first clock cycle and data is driven on the same bus for at least the following clock cycle. In such cases, it may be desirable to delay the address information one or more cycles so that it is driven on the address bus at the same time valid write data is driven on the data bus. In the illustrated embodiment, delay circuitry 109A and 109B may be programmed to provide zero latency up to a three-cycle delay, however other embodiments may provide a greater or fewer number of delay intervals. In one embodiment, delay circuitry 109A and 109B default to a latency that accounts for the slowest of potential host processor types that may likely be used (i.e. worst case scenario). In one embodiment, a default latency of three cycles is implemented. If a particular processor is capable of functioning with less latency than that stipulated by default, the processor may subsequently adjust the stored latency value(s) by writing a representative value to a particular configuration register provided by integrated circuit 100 or control interface 105 to set the above-mentioned latency control signal.
Reference is once again made to
Mode control signal 130 represents a mechanism through which control interface 105 may be programmed to operate in one of a plurality of operational modes in accordance with one of a plurality of signaling protocols and/or processor architectures. In one embodiment, mode control signal 130 represents two control signals implemented in the form of one or more independently programmable binary switches, such as “DIP” switches, that may be manually set to signal a selected one of a plurality of operating modes under which control interface 105 is to operate (e.g. based upon the constitution of processor 102). In an alternative embodiment, mode control signal 130 may be implemented in the form of one or more independently and automatically programmable data registers to cause control interface 105 to operate in a specified operating mode based upon an identified architecture type of processor 102. For example, in the event processor 102 is equipped with one or more connection pins that provide external devices with information identifying one or more aspects of the processor's architecture, mode control signals 130 may be adapted to decode such information and identify an operating mode for control interface 105 based upon that information.
In one embodiment of the invention, mode control signal 130 represents two control signals enabling four independently programmable operating modes for control interface 105. For example, a first control signal is used to select between a first operating mode whereby multiplexed address and data signals are received on host address/data bus 120, and a second operating mode whereby data is received on host address/data bus 120 and address signals are received on separate host address bus 122. Similarly, a second control signal is used to select between a third operating mode whereby a transfer start indicates is used in cooperation with a read/write indication to signify the start of either a read or a write transaction, and a fourth operating mode whereby separate read and write strobes are used to signal the start of a read/write transaction. In accordance with one embodiment of the invention, each mode control signal may be independently set or cleared based upon the architecture of processor 102.
The control interface described above may provide flexible and interchangeable interface functionality to a broad category of devices.
In one embodiment, optical components 182, optical-electrical components 184, support control electronics 185 and processor 102 are encased in a body (not shown) forming a singular optical networking module. In addition to being equipped to provide optical to electrical and electrical to optical conversions, clock and data recovery, and so forth, the integrated optical networking module is also equipped to provide data link and physical sub-layer processing on egress and ingress data selectively for a number of protocols. In one embodiment, processor 102 is interchangeably coupled to the optical networking module, and may be replaced by one or more additional processors of varying architecture types.
Thus, as can be seen from the above descriptions, a novel control interface having selectable operating modes to facilitate interchangeable operation with multiple host processor architectures has been described. While the present invention has been described in terms of the foregoing embodiments, those skilled in the art will recognize that the invention is not limited to those embodiments. The present invention may be practiced with modification and alteration within the spirit and scope of the appended claims. Thus, the description is to be regarded as illustrative instead of restrictive on the present invention.
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|U.S. Classification||710/305, 710/315|
|International Classification||G06F13/40, G06F13/14, G06F13/00|
|Feb 2, 2007||AS||Assignment|
Owner name: TRIQUINT SEMICONDUCTOR, INC., OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NETWORK ELEMENTS, INC.;REEL/FRAME:018849/0059
Effective date: 20041217
Owner name: NETWORK ELEMENTS, INC., OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PRIMROSE, DONALD R.;REEL/FRAME:018849/0051
Effective date: 20010731
Owner name: NULL NETWORKS LLC, NEVADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRIQUINT SEMICONDUCTOR, INC.;REEL/FRAME:018849/0091
Effective date: 20050908
|Jun 25, 2012||FPAY||Fee payment|
Year of fee payment: 8