US RE40710 E1 Abstract A data converter (
1) capable of reducing a size of the total implementation in a device is a processing apparatus that performs secret converting processing predetermined to input data with 64 bits, the data converter including a finite field polynomial cubing unit (10), data integrating units (11a) to (11d), (12) and (13), a first converter (14), a second converter (15), a data splitting unit (16), and a data integrating unit (17). The finite field polynomial cubing unit (10) performs cubing, on the 32 bits data, in the polynomial residue class ring with a value in the finite field GF (2^{8}) as a coefficient and respectively outputs data with 32 bits.Claims(16) 1. A data converter comprising:
a splittingan obtaining unit operable to split input data intoobtain a plurality of data blocks;
a conversion performing unit operable to perform conversion on each one of the plurality of data blocks, the conversion being based on an exponentiation to a predetermined exponent in a polynomial residue class ring with a value in a finite field GF (2
^{n}) as a coefficient, the n being a natural number, as a coefficient;and the exponentiation using a predetermined value as an exponent; and an output data generating unit operable to generate output data based on the plurality of data blocks converted by the conversion performing unit,
wherein the predetermined exponentvalue is a value that is 3 or larger and other than 2
^{m}, the m being an integer which is 1 or larger. 2. The data converter according to
a finite field multiplying unit operable to perform multiplication in the finite field GF (2
^{n}), wherein the conversion performing unit performs exponentiation using the finite field multiplying unit.
3. The data converter according to
wherein the conversion performing unit includes:
an adding subunit operable to add, in the polynomial residue class ring, a predetermined constant and each one of the plurality of data blocks split by the splitting unit,obtained by the obtaining unit, the predetermined constant being the same or variable depending on said each data block; and
a conversion performing subunit operable to perform conversion on said each one of the plurality of data blocks to which the constant is added by the adding subunit, the conversion being based on the exponentiation to the predetermined exponent in the polynomial residue class ring.
4. The data converter according to
wherein the output data generating unit includes:
an adding subunit operable to perform addition in the polynomial residue class ring among the plurality of data blocks converted by the conversion performing unit; and
a multiplying subunit operable to multiply, in the finite field GF (2
^{n}), a result of the addition by the adding subunit by a predetermined constant. 5. The data converter according to
a finite field multiplying unit operable to perform multiplication in the finite field GF (2
^{n}), wherein the conversion performing unit performs exponentiation using the finite field multiplying unit, and
the multiplying subunit performs multiplication using the finite field multiplying unit.
6. A data conversion/method comprising:
splitting input data intoobtaining a plurality of data blocks;
performing conversion on each one of the plurality of data blocks, the conversion being based on an exponentiation by a predetermined exponent in a polynomial residue class ring with a value in a finite field GF (2
^{n}) as a coefficient, the n being a natural number, as a coefficient;and the exponentiation using a predetermined value as an exponent; and generating output data based on the plurality of data blocks converted by the conversion performance,
wherein the predetermined exponentvalue is a value that is 3 or larger and except 2
^{m}, the m being an integer which is 1 or larger. 7. The data conversion method according to
wherein in the conversion performance, the exponentiation is performed using a finite field multiplying unit operable to perform multiplication in the finite field GF (2
^{n}). 8. The data conversion method according to
wherein the conversion performance includes:
adding, in the polynomial residue class ring, a predetermined constant and each one of the plurality of split data blocks, the predetermined constant being the same or variable depending on said each data block; and
performing conversion on said each one of the plurality of data blocks to which the constant is added by the addition, the conversion being based on anthe exponentiation to a predetermined exponent in the polynomial residue class ring.
9. The data conversion method according to
wherein the output data generation includes:
performing addition in the polynomial residue class ring among the plurality of data blocks converted by the conversion performance; and
multiplying, in the finite field GF (2
^{n}), a result of the addition by a predetermined constant. 10. The data conversion method according to
wherein in the conversion performance, the exponentiation is performed using a finite field multiplying unit operable to perform multiplication in the finite field GF (2
^{n}); and in the multiplication, the multiplication is performed using the finite field multiplying unit operable to perform multiplication in the finite field GF (2
^{n}). 11. An integrated circuit comprising:
a finite field multiplying unit operable to perform multiplication in a finite field GF (2
^{n}), the n being a natural number; an error-correction coding unit operable to perform error-correction coding on input data by performing multiplication in the finite field GF (2
^{n}) using the finite field multiplying unit; a splitting unit operable to split the input data into a plurality of data blocks;
a conversion performing unit operable to perform conversion on each one of the plurality of data blocks, the conversion being based on an exponentiation to a predetermined exponent in a polynomial residue class ring with a value in the finite field GF (2
^{n}) as a coefficient;coefficient, and the exponentiation using a predetermined value as an exponent; and generatingan output data generating unit operable to generate output data unit based on the plurality of data blocks converted by the conversion performing unit,
wherein the predetermined exponentvalue is a value that is 3 or larger and other than 2
^{m}, the m being an integer that is 1 or larger. 12. The integrated circuit according to
wherein the conversion performing unit includes:
an adding subunit operable to add, in the polynomial residue class ring, a predetermined constant and each one of the plurality of data blocks split by the splitting unit, the predetermined constant being the same or variable depending on said each data block; and
a conversion performing subunit operable to perform conversion, using the finite field multiplying unit, on said each one of the plurality of data blocks to which the constant is added by the adding subunit, the conversion being based on the exponentiation to a predetermined exponent in the polynomial residue class ring.
13. The integrated circuit according to
wherein the output data generating unit includes:
an adding subunit operable to perform addition in the polynomial residue class ring among the plurality of data blocks converted by the conversion performing unit; and
a multiplying subunit operable to multiply, in the finite field GF (2
^{n}), the result of the addition by the adding subunit by a predetermined constant using the finite field multiplying unit. 14. A program recorded on a computer readable medium that causes a computer to execute a method comprising:
splitting input data intoobtaining a plurality of data blocks;
performing conversion on each one of the plurality of data blocks using a finite field multiplying unit operable to perform multiplication in a finite field GF (2
^{n}), the n being a natural number, the conversion being based on an exponentiation to a predetermined exponent in a polynomial residue class ring with a value in the finite field GF (2^{n}) as a coefficient;coefficient, and the exponentiation using a predetermined value as an exponent; and generating output data based on the plurality of data blocks converted by the conversion performance,
wherein the predetermined exponentvalue is a value that is 3 or larger and other than 2
^{m}, the m being an integer which is 1 or larger. 15. The program according to
wherein the conversion performance includes:
adding, in the polynomial residue class ring, a predetermined constant and each one of the plurality of the split data blocks, the predetermined constant being the same or variable depending on said each data block; and
performing conversion on said each one of the plurality of data blocks added by the addition using the finite field multiplying unit, the conversion being based on anthe exponentiation to a predetermined exponent in the polynomial residue class ring.
16. The program according to
wherein the output data generation includes:
performing addition in the polynomial residue class ring among the plurality of data blocks converted by the conversion performance; and
multiplying, in the finite field GF (2
^{n}), a result of the addition by a predetermined constant using the finite field multiplying unit.Description This is a reissue application of U.S. Pat. No. (1) Field of the Invention The present invention relates to a data converter that realizes a data conversion system used for an authentication system and to a method thereof, in particular to a data converter that can be realized in an especially small size of implementation scale and has a high data confusion and to a method thereof. (2) Description of the Related Art In a challenge-response authentication system which is one of a method for examining a validity of a communication partner and the like, a secret conversion system is necessary for both authenticating and authenticated sides. As requirements for the secret conversion system, it is wished not only to have high data confusion performance (avalanche performance) but also to mount the method onto an apparatus at low cost. As a conventional example of a data conversion system, there is a system of using a secret key encryption system. For example, in the case of where the challenge-response authentication system is realized by a data conversion system using a 56 bits key length Data Encryption Standard (DES) encryption system (for details about the DES encryption system, refer to Menezes, Alfred J., et al., “HANDBOOK of APPLIED CRYPTOGRAPHY”, CRC Press, 1997: 252-256), both of the authenticating side and the authenticated side secretly store a 56 bits key of the DES encryption system as an authentication key. Also, a plaintext and encrypted text of the DES encryption system are respectively determined as an input and an output for the data converting system. Accordingly, the DES encryption method can be used for a secret data converting system for an authentication (for details about the authentication system, refer to Menezes, Alfred J., et al., “HANDBOOK of APPLIED CRYPTOGRAPHY”, CRC Press, 1997: 400-403). However, the secret key encryption system such as the DES encryption system is not constructed considering for sharing a circuit with other circuits that are mounted together with an encryption circuit in an apparatus. Therefore, it needs to be mounted as a circuit independent from other circuits. Accordingly, in a data conversion system using the conventional secret key encryption system, an encryption circuit is independently mounted separately from other circuits in the apparatus so that a scale of the circuit in the apparatus as a whole becomes large. That is, in order to realize an apparatus at a low cost, it is generally required to make a total scale of the circuit mounted in the apparatus smaller as possible. Therefore, it is desirable for the encryption circuit mounted in the apparatus to share the circuit with other circuits. However, it is not realized in the conventional structure. Considering the above mentioned problem, the present invention aims to provide a data converter capable of reducing the total size of the implementation scale in an apparatus. A data converter by the present invention comprises: a splitting unit operable to split input data into a plurality of data blocks; a conversion performing unit operable to perform conversion on each one of the plurality of data blocks, the conversion being based on an exponentiation to a predetermined exponent in a polynomial residue class ring with a value in a finite field GF (2 According to this structure, in the exponentiation, the multiplication in the polynomial residue class ring is performed. By performing an operation in the polynomial residue class ring, even if a part of the input data is changed as described later, the change affects all bits in the output data. Therefore, the data confusion can be improved. Also, when a multiplication with two or more variables is performed, if any one of the variables is 0, a result of the multiplication becomes 0 regardless of values of other variables and a better data confusion performance is not shown. On the other hand, when an exponentiation of the input data is performed, the data confusion performance can be improved without causing such problems. Furthermore, in the exponentiation, an operation in the polynomial residue class ring with a value in the finite field GF (2 As further information about technical background to this application, the disclosure of Japanese Patent Application No. 2003-353439 filed on Oct. 14, 2003 including specification, drawings and claims is incorporated herein by reference in its entirety. These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings that illustrate a specific embodiment of the invention. In the Drawings: The following explains about an embodiment of the present invention with references to diagrams. (Configuration of Authentication System with Data Converter) The authenticating apparatus (Configuration of Data Converter Whereas the data converters Firstly, the data splitting unit Next, the finite field polynomial cubing unit Next, the 32 bit data (A The data integrating unit The first converter After the above processes, the data integrating unit (Internal Configuration of Finite Field Polynomial Cubing Unit The input controlling unit Hereafter, it is explained about internal performances when 32 bit input data X is inputted to the finite field polynomial cubing unit The output controlling unit The finite field polynomial multiplying unit The output controlling unit (Internal Configuration of Finite Field Polynomial Multiplying Unit Firstly, it is explained about the operation in the finite field GF (2 From the above, the addition in the finite field (2 Next, a multiplication in the finite field GF (2 Here, “f(x) mod g(x)” is a residual calculation result of residual calculation f(x) modulo g(x) and m(x) is, as described before, a primitive polynomial m(x)=x An example of the multiplication is explained. Given A=57 (hexadecimal) and B=83 (hexadecimal), a(x)=x Next, it is explained about an operation in the polynomial residue class ring with a value in the finite field GF (2 Next, the multiplication in the polynomial residual class ring is explained. Given 32 bit data C as the result of multiplying the 32 bit data A and B, as explained above, when each data is applied to the third order polynomials A(X), B(X) and C(X), the multiplication in the polynomial residue class ring is expressed as the following polynomial operation:
Here, L(X) is, as explained, L(X)=X Herein, X Therefore, C can be calculated as follows:
With that, the explanation about the operations in the polynomial residue class ring and in the finite field GF (2 The finite field polynomial multiplying unit The finite field multiplying unit The data splitting unit Note that all of the multiplications “×” and the additions “+” are operated in the finite field GF (2 It is now explained only about performances of the finite polynomial multiplying unit The operation controlling unit Next, by similar performances, the finite field multiplying unit After outputting the Z Next, it is explained about an internal configuration and performances of the first converter (Internal Structure of First Converter The first converter The data splitting unit After the processing, the data integrating unit (Internal Configuration of Second Converter As shown in Next, with reference to (Internal Configurations of the Finite Field Multiplying Units The finite field multiplying units The finite field multiplying unit Each of the first input controlling unit First, the data splitting unit (1) The first input controlling unit (2) The finite field doubling unit (3) The second input controlling unit (4) The data integrating unit (5) The output controlling unit It is briefly explained about the reason why the multiplication of the first input data X and the second input data Y can be calculated through the above mentioned processes. Taking values Y So,
Next, it is explained about an internal configuration and performances of the finite field doubling unit (Internal Configuration of Finite Field Doubling Unit The finite field doubling unit The data splitting unit Firstly, the data splitting unit By denoting, for each bit X The input data X is denoted by a following polynomial of α whose coefficient is the value in the finite field GF (2).
Herein, doubling in the finite field GF (2 Here, the primitive polynomial is x The data converters (1) Split the input data X into the high-ordered 32 bits and the low-ordered 32 bits and denote respectively data X (2) Calculate T (3) Split the 32 bits data T (4) Calculate G As clear from the equations (1) to (4), in the multiplication in the polynomial residue class ring with a value in the finite field GF (2 Furthermore, in the present embodiment, the calculation raised to cube is used. This results in the following reasons. First, when given a conversion such as Y=X When k=1, the exponent=2, therefore the output value based on the above explanation is (α+Δ) Also, in the present embodiment, an addition (exclusive OR operation) by a constant K is calculated before the exponentiation such as (X+K) Herein, when the value of (X+K) Also, in the present embodiment, the same exponentiation in cube is performed on four data blocks of A Further, the data converter according to the present embodiment uses an operation processing in the finite field GF (2 Note that each data size of the present invention is just an example and it can be beyond the data size. Also, the primitive polynomial and the residue polynomial according to the present embodiment are just examples. Therefore, the size is not limited to this. Furthermore, the present embodiment describes about the case where the data converter is used in the authentication system. However, the data converter of the present embodiment can be used unless it uses a secret data converter. As other applied examples of using the data converter is that, for example, it can be applied to a content distribution system as shown in FIG. Also, in the present embodiment, whereas fixed values K Furthermore in the present embodiment, whereas the finite field GF (2 Note that each functional block in the block diagrams ( As shown in The Reed-Solomon error correction coding unit While the data converter Accordingly, the Reed-Solomon error correction coding unit Here, the error correction/data converter In addition, a method of constructing the integrated circuit is not limited to the LSI. It can be realized by a special circuit or a general processor. A Field Programmable Gate Array (FPGA) capable of programming and a reconfigurable processor capable of reconfiguring a connection and a setting of the circuit cell inside the LSI after manufacturing the LSI may be used. Furthermore, if a technique of constructing the integrated circuit which can be replaced of the LSI according to the development of the semiconductor technology and an emerging technology is introduced, the functional block may be of course integrated using the newly introduced technique. As another technology, it is possible that a biotechnology and the like may be used. Although only an exemplary embodiment of this invention has been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiment without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention. The data converter according to the present invention can reduce a scale of a circuit as a whole including a data converter by sharing a data conversion with an error correction coding circuit. Therefore, for example, it is useful for an apparatus having a function of authenticating a communication partner via a communication channel. Also, not only limited to this example, this invention applies to any apparatuses unless they need to mount any kind of a data conversion circuit. Patent Citations
Non-Patent Citations
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