|Publication number||USRE40776 E1|
|Application number||US 11/119,494|
|Publication date||Jun 23, 2009|
|Filing date||Jun 12, 1998|
|Priority date||Jun 13, 1997|
|Also published as||CA2262491A1, DE69831308D1, DE69831308T2, EP0931403A1, EP0931403B1, US6556570, WO1998057466A1|
|Publication number||11119494, 119494, PCT/1998/1239, PCT/FR/1998/001239, PCT/FR/1998/01239, PCT/FR/98/001239, PCT/FR/98/01239, PCT/FR1998/001239, PCT/FR1998/01239, PCT/FR1998001239, PCT/FR199801239, PCT/FR98/001239, PCT/FR98/01239, PCT/FR98001239, PCT/FR9801239, US RE40776 E1, US RE40776E1, US-E1-RE40776, USRE40776 E1, USRE40776E1|
|Inventors||Michel Delattre, Didier Guerin, Marc Bavant|
|Original Assignee||Michel Delattre, Didier Guerin, Marc Bavant|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Classifications (10), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to a process for translating a header of a cell applied to the input of a node of an asynchronous packet data transmission network.
It applies in particular to the digital data switching and cross-connection equipment making up a network operating in the mode of transmission known by the abbreviation ATM standing for “Asynchronous Transfer Mode”.
2. Discussion of the Background
The ATM asynchronous transfer mode is mainly defined in the recommendations of the ITU-T (series I), as well as in the work of an industrial grouping dubbed the “ATM Forum”.
In the ATM asynchronous transfer mode the information to be transmitted is grouped together in the form of packets. Together, header plus data is dubbed a cell. Basically, ATM operates in a connected mode, that is to say it has to establish a route through the transmission network before being able to transmit the data. This route is termed a “virtual circuit”. There are in general numerous virtual circuits which follow the same physical connection between two items of ATM equipment. The main role of the header of the cells is to allow the identification of the virtual circuits over the link. An example of implementing such a process is known in particular from French Patent Application No. 2 681 164 filed in the name of the Applicant.
A virtual circuit is obtained by placing end-to-end virtual communication pathways established between adjacent switches. These pathways are of two types: virtual paths or virtual channels, the virtual channels being regarded as a subdivision of the virtual paths. On a given highway, any virtual circuit is fully determined by indicating the identifier of the virtual path (VPI) and that of the virtual channel (VCI) which it follows, in the case of a circuit to be switched in VC mode (VCC), or else by indicating just the identifier of the virtual path (VPI), in the case of a circuit to be switched in VP mode (VPC).
According to this process, each cell to be routed within a network is composed on the one hand of a header making it possible to identify it and guide it through the pathways making up the virtual circuit, and on the other hand, of a part containing the information to be conveyed. Routing is effected at the level of each node of the network by extracting from the header the address of a word contained in a first context memory containing the information required for identifying the header and for guiding the data to be conveyed and by creating a new address on the basis of the word read from the first context memory. This new address serves as a pointer to an area of a second context memory in which there is at least one new header and one outgoing direction information cue for the cell or cells existing the node.
The translation function which is thus carried out makes it possible for each cell to be associated with the information enabling it to undergo the processing operations for which it is intended. The translator which is responsible for executing this function on each cell which it receives must typically provide information about the validity of the virtual path identifier, the validity of the virtual channel identifier, counting, the list of outgoing directions in which the cell received is transmitted, the new header associated with the cell during its transmission etc. The translator must also execute the processing operations corresponding to the context defined previously for each cell. These processing operations relate in particular to virtual path (VP) switching, virtual channel (VC) switching and the extracting of the maintenance flows.
From the structural standpoint the translation function is carried out with the aid of a memory plane addressed by a microprogrammed processing unit.
However, this very large memory plane, whose size may contain for example 232 words of 16 bits, is difficult to manage.
To alleviate this difficulty, the French Patent Application published under No. 2 726 669 filed by the applicant proposed that the memory space of the node be addressed on the basis of the virtual path number VPI contained in the header of the cell so as to identify in this space a first context area indicating the range of the virtual channels which can be used by the cell for this VPI
However, this process proves to be poorly suited to the constraints imposed by the new virtual interfaces of switches such as for example the “Virtual UNI” interface specified in chapter A7-4 of the ATM Forum's “UNI signalling version 4.0” specification. It does not for example allow a rearrangement of the translation memory when there is a modification in the number of users who, on one and the same physical interface, are sharing the virtual path capacities.
This is manifested through the appearance of gaps in the translation memory which limit the possibilities for utilizing the whole spectrum of possible VPI and VCI values.
The purpose of the invention is to alleviate the above-mentioned drawbacks.
To this end, the subject of the invention is a process for translating an ATM cell header for the routing thereof on a transmission highway of a communication network via an ATM switch, the header of the cell comprising a first field VPI and a second field VCI, the first field VPI identifying a virtual path number and the second field VCI selecting a specified virtual channel within the virtual path, characterized in that it consists:
The main advantage of the invention is that it associates the N contexts determined by the available memory size with a number of connection of the same order of magnitude as N, even if the identifiers (VPI, VCI) of its connections describe ranges of values which are multiples from among the 228 theoretically possible values. It also allows partial modifications of the configuration of a network consisting for example in modifying a VP switching mode into a VC mode for a specified VPI value or else in activating/deactivating a consequent string of VPI values, without impairing the operational functioning involving the VPI and VCI values for which the modification is not relevant. As another advantage the size of the translation memory is suited to the strict need of a limited number of connections (either VPC or VCC), this number being small relative to the numbers of possible combinations of the VPI/VCI values. On the other hand, the translation operations, especially those giving rise to slow memory accesses, are reduced to a minimum number, thereby making it possible to process ATM flows with high bit rates of for example greater than 155 Mbps. Finally, it allows the installation of a temporary bypass to a built-in test probe in VP switching mode so as to observe the traffic over certain virtual channels VC.
Other characteristics and advantages of the invention will emerge from the following description which is given with regard to the appended drawings which represent:
According to the embodiment of
The addressing of the context page on the basis of the major tables 3 and 4 takes place in accordance with the diagram of
According to one of the characteristics of the invention the size of the VPC and VCC contexts is constant and is determined by the relation TVPC=TVCC=2M where M is an integer which is independent of the sizes of pages. The size of an indirect addressing context is TIND=1.
Denoting by Np0, Np1, Np2, Np3 and Np4 the numbers of bits making up the areas VPI0, VPI1, VPI2, VPI3 and VPI4 respectively of the field VPI and by Nc0, Nc1 and Nc4 the numbers of bits making up the areas VCI0, VCI1 and VCI4 respectively, the size of the context pages is defined as follows:
Since the size of the pages is constant the above relations make it possible to write
Furthermore, the following relations exist:
The sizes of the major tables have respective values 2Np1,2Np2,TIND for the major table (VC mode) 3 and 2NP1,TIND for the major table (VP mode) 4.
Taking as parameters P=12, the following relations are obtained.
By way of example, a dimensioning with M=5 may be as follows:
An algorithm for implementing the addressing process according to the invention is described below with the aid of steps 11 to 21 of the flow chart of FIG. 5.
In this flow chart the translation process commences at step 11 with a check of the validity of the virtual circuit identifier by extracting through logical intersection, for example, the bits of the area VPI0. If the identifier is not valid, the cell is rejected in step 19. If the identifier is validated, step 12 is executed in order to access, in the major table 3, the pointer M1 of an indirect addressing page at the address indicated by the areas VPI1 and VPI2. If the pointer M1 is null, the VP switching mode is selected by fetching in step 13 the word M4 from the major table 4 at the address indicated by the area VPI1. If the content of the word M4 is not null, a VP context is selected in step 14 from the context page M4 of the VP switching mode, at the address indicated by the content of the field VPI4. In the case in which the word M4 is null, the cell is rejected in step 15. If the test performed in step 12 indicates that the content of the pointer M1 is not null, then a VC context page is selected in step 16 at the address indicated by the page pointer M2 found inside the indirect addressing context 5 page M1 at the address indicated by the fields VPI3 and VCI1. If M2 is null, we return to the VP switching mode and we go to step 13. If M2 is not null, a test is performed in step 17 on the content of the field VCI0. If the later is not null, a context is selected in step 18 from the VCC context page addressed by the pointer M2 at the address indicated by the content of the field VCI4. If VCI0 is null, the cell is rejected in step 19. Upon the two cases of error which are identified in this flow chart (15 and 19), specific counters can be incremented. Furthermore, during steps 14 and 18, a check is carried out in the context reached to verify whether the VPC or the VCC concerned is active before performing the translation.
Variants to this process may be implemented for the addressing of pages, of 16, 32 and 128 contexts. By way of example, the addressing of pages with 16 contexts can take place by performing the following operations referenced from (a to k):
If the indicator is inactive, reject the cell (increment a counter).
Similar operations can be executed for the addressing of pages with 32 and 128 contexts.
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|U.S. Classification||370/395.31, 370/397, 370/399|
|International Classification||H04L12/70, H04L12/935|
|Cooperative Classification||H04L2012/5619, H04L49/3009, H04L49/3081|
|European Classification||H04L49/30A, H04L49/30J|
|Mar 31, 2010||AS||Assignment|
Owner name: REMOTE ACCESS, LLC,CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:THALES SA;REEL/FRAME:024165/0697
Effective date: 20080420
|Apr 6, 2010||CC||Certificate of correction|
|Sep 22, 2010||FPAY||Fee payment|
Year of fee payment: 8
|Dec 5, 2014||REMI||Maintenance fee reminder mailed|
|Apr 29, 2015||LAPS||Lapse for failure to pay maintenance fees|