|Publication number||USRE40790 E1|
|Application number||US 09/488,099|
|Publication date||Jun 23, 2009|
|Filing date||Jan 18, 2000|
|Priority date||Jun 23, 1992|
|Publication number||09488099, 488099, US RE40790 E1, US RE40790E1, US-E1-RE40790, USRE40790 E1, USRE40790E1|
|Inventors||Charles H. Dennison, Guy T. Blalock|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (43), Non-Patent Citations (12), Classifications (16)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,229,326. The reissue applications are U.S. application Ser. No. 09/488,099 (the present application) and U.S. application Ser. No. 08/504,943, now RE 36,518, of which the present application is a continuation.
This invention relates to semiconductor processing methods for making electrical contact with an active area and more particularly, for making electrical contact with an active area through sub-micron contact openings. This invention also relates to semiconductor devices having buried contact plugs.
As semiconductor devices are scaled down to increase packing density, distances between adjacent components are becoming increasingly smaller. Sub-micron geometries are possible with currently available technologies. In some high-density memory devices, distances between adjacent word lines are required to be 0.4 micron or less to produce a sufficiently dense cell. At these geometries, problems arise when attempting to define contact openings to active areas between these adjacent, tightly spaced word lines. Present photolithographic alignment and metallization techniques are only possible to 0.35 micron features, with a misalignment error of ±0.15 micron. Without the use of self-aligned active area contacts, the minimum word line spacing would be approximately greater than 0.85 micron which is equal to the minimum photolithographic feature of 0.35 micron, plus twice the misalignment tolerance of 0.15 micron, plus twice the processing margin of 0.10 micron (or, 0.35 micron+2×0.15 micron+2×0.10 micron=0.85 micron). Present processing techniques are therefore incapable of producing narrow and properly aligned contact openings to active areas for geometries of 0.4 micron or less.
This invention provides a processing method for making contacts to active areas between semiconductor word line (conductive runners) having sub-micron geometries.
One or more preferred embodiments of the invention are described below with reference to the following accompanying drawings.
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
In accordance with one aspect of the invention, a semiconductor processing method of making electrical contact with an active area on a semiconductor wafer comprises the following steps:
providing a pair of conductive runners on a semiconductor wafer, individual conductive runners having sides;
providing an insulative layer on the sides of the conductive runners, the insulative sides of adjacent conductive runners being spaced a selected distance apart at a selected location on the wafer;
providing an active area between the conductive runners at the selected location;
providing a layer of first oxide to a selected thickness over the active area and conductive runners, the first oxide layer selected thickness being less than one-half the selected distance between the insulative sides of adjacent conductive runners;
providing a first planarized layer of insulating material atop the first oxide layer, the first layer of insulating material being selectively etchable relative to the first oxide, the first layer of insulating material having an upper surface;
patterning the planarized first insulating layer for definition of a first contact opening therethrough to the active area;
etching the patterned first insulating layer selectively relative to the first oxide layer to define the first contact opening therethrough, the first contact opening having an aperture width at the planarized first insulating layer upper surface, the aperture width being greater than the selected distance between the insulative sides of adjacent conductive runners;
etching the first oxide layer within the first contact opening to expose the active area;
providing a plug of conductive material within the first contact opening over the exposed active area;
providing a second insulating layer over the first insulating layer and the conductive plug;
patterning and etching the second insulating layer to form a second contact opening to and exposing the conductive plug; and providing a conductive layer over the second insulating layer and into the second contact opening, the conductive layer electrically contacting the conductive plug.
In accordance with another aspect of the invention, the step of providing a first planarized layer of insulating material comprises:
providing a conformal first layer of insulating material atop the first oxide layer; and
chemical mechanical polishing the wafer to planarize the first insulating layer.
In accordance with yet another aspect of the invention, a semiconductor device comprises:
conductive runners formed on the semiconductor wafer, individual runners having a top and sides;
insulative spacers provided on the sides of the conductive runners, the spacers of adjacent runners being spaced a selected distance apart at selected locations on the wafer;
active areas positioned between the conductive runners at the selected locations;
an insulating layer with an upper surface formed over the runners, the insulating layer having first contact openings between adjacent runners above the selected locations, the first contact openings having an aperture width at the upper surface which is greater than the selected distance;
conductive plugs disposed in the first contact openings to electrically contact the active areas, individual conductive plugs having a substantially flat upper surface, the upper surfaces of the conductive plugs being approximately uniform in elevational height across the wafer;
an oxide layer provided above the insulating layer and having second contact openings formed therethrough which extend to the upper surfaces of the conductive plugs; and
a conductive layer disposed above the oxide layer and in the second contact openings to electrically contact the conductive plugs.
A semiconductor processing method of making electrical contact with an active area on a semiconductor wafer is described with reference to
An insulative layer is provided over wafer 10, and then patterned and etched to define insulative spacers 34 on the sides of conductive runners 20, 22, 24, and 26. Insulative spacers 34 on the sides of adjacent conductive runners 20, 22 and 24, 26 are spaced a distance D apart at a selected location on wafer 10 in which a buried contact is eventually formed.
An impurity is implanted into substrate 12 to define source/drain regions 36, 38, 40, and 42. In subsequent steps discussed below, buried contact openings are formed to expose source/drain region 38 of active area 16 and source/drain region 40 of active area 18.
A thick conformal first layer of insulating material 48 is provided on top of first oxide layer 44. First insulating layer 48 is formed of a material which is selectively etchable relative to first oxide layer 44, and is preferably formed of a nitride. First insulating layer 48 has an upper surface 50 which generally follows the contour defined by the underlying topography of the runners and field oxide. Upper surface 50 defines a lowest elevational location H above active areas 16 and 18 which is elevationally higher than highest elevational location K of first oxide layer 44.
One of the advantages of this invention is that plugs 58 and 60 have relatively large upper surface areas. The distance across plugs 58 and 60 at upper surfaces 62 and 64 is equal to width W of contact openings 54 and 56 (FIG. 4). This distance is significantly greater than distance D (
According to one aspect of the invention, conductive plugs 58 and 60 are formed by providing a layer of conductive material (preferably polysilicon) over first insulating layer 48 and within first contact openings 54 and 56. The semiconductor wafer is then subjected to chemical mechanical polishing to remove the conductive layer from upper surface 52 of first insulating layer 48. All the conductive material is removed from upper surface 52 to electrically isolate individual plugs 58 and 60 and to prevent formation of undesired stray conductive traces between conductive plugs 58 and 60. To help insure that all conductive material is removed from upper surface 52, plugs 58 and 60 are over polished such that plug surfaces 62 ad 64 are slightly below first insulating layer upper surface 52. In this manner, individual plugs 58 and 60 are electrically isolated from one another.
An alternative technique to chemical mechanical polishing is to subject the layer of conductive material to a resist etch back process to define the slightly recessed plug surfaces 62 and 64 of respective plugs 58 and 60.
Another advantage provided by this invention relates to misalignment tolerance. In
This invention defines a processing method for submicron geometries, and is most useful at geometries of less than 0.4 micron. The combined thin oxide and thick nitride layers afford a structure suitable for highly selective etching to define contact openings on the scale of 0.3 to 0.4 micron. The uniformly elevated and significantly wide landing plugs provide an easy target for conventional photolithographic techniques when forming the second contact openings. Additionally, the wide landing plugs provide misalignment tolerance which helps increase production yield.
In compliance with the statute, the invention has been described in language more or less specific as to methodical features. It is to be understood, however, that the invention is not limited to the specific features described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3423646 *||Feb 1, 1965||Jan 21, 1969||Sperry Rand Corp||Computer logic device consisting of an array of tunneling diodes,isolators and short circuits|
|US3796926 *||Mar 29, 1971||Mar 12, 1974||Ibm||Bistable resistance device which does not require forming|
|US4099260 *||Sep 20, 1976||Jul 4, 1978||Bell Telephone Laboratories, Incorporated||Bipolar read-only-memory unit having self-isolating bit-lines|
|US4115872 *||May 31, 1977||Sep 19, 1978||Burroughs Corporation||Amorphous semiconductor memory device for employment in an electrically alterable read-only memory|
|US4174521 *||Apr 6, 1978||Nov 13, 1979||Harris Corporation||PROM electrically written by solid phase epitaxy|
|US4194283 *||Aug 16, 1978||Mar 25, 1980||Siemens Aktiengesellschaft||Process for the production of a single transistor memory cell|
|US4203123 *||Dec 12, 1977||May 13, 1980||Burroughs Corporation||Thin film memory device employing amorphous semiconductor materials|
|US4227297 *||Jul 31, 1978||Oct 14, 1980||Siemens Aktiengesellschaft||Method for producing a single transistor storage cell|
|US4272562 *||Jun 19, 1979||Jun 9, 1981||Harris Corporation||Method of fabricating amorphous memory devices of reduced first fire threshold voltage|
|US4458260 *||Nov 20, 1981||Jul 3, 1984||Rca Inc.||Avalanche photodiode array|
|US4502208 *||Aug 26, 1983||Mar 5, 1985||Texas Instruments Incorporated||Method of making high density VMOS electrically-programmable ROM|
|US4569698 *||May 31, 1985||Feb 11, 1986||Raytheon Company||Method of forming isolated device regions by selective successive etching of composite masking layers and semiconductor material prior to ion implantation|
|US4617193||Jun 16, 1983||Oct 14, 1986||Digital Equipment Corporation||Planar interconnect for integrated circuits|
|US4714686||Jul 31, 1985||Dec 22, 1987||Advanced Micro Devices, Inc.||Method of forming contact plugs for planarized integrated circuits|
|US4757359 *||Apr 7, 1986||Jul 12, 1988||American Microsystems, Inc.||Thin oxide fuse|
|US4804490 *||Oct 13, 1987||Feb 14, 1989||Energy Conversion Devices, Inc.||Method of fabricating stabilized threshold switching material|
|US4809044 *||Nov 26, 1986||Feb 28, 1989||Energy Conversion Devices, Inc.||Thin film overvoltage protection devices|
|US4823181 *||May 9, 1986||Apr 18, 1989||Actel Corporation||Programmable low impedance anti-fuse element|
|US4868138||Mar 23, 1988||Sep 19, 1989||Sgs-Thomson Microelectronics, Inc.||Method for forming a self-aligned source/drain contact for an MOS transistor|
|US4876220 *||Nov 13, 1987||Oct 24, 1989||Actel Corporation||Method of making programmable low impedance interconnect diode element|
|US4876668 *||Apr 29, 1986||Oct 24, 1989||California Institute Of Technology||Thin film memory matrix using amorphous and high resistive layers|
|US4881114 *||May 16, 1986||Nov 14, 1989||Actel Corporation||Selectively formable vertical diode circuit element|
|US4892840 *||Apr 11, 1989||Jan 9, 1990||Texas Instruments Incorporated||EPROM with increased floating gate/control gate coupling|
|US4892845||Aug 31, 1984||Jan 9, 1990||Texas Instruments Incorporated||Method for forming contacts through a thick oxide layer on a semiconductive device|
|US5110766||Jul 6, 1990||May 5, 1992||Kabushiki Kaisha Toshiba||Method of manufacturing a semiconductor device including forming a flattening layer over hollows in a contact hole|
|US5124280||Jan 31, 1991||Jun 23, 1992||Sgs-Thomson Microelectronics, Inc.||Local interconnect for integrated circuits|
|US5144404 *||Aug 22, 1990||Sep 1, 1992||National Semiconductor Corporation||Polysilicon Schottky clamped transistor and vertical fuse devices|
|US5158910||Nov 26, 1990||Oct 27, 1992||Motorola Inc.||Process for forming a contact structure|
|US5166096 *||Apr 14, 1992||Nov 24, 1992||International Business Machines Corporation||Process for fabricating self-aligned contact studs for semiconductor structures|
|US5166758 *||Jan 18, 1991||Nov 24, 1992||Energy Conversion Devices, Inc.||Electrically erasable phase change memory|
|US5171713||Jan 28, 1991||Dec 15, 1992||Micrunity Systems Eng||Process for forming planarized, air-bridge interconnects on a semiconductor substrate|
|US5177567 *||Jul 19, 1991||Jan 5, 1993||Energy Conversion Devices, Inc.||Thin-film structure for chalcogenide electrical switching devices and process therefor|
|US5296716 *||Aug 19, 1991||Mar 22, 1994||Energy Conversion Devices, Inc.||Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom|
|US5335219 *||Sep 30, 1991||Aug 2, 1994||Ovshinsky Stanford R||Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements|
|US5341328 *||Jun 15, 1992||Aug 23, 1994||Energy Conversion Devices, Inc.||Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life|
|US5359205 *||May 8, 1992||Oct 25, 1994||Energy Conversion Devices, Inc.||Electrically erasable memory elements characterized by reduced current and improved thermal stability|
|US5510629 *||May 27, 1994||Apr 23, 1996||Crosspoint Solutions, Inc.||Multilayer antifuse with intermediate spacer layer|
|DE4107883A1||Mar 12, 1991||Sep 19, 1991||Mitsubishi Electric Corp||Semiconductor device - contains gate electrodes formed on insulation regions between impurity regions|
|EP0117045A2 *||Jan 13, 1984||Aug 29, 1984||OIS Optical Imaging Systems, Inc.||Liquid crystal flat panel display|
|GB1319388A *||Title not available|
|JPS6232630A||Title not available|
|JPS6472543A||Title not available|
|JPS60109266A *||Title not available|
|1||*||Kim and Kim, "Effects of High Pulses on Polycrystalline Silicon Diode with n-type Region Heavily Doped with Both Boron and Phosphorus," J. Appl. Phys., 53(7):5359-5360, 1982, No month.|
|2||*||Neale and Aseltine, "The Application of Amorphous Materials to Computer Memories," IEEE, 20(2):195-205, 1973, No month.|
|3||*||Oakley et al., "Pillars-The Way to Two Micron Pitch Multilevel Metallization," IEEE, 23-29, 1984, No month.|
|4||*||Pein and Plummer, "Performance of the 3-D Sidewall Flash EPROM Cell," IEEE, 11-14, 1993, No month.|
|5||*||Post and Ashburn, "Investigation of Boron Diffusion in Polysilicon and its Application to the Design of p-n-p Polysilicon Emitter Bipolar Transistors with Shallow Emitter Junctions," IEEE, 38(11):2442-2451, 1991, No month.|
|6||*||Post and Ashburn, "The Use of an Interface Anneal to Control the Base Current and Emitter Resistance of p-n-p Polysilicon Emitter Bipolar Transistors," IEEE, 13(8):408-410, 1992, No month.|
|7||*||Post et al., "Polysilicon Emitters for Bipolar Transistors: A Review and Re-Evaluation of Theory and Experiment," IEEE, 39(7):1717-1731, 1992, No month.|
|8||*||Rose et al., "Amorphous Silicon Analogue Memory Devices," J. Non-Crystalline Solids, 115:168-170, 1989, No month.|
|9||*||Schaber et al., "Laser Annealing Study of the Grain Size Effect in Polycrystalline Silicon Schottky Diodes," J. Appl. Phys., 53(12):8827-8834, 1982, No month.|
|10||*||Yamamoto et al., "The I-V Characteristics of Polycrystalline Silicon Diodes and the Energy Distribution of Traps in Grain Boundaries," Electronics and Communications in Japan, Part 2, 75(7):51-58, 1992, No month.|
|11||*||Yeh et al., "Investigation of Thermal Coefficient for Polycrystalline Silicon Thermal Sensor Diode," Jpn. J. Appl. Phys., 31(Part 1, No. 2A):151-155, 1992, No month.|
|12||Yoshire Nakata et al., "Tunnel Shape Stacked Capacitor (TSSC) Memory Cell for 64Mb Dram", article (date unknown).|
|U.S. Classification||438/586, 438/633, 438/692, 438/524|
|International Classification||H01L21/44, H01L21/60, H01L23/485, H01L21/48, H01L23/522|
|Cooperative Classification||H01L21/76897, H01L23/485, H01L2924/0002, H01L23/5226|
|European Classification||H01L21/768S, H01L23/522E, H01L23/485|