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Publication numberUSRE40790 E1
Publication typeGrant
Application numberUS 09/488,099
Publication dateJun 23, 2009
Filing dateJan 18, 2000
Priority dateJun 23, 1992
Publication number09488099, 488099, US RE40790 E1, US RE40790E1, US-E1-RE40790, USRE40790 E1, USRE40790E1
InventorsCharles H. Dennison, Guy T. Blalock
Original AssigneeMicron Technology, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
US RE40790 E1
Abstract
A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first contact opening over the exposed active areas; (i) providing an insulating layer over the nitride layer and the polysilicon plug; (j) patterning and etching the insulating layer to form a second contact opening to and exposing the polysilicon plug; and (k) providing a conductive layer over the insulating layer and into the second opening to electrically contact the polysilicon plug. A semiconductor device having buried landing plugs of approximately uniform height across the wafer is also described.
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Claims(31)
1. A semiconductor processing method of making electrical contact with an active area on a semiconductor wafer, the method comprising the following steps:
providing a pair of conductive runners on a semiconductor wafer, individual conductive runners having sides;
providing an insulative layer on the sides of the conductive runners, the insulative sides of adjacent conductive runners being spaced a selected distance apart at a selected location on the wafer;
providing an active area between the conductive runners at the selected location;
providing a layer of first oxide to a selected thickness over the active area and conductive runners, the first oxide layer selected thickness being less than one-half the selected distance between the insulative sides of adjacent conductive runners;
providing a first planarized layer of insulating material atop the first oxide layer, the first layer of insulating material being selectively etchable relative to the first oxide, the first layer of insulating material having an upper surface;
patterning the planarized first insulating layer for definition of a first contact opening therethrough to the active area;
etching the patterned first insulating layer selectively relative to the first oxide layer to define the first contact opening therethrough, the first contact opening having an aperture width at the planarized first insulating layer upper surface, the aperture width being greater than the selected distance between the insulative sides of adjacent conductive runners;
etching the first oxide layer within the first contact opening to expose the active area;
providing a plug of conductive material within the first contact opening over the exposed active area;
providing a second insulating layer over the first insulating layer and the conductive plug;
patterning and etching the second insulating layer to form a second contact opening to and exposing the conductive plug; and
providing a conductive layer over the second insulating layer and into the second contact opening, the conductive layer electrically contacting the conductive plug.
2. A semiconductor processing method according to claim 1 wherein the selected first oxide layer thickness is from about 100 to 1,000 Angstroms.
3. A semiconductor processing method according to claim 1 wherein the selected first oxide layer thickness is from about 300 to 500 Angstroms.
4. A semiconductor processing method according to claim 1 wherein the first insulating layer is formed of a nitride.
5. A semiconductor processing method according to claim 1 wherein the conductive plug is formed of polysilicon.
6. A semiconductor processing method according to claim 1 wherein the step of providing a first planarized layer of insulating material comprises:
providing a conformal first layer of insulating material atop the first oxide layer; and
chemical mechanical polishing the wafer to planarize the first insulating layer.
7. A semiconductor processing method according to claim 1 wherein the first insulating layer has an upper surface and wherein the step of providing a plug of conductive material comprises:
providing a layer of conductive material over the first insulating layer and within the first contact opening over the exposed active area;
chemical mechanical polishing the wafer to remove the conductive layer from the first insulating layer upper surface and to define a plug within the first contact opening, the plug having an upper surface slightly below the first insulating layer upper surface to ensure that the plug is electrically isolated.
8. A semiconductor processing method according to claim 1 wherein the second insulating layer is etched with an etchant selective to both the first insulating layer and the conductive plug.
9. A semiconductor processing method according to claim 1 wherein:
the first insulating layer is formed of a nitride;
the conductive plug is formed of polysilicon; and
the second insulating layer is etched with an etchant selective to both the nitride insulating layer and the polysilicon plug.
10. A semiconductor processing method for making electrical contact with an active area on a semiconductor wafer comprising the steps of:
providing a pair of conductive runners on a semiconductor wafer, individual conductive runners having a top and sides;
providing insulative spacers on the sides of the runners, the insulative spacers being spaced a selected distance apart at a selected location on the wafer;
providing an active area between the conductive runners at the selected location;
depositing a first oxide layer over the wafer to a thickness from about 100 to 1,000 Angstroms, the first oxide layer having an upper surface defining a highest elevational location above the active area;
providing a nitride layer having an upper surface over the first oxide layer to a selected thickness, the nitride layer upper surface defining a lowest elevational location above the active area which is elevationally higher than the highest elevational location of the first oxide layer, the nitride being selectively etchable relative to the first oxide;
planarizing the nitride layer to a first elevational height above the active area, the first elevational height being higher than the highest elevational location of the first oxide layer;
patterning the planarized nitride layer for definition of a first contact opening therethrough to the active area;
etching the patterned nitride layer selectively relative to the first oxide layer to define the first contact opening therethrough, the first contact opening having an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative sides of adjacent conductive runners;
etching the first oxide layer within the first contact opening to expose the active area;
providing a polysilicon plug within the first contact opening over the exposed active area to a second elevational height;
depositing a second oxide layer over the nitride layer and the polysilicon plug;
patterning and etching the second oxide layer to form a second contact opening to and exposing the polysilicon plug; and
providing a conductive layer over the second oxide layer and into the second contact opening, the conductive layer electrically contacting the conductive plug.
11. A semiconductor processing method according to claim 10 wherein the selected first oxide layer thickness is from about 300 to 500 Angstroms.
12. A semiconductor processing method according to claim 10 wherein the step of planarizing the nitride layer comprises chemical mechanical polishing the wafer to planarize the nitride layer.
13. A semiconductor processing method according to claim 10 wherein the step of providing a polysilicon plug comprises:
providing a layer of polysilicon over the nitride layer and within the first contact opening over the exposed active area;
chemical mechanical polishing the wafer to remove the polysilicon layer from the nitride layer upper surface and to define a polysilicon plug within the first contact opening.
14. A semiconductor processing method according to claim 10 wherein the second oxide layer is etched by an etchant selective to both the nitride layer and the polysilicon plug.
15. A semiconductor processing method according to claim 10 wherein the second elevational height is approximately equal to the first elevational height.
16. A semiconductor processing method according to claim 10 wherein the second elevational height is slightly lower than the first elevational height.
17. A semiconductor processing method of forming an electrical contact structure for an active area on a semiconductor wafer, the method comprising the following steps:
providing a pair of conductive runners on a semiconductor wafer, individual conductive runners having sides;
providing an insulative layer on the mutually adjacent sides of the conductive runners, the insulated mutually adjacent sides of adjacent conductive runners being spaced a selected distance apart;
providing an active area between the insulated mutually adjacent sides of conductive runners;
providing a layer of first oxide to a selected thickness over the active area and conductive runners, the first oxide layer selected thickness being less than one-half the selected distance between the insulated sides of adjacent conductive runners;
providing a first insulating layer having a planarized upper surface atop the first oxide layer, the first layer of insulating material being selectively etchable relative to the first oxide;
patterning the first insulating layer for definition of a first contact opening therethrough to the active area;
etching the patterned first insulating layer selectively relative to the first oxide layer to define the first contact opening therethrough, the first contact opening having an aperture width at the first insulating layer planarized upper surface, the aperture width being greater than the selected distance between the insulated sides of adjacent conductive runners;
etching the first oxide layer within the first contact opening to expose the active area; and
providing a conductive plug of within the first contact opening over the exposed active area.
18. A semiconductor processing method according to claim 17 wherein the step of providing a plug of conductive material comprises:
providing a layer of conductive material over the first insulating layer and within the first contact opening over the exposed active area; and
polishing the wafer to remove the conductive layer from the first insulating layer planarized upper surface and to define the conductive plug within the first contact opening, the plug having an upper surface slightly below the first insulating layer planarized upper surface.
19. A semiconductor processing method according to claim 17 further comprising:
providing a second insulating layer and the conductive plug; and
patterning and etching the second insulating layer to form a second contact opening to expose the conductive plug.
20. A semiconductor processing method according to claim 19 further comprising etching the second insulating layer with an etchant selective to both the first insulating layer and the conductive plug.
21. A semiconductor processing method according to claim 19 further comprising:
forming the first insulating layer of a nitride;
forming the conductive plug of polysilicon; and
etching the second insulating layer with an etchant selective to both the nitride insulating layer and the polysilicon plug.
22. A semiconductor processing method of forming an electrical contact structure for an active area on a semiconductor wafer, the method comprising the following steps:
providing a pair of conductive runners on a semiconductor wafer, individual conductive runners having sides;
providing an insulative layer on the mutually adjacent sides of the conductive runners, the insulated mutually adjacent sides of adjacent conductive runners being spaced a selected distance apart;
providing an active area between the insulated mutually adjacent sides of conductive runners;
providing a layer of first oxide to a selected thickness over the active area and conductive runners, the first oxide layer selected thickness being less than one-half the selected distance between the insulated sides of adjacent conductive runners;
providing a first insulating layer having a planarized upper surface atop the first oxide layer, the first insulating layer being selectively etchable relative to the first oxide, said step performed by,
providing a conformal first layer of insulating material atop the first oxide layers; and
polishing the wafer to planarize the first insulating layer upper surface;
patterning the first insulating layer for definition of a first contact opening therethrough to the active area;
etching the patterned first insulating layer selectively relative to the first oxide layer to define the first contact opening therethrough, the first contact opening having an aperture width at the first insulating layer planarized upper surface, the aperture width being greater than the selected distance between the insulated sides of adjacent conductive runners;
etching the first oxide layer within the first contact opening to expose the active area; and
providing a conductive plug within the first contact opening over the exposed active area.
23. A semiconductor processing method for making electrical contact with an active area on a semiconductor wafer comprising the steps of:
providing a pair of conductive runners on a semiconductor wafer, individual conductive runners having a top and sides;
providing insulative spacers on mutually adjacent sides of the runners, the insulative spacers being spaced a selected distance apart at a selected location on the wafer;
providing an active area between the conductive runners at the selected location;
depositing a first oxide layer over the wafer to a thickness from about 100 to 1,000 Angstroms, the first oxide layer having an upper surface defining a highest elevational location above the active area;
providing a nitride layer having an upper surface over the first oxide layer to a selected thickness, the nitride layer upper surface defining a lowest elevational location above the active area which is elevationally higher than the highest elevational location of the first oxide layer, the nitride being selectively etchable relative to the first oxide;
planarizing an upper surface of the nitride layer to a first elevational height above the active area, the first elevational height being higher than the highest elevational location of the first oxide layer upper surface;
patterning the nitride layer for definition of a first contact opening therethrough to the active area;
etching the patterned nitride layer selectively relative to the first oxide layer to define the first contact opening therethrough, the first contact opening having an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers at the mutually adjacent sides of the conductive runners;
etching the first oxide layer within the first contact opening to expose the active area;
providing a polysilicon plug within the first contact opening over the exposed active area to a second elevational height; and
depositing a second oxide layer over the nitride layer and the polysilicon plug.
24. A semiconductor processing method according to claim 23 wherein the step of planarizing the nitride layer comprises polishing the wafer to planarize the nitride layer.
25. A semiconductor processing method according to claim 23 wherein the step of providing a polysilicon plug comprises:
providing a layer of polysilicon over the nitride layer and within the first contact opening over the exposed active area; and
polishing the wafer to remove the polysilicon layer from the nitride layer upper surface and to define a polysilicon plug within the first contact opening.
26. A semiconductor processing method according to claim 23 further comprising etching the second oxide layer by an etchant selective to both the nitride layer and the polysilicon plug.
27. A method of providing electrical communication with a transistor including a source/drain, said method comprising:
providing a conductor over said source/drain that extends upward and is laterally surrounded by a first layer of insulation;
providing a second layer of insulation over said first layer of insulation, wherein said second layer of insulation is higher than said conductor and exposes said conductor; and
allowing electrical communication with said source/drain only by way of said conductor.
28. The method in claim 27, wherein said step of providing a conductor comprises providing a plug.
29. A method of processing a device comprising a transistor, said method comprising:
providing a plug in electrical communication with said transistor;
providing a conductive material in electrical communication with said plug; and
providing an insulating layer lateral to said conductive material, wherein said step of providing an insulating layer occurs before said step of providing a conductive material.
30. The method in claim 29, further comprising a step of providing a first insulating layer over said transistor; and wherein said step of providing an insulating layer lateral to said conductive material comprises providing a second insulating layer over said first insulating layer.
31. The method in claim 30, wherein said step of providing a conductive material is discrete from said step of providing a plug.
Description

Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 5,229,326. The reissue applications are U.S. application Ser. No. 09/488,099 (the present application) and U.S. application Ser. No. 08/504,943, now RE 36,518, of which the present application is a continuation.

TECHNICAL FIELD

This invention relates to semiconductor processing methods for making electrical contact with an active area and more particularly, for making electrical contact with an active area through sub-micron contact openings. This invention also relates to semiconductor devices having buried contact plugs.

BACKGROUND OF THE INVENTION

As semiconductor devices are scaled down to increase packing density, distances between adjacent components are becoming increasingly smaller. Sub-micron geometries are possible with currently available technologies. In some high-density memory devices, distances between adjacent word lines are required to be 0.4 micron or less to produce a sufficiently dense cell. At these geometries, problems arise when attempting to define contact openings to active areas between these adjacent, tightly spaced word lines. Present photolithographic alignment and metallization techniques are only possible to 0.35 micron features, with a misalignment error of ±0.15 micron. Without the use of self-aligned active area contacts, the minimum word line spacing would be approximately greater than 0.85 micron which is equal to the minimum photolithographic feature of 0.35 micron, plus twice the misalignment tolerance of 0.15 micron, plus twice the processing margin of 0.10 micron (or, 0.35 micron+2×0.15 micron+2×0.10 micron=0.85 micron). Present processing techniques are therefore incapable of producing narrow and properly aligned contact openings to active areas for geometries of 0.4 micron or less.

This invention provides a processing method for making contacts to active areas between semiconductor word line (conductive runners) having sub-micron geometries.

BRIEF DESCRIPTION OF THE DRAWINGS

One or more preferred embodiments of the invention are described below with reference to the following accompanying drawings.

FIG. 1 is a diagrammatic section of a semiconductor wafer shown at one processing step in accordance with the invention.

FIG. 2 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 1.

FIG. 3 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 2.

FIG. 4 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 3.

FIG. 5 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 5.

FIG. 6 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 5.

FIG. 7 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 6.

FIG. 8 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 7.

FIG. 9 is diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 8.

FIG. 10 is a diagrammatic section of the FIG. 1 wafer illustrated at a processing step subsequent to that shown in FIG. 7. FIG. 10 illustrates advantages of the present invention in diminishing problems associated with misalignment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

In accordance with one aspect of the invention, a semiconductor processing method of making electrical contact with an active area on a semiconductor wafer comprises the following steps:

providing a pair of conductive runners on a semiconductor wafer, individual conductive runners having sides;

providing an insulative layer on the sides of the conductive runners, the insulative sides of adjacent conductive runners being spaced a selected distance apart at a selected location on the wafer;

providing an active area between the conductive runners at the selected location;

providing a layer of first oxide to a selected thickness over the active area and conductive runners, the first oxide layer selected thickness being less than one-half the selected distance between the insulative sides of adjacent conductive runners;

providing a first planarized layer of insulating material atop the first oxide layer, the first layer of insulating material being selectively etchable relative to the first oxide, the first layer of insulating material having an upper surface;

patterning the planarized first insulating layer for definition of a first contact opening therethrough to the active area;

etching the patterned first insulating layer selectively relative to the first oxide layer to define the first contact opening therethrough, the first contact opening having an aperture width at the planarized first insulating layer upper surface, the aperture width being greater than the selected distance between the insulative sides of adjacent conductive runners;

etching the first oxide layer within the first contact opening to expose the active area;

providing a plug of conductive material within the first contact opening over the exposed active area;

providing a second insulating layer over the first insulating layer and the conductive plug;

patterning and etching the second insulating layer to form a second contact opening to and exposing the conductive plug; and providing a conductive layer over the second insulating layer and into the second contact opening, the conductive layer electrically contacting the conductive plug.

In accordance with another aspect of the invention, the step of providing a first planarized layer of insulating material comprises:

providing a conformal first layer of insulating material atop the first oxide layer; and

chemical mechanical polishing the wafer to planarize the first insulating layer.

In accordance with yet another aspect of the invention, a semiconductor device comprises:

conductive runners formed on the semiconductor wafer, individual runners having a top and sides;

insulative spacers provided on the sides of the conductive runners, the spacers of adjacent runners being spaced a selected distance apart at selected locations on the wafer;

active areas positioned between the conductive runners at the selected locations;

an insulating layer with an upper surface formed over the runners, the insulating layer having first contact openings between adjacent runners above the selected locations, the first contact openings having an aperture width at the upper surface which is greater than the selected distance;

conductive plugs disposed in the first contact openings to electrically contact the active areas, individual conductive plugs having a substantially flat upper surface, the upper surfaces of the conductive plugs being approximately uniform in elevational height across the wafer;

an oxide layer provided above the insulating layer and having second contact openings formed therethrough which extend to the upper surfaces of the conductive plugs; and

a conductive layer disposed above the oxide layer and in the second contact openings to electrically contact the conductive plugs.

A semiconductor processing method of making electrical contact with an active area on a semiconductor wafer is described with reference to FIGS. 1-9. The same numbers have been used throughout these figures to reference like parts.

In FIG. 1, a section of a semiconductor wafer 10 has bulk substrate 12, field oxide 14, and active areas 16 and 18. Conductive runners 20, 22, 24, and 26 are provided over wafer 10. Individual runners have a polysilicon layer 28, a silicide layer 30, and an oxide layer 32. Gate oxide layers are omitted for purposes of clarity. Individual runners 20, 22, 24, and 26 have respective tops 20a, 22a, 24a, and 26a and respective sides 20b/20c, 22b/22c, 24b/24c, and 26b/26c.

An insulative layer is provided over wafer 10, and then patterned and etched to define insulative spacers 34 on the sides of conductive runners 20, 22, 24, and 26. Insulative spacers 34 on the sides of adjacent conductive runners 20, 22 and 24, 26 are spaced a distance D apart at a selected location on wafer 10 in which a buried contact is eventually formed.

An impurity is implanted into substrate 12 to define source/drain regions 36, 38, 40, and 42. In subsequent steps discussed below, buried contact openings are formed to expose source/drain region 38 of active area 16 and source/drain region 40 of active area 18.

In FIG. 2, a first oxide layer 44 is provided over active areas 16 and 18 and conductive runners 20, 22, 24, and 26. First oxide layer 44 has a thickness less than one-half of distance D (FIG. 1) between insulative spacers 34 on the sides of adjacent conductive runners 20, 22 and 24, 26. First oxide layer 44 is preferably deposited to a thickness from about 100 to 1000 Angstroms, with a thickness from about 300 to 500 Angstroms being most preferred. First oxide layer 44 has an upper surface 46 with a contour conforming to the shape of the underlying semiconductor components. Upper surface 46 defines a highest elevational location K of first oxide layer 44 above active areas 16 and 18.

A thick conformal first layer of insulating material 48 is provided on top of first oxide layer 44. First insulating layer 48 is formed of a material which is selectively etchable relative to first oxide layer 44, and is preferably formed of a nitride. First insulating layer 48 has an upper surface 50 which generally follows the contour defined by the underlying topography of the runners and field oxide. Upper surface 50 defines a lowest elevational location H above active areas 16 and 18 which is elevationally higher than highest elevational location K of first oxide layer 44.

In FIG. 3, semiconductor wafer 10 undergoes chemical mechanical polishing (CMP) to planarize first insulating layer 48 and define a substantially flat upper surface 52. Planarized upper surface 52 is at an elevational location L above active areas 16 and 18 which is elevationally higher than highest elevational location K of first oxide layer 44. Although the preferred embodiment has been described as a two-step process involving depositing a conformal insulating layer followed by a CMP step to planarize the insulating layer, first insulating layer 48 may be deposited in a manner to provide a substantially planarized upper surface without the need for a subsequent CMP step.

In FIG. 4, first insulating layer 48 is patterned by a mask (not shown) and etched selectively relative to first oxide layer 44 to define first contact openings 54 and 56 between adjacent conductive runners 20, 22 and 24, 26 above respective source/drain regions 38 and 40 of active areas 16 and 18. First contact openings 54 and 56 have an aperture width W at or near upper surface 52 which is greater than distance D between insulative spacers 34 on the sides of adjacent conductive runners 20, 22 and 24, 26.

In FIG. 5, first oxide layer 44 is etched within first contact openings 54 and 56 to expose respective active areas 16 and 18, or more specifically, respective source/drain regions 38 and 40 of active areas 16 and 18. This etching step is preferably a timed etch, selective to silicon, which removes the thin oxide layer 44 without detrimentally etching into insulative spacers 34 or oxide caps 32.

In FIG. 6, plugs 58 and 60 are provided within respective first contact openings 54 and 56 over the exposed active areas 16 and 18. Plugs 58 and 60 are formed of a conductive material and electrically contact source/drain regions 38 and 40. Preferably, plugs 58 and 60 are formed of polysilicon. Plugs 58 and 60 have respective substantially flat upper surfaces 62 and 64 which are at an elevational height M above active areas 16 and 18. Height M is preferably approximately equal to, or slightly lower than, elevational height L of the insulating layer upper surface 52. Plug surfaces 62 and 64 are approximately uniform in elevational height across the semiconductor wafer. The advantages of this globally uniform height are discussed below in more detail.

One of the advantages of this invention is that plugs 58 and 60 have relatively large upper surface areas. The distance across plugs 58 and 60 at upper surfaces 62 and 64 is equal to width W of contact openings 54 and 56 (FIG. 4). This distance is significantly greater than distance D (FIG. 1) of the buried contact region near source/drain regions 34 and 40 of substrate 12. Accordingly, the process of this invention effectively replaces a narrow contact area near the active area with a large contact area.

According to one aspect of the invention, conductive plugs 58 and 60 are formed by providing a layer of conductive material (preferably polysilicon) over first insulating layer 48 and within first contact openings 54 and 56. The semiconductor wafer is then subjected to chemical mechanical polishing to remove the conductive layer from upper surface 52 of first insulating layer 48. All the conductive material is removed from upper surface 52 to electrically isolate individual plugs 58 and 60 and to prevent formation of undesired stray conductive traces between conductive plugs 58 and 60. To help insure that all conductive material is removed from upper surface 52, plugs 58 and 60 are over polished such that plug surfaces 62 ad 64 are slightly below first insulating layer upper surface 52. In this manner, individual plugs 58 and 60 are electrically isolated from one another.

An alternative technique to chemical mechanical polishing is to subject the layer of conductive material to a resist etch back process to define the slightly recessed plug surfaces 62 and 64 of respective plugs 58 and 60.

In FIG. 7, a second insulating layer 66 is provided over first insulating layer 48 and plugs 58 and 60. Second insulating layer 66 may be an oxide layer such as BPSG.

In FIG. 8, second insulating layer 66 is patterned beneath a mask (not shown) and etched to form second contact openings 68 and 70 which expose respective upper surfaces 62 and 64 of conductive plugs 58 and 60. Second insulating layer 66 is preferably dry etched with an etchant selective to both insulating layer 48 (which is preferably a nitride layer) and polysilicon plugs 58 and 60 (which are preferably polysilicon). Due to the relatively large surface areas of plugs 58 and 60 and the etch selectivity, conventional photolithographic techniques may be used to form second contact openings 68 and 70. First insulating layer 48 and oxide layer 44 assist in protecting conductive runners 20, 22, 24, and 26 during this etching step. The etchant may remove insulating layer 48 at a different rate than polysilicon plugs 58 and 60 as illustrated by surface level discontinuities 71 at the interface between insulating layer 48 and plugs 58 and 60.

In FIG. 9, a conductive layer 76 is provided over second insulating layer 66 and into second contact openings 68 and 70 to electrically contact plugs 58 and 60. Conductive layer 76 may be formed by polysilicon or metal.

Another advantage provided by this invention relates to misalignment tolerance. In FIG. 10, second insulating layer 66 is undesirably patterned and etched to form misaligned contact openings 72 an 74. Despite this misalignment, however, electrical contact with active areas 16 and 18 is still achieved through respective plugs 58 and 60 due to the large surface area at upper plug surfaces 62 and 64 (in comparison to the narrow distance D of the buried contact opening between adjacent runners near active areas 16 and 18). Additionally, etching second contact layer 66 with an etchant selective to both first insulating layer 48 and conductive plugs 58 and 60 permits significant misalignment while still protecting the underlying structure. The present invention therefore provides desirable misalignment tolerance which results in higher yields of processed semiconductor devices.

This invention defines a processing method for submicron geometries, and is most useful at geometries of less than 0.4 micron. The combined thin oxide and thick nitride layers afford a structure suitable for highly selective etching to define contact openings on the scale of 0.3 to 0.4 micron. The uniformly elevated and significantly wide landing plugs provide an easy target for conventional photolithographic techniques when forming the second contact openings. Additionally, the wide landing plugs provide misalignment tolerance which helps increase production yield.

In compliance with the statute, the invention has been described in language more or less specific as to methodical features. It is to be understood, however, that the invention is not limited to the specific features described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US3423646 *Feb 1, 1965Jan 21, 1969Sperry Rand CorpComputer logic device consisting of an array of tunneling diodes,isolators and short circuits
US3796926 *Mar 29, 1971Mar 12, 1974IbmBistable resistance device which does not require forming
US4099260 *Sep 20, 1976Jul 4, 1978Bell Telephone Laboratories, IncorporatedBipolar read-only-memory unit having self-isolating bit-lines
US4115872 *May 31, 1977Sep 19, 1978Burroughs CorporationAmorphous semiconductor memory device for employment in an electrically alterable read-only memory
US4174521 *Apr 6, 1978Nov 13, 1979Harris CorporationPROM electrically written by solid phase epitaxy
US4194283 *Aug 16, 1978Mar 25, 1980Siemens AktiengesellschaftProcess for the production of a single transistor memory cell
US4203123 *Dec 12, 1977May 13, 1980Burroughs CorporationThin film memory device employing amorphous semiconductor materials
US4227297 *Jul 31, 1978Oct 14, 1980Siemens AktiengesellschaftMethod for producing a single transistor storage cell
US4272562 *Jun 19, 1979Jun 9, 1981Harris CorporationMethod of fabricating amorphous memory devices of reduced first fire threshold voltage
US4458260 *Nov 20, 1981Jul 3, 1984Rca Inc.Avalanche photodiode array
US4502208 *Aug 26, 1983Mar 5, 1985Texas Instruments IncorporatedMethod of making high density VMOS electrically-programmable ROM
US4569698 *May 31, 1985Feb 11, 1986Raytheon CompanyMethod of forming isolated device regions by selective successive etching of composite masking layers and semiconductor material prior to ion implantation
US4617193Jun 16, 1983Oct 14, 1986Digital Equipment CorporationPlanar interconnect for integrated circuits
US4714686Jul 31, 1985Dec 22, 1987Advanced Micro Devices, Inc.Method of forming contact plugs for planarized integrated circuits
US4757359 *Apr 7, 1986Jul 12, 1988American Microsystems, Inc.Thin oxide fuse
US4804490 *Oct 13, 1987Feb 14, 1989Energy Conversion Devices, Inc.Subjecting chalcogenide galss to hydrogenated atmosphere
US4809044 *Nov 26, 1986Feb 28, 1989Energy Conversion Devices, Inc.Thin film overvoltage protection devices
US4823181 *May 9, 1986Apr 18, 1989Actel CorporationProgrammable low impedance anti-fuse element
US4868138Mar 23, 1988Sep 19, 1989Sgs-Thomson Microelectronics, Inc.Method for forming a self-aligned source/drain contact for an MOS transistor
US4876220 *Nov 13, 1987Oct 24, 1989Actel CorporationMethod of making programmable low impedance interconnect diode element
US4876668 *Apr 29, 1986Oct 24, 1989California Institute Of TechnologyThin film memory matrix using amorphous and high resistive layers
US4881114 *May 16, 1986Nov 14, 1989Actel CorporationSelectively formable vertical diode circuit element
US4892840 *Apr 11, 1989Jan 9, 1990Texas Instruments IncorporatedElectrically programmable read only memory, semiconductors
US4892845Aug 31, 1984Jan 9, 1990Texas Instruments IncorporatedMethod for forming contacts through a thick oxide layer on a semiconductive device
US5110766Jul 6, 1990May 5, 1992Kabushiki Kaisha ToshibaMethod of manufacturing a semiconductor device including forming a flattening layer over hollows in a contact hole
US5124280Jan 31, 1991Jun 23, 1992Sgs-Thomson Microelectronics, Inc.Depositing polycrystalline silicon dielectric, patterning, converting part of patterned layer ot conductive silicide
US5144404 *Aug 22, 1990Sep 1, 1992National Semiconductor CorporationPolysilicon Schottky clamped transistor and vertical fuse devices
US5158910Nov 26, 1990Oct 27, 1992Motorola Inc.Process for forming a contact structure
US5166096 *Apr 14, 1992Nov 24, 1992International Business Machines CorporationProcess for fabricating self-aligned contact studs for semiconductor structures
US5166758 *Jan 18, 1991Nov 24, 1992Energy Conversion Devices, Inc.Electrically erasable phase change memory
US5171713Jan 28, 1991Dec 15, 1992Micrunity Systems EngProcess for forming planarized, air-bridge interconnects on a semiconductor substrate
US5177567 *Jul 19, 1991Jan 5, 1993Energy Conversion Devices, Inc.Thin-film structure for chalcogenide electrical switching devices and process therefor
US5296716 *Aug 19, 1991Mar 22, 1994Energy Conversion Devices, Inc.Electrically erasable, directly overwritable, multibit single cell memory elements and arrays fabricated therefrom
US5335219 *Sep 30, 1991Aug 2, 1994Ovshinsky Stanford RHomogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements
US5341328 *Jun 15, 1992Aug 23, 1994Energy Conversion Devices, Inc.Electrically erasable memory elements having reduced switching current requirements and increased write/erase cycle life
US5359205 *May 8, 1992Oct 25, 1994Energy Conversion Devices, Inc.Electrically erasable memory elements characterized by reduced current and improved thermal stability
US5510629 *May 27, 1994Apr 23, 1996Crosspoint Solutions, Inc.Multilayer antifuse with intermediate spacer layer
DE4107883A1Mar 12, 1991Sep 19, 1991Mitsubishi Electric CorpSemiconductor device - contains gate electrodes formed on insulation regions between impurity regions
EP0117045A2 *Jan 13, 1984Aug 29, 1984OIS Optical Imaging Systems, Inc.Liquid crystal flat panel display
GB1319388A * Title not available
JPS6232630A Title not available
JPS6472543A Title not available
JPS60109266A * Title not available
Non-Patent Citations
Reference
1 *Kim and Kim, "Effects of High Pulses on Polycrystalline Silicon Diode with n-type Region Heavily Doped with Both Boron and Phosphorus," J. Appl. Phys., 53(7):5359-5360, 1982, No month.
2 *Neale and Aseltine, "The Application of Amorphous Materials to Computer Memories," IEEE, 20(2):195-205, 1973, No month.
3 *Oakley et al., "Pillars-The Way to Two Micron Pitch Multilevel Metallization," IEEE, 23-29, 1984, No month.
4 *Pein and Plummer, "Performance of the 3-D Sidewall Flash EPROM Cell," IEEE, 11-14, 1993, No month.
5 *Post and Ashburn, "Investigation of Boron Diffusion in Polysilicon and its Application to the Design of p-n-p Polysilicon Emitter Bipolar Transistors with Shallow Emitter Junctions," IEEE, 38(11):2442-2451, 1991, No month.
6 *Post and Ashburn, "The Use of an Interface Anneal to Control the Base Current and Emitter Resistance of p-n-p Polysilicon Emitter Bipolar Transistors," IEEE, 13(8):408-410, 1992, No month.
7 *Post et al., "Polysilicon Emitters for Bipolar Transistors: A Review and Re-Evaluation of Theory and Experiment," IEEE, 39(7):1717-1731, 1992, No month.
8 *Rose et al., "Amorphous Silicon Analogue Memory Devices," J. Non-Crystalline Solids, 115:168-170, 1989, No month.
9 *Schaber et al., "Laser Annealing Study of the Grain Size Effect in Polycrystalline Silicon Schottky Diodes," J. Appl. Phys., 53(12):8827-8834, 1982, No month.
10 *Yamamoto et al., "The I-V Characteristics of Polycrystalline Silicon Diodes and the Energy Distribution of Traps in Grain Boundaries," Electronics and Communications in Japan, Part 2, 75(7):51-58, 1992, No month.
11 *Yeh et al., "Investigation of Thermal Coefficient for Polycrystalline Silicon Thermal Sensor Diode," Jpn. J. Appl. Phys., 31(Part 1, No. 2A):151-155, 1992, No month.
12Yoshire Nakata et al., "Tunnel Shape Stacked Capacitor (TSSC) Memory Cell for 64Mb Dram", article (date unknown).
Classifications
U.S. Classification438/586, 438/633, 438/692, 438/524
International ClassificationH01L21/44, H01L21/60, H01L23/485, H01L21/48, H01L23/522
Cooperative ClassificationH01L23/485, H01L23/5226, H01L21/76897
European ClassificationH01L21/768S, H01L23/522E, H01L23/485