|Publication number||USRE40904 E1|
|Application number||US 10/412,827|
|Publication date||Sep 1, 2009|
|Filing date||Apr 14, 2003|
|Priority date||Nov 2, 1990|
|Also published as||DE69118392D1, DE69118392T2, EP0555382A1, EP0555382B1, WO1992008186A1|
|Publication number||10412827, 412827, US RE40904 E1, US RE40904E1, US-E1-RE40904, USRE40904 E1, USRE40904E1|
|Original Assignee||Analog Devices, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (25), Non-Patent Citations (2), Referenced by (4), Classifications (17)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application Ser. No. 07/368,365, filed Nov. 2, 1990, now abandoned.
The invention relates to the field of digital buffers and, more particularly, to the generation of addresses for accessing digital buffers. Even more particularly, the invention relates to the generation of addresses for accessing circular buffers.
Digital information processors frequently employ digital memory buffers to temporarily store information en route to another device such as an input/output device or processor. A buffer may be constructed of dedicated hardware registers wired together or it may simply be a dedicated section of a larger memory. Such digital information buffers can take many forms. One such form is known as a circular buffer. In circular buffers, the addresses for accessing locations in the buffers typically are generated by modifying the contents of a pointer register which is external to the buffer area which points to an address location within the buffer. When that address is needed on the address bus, it is output from the pointer address and the pointer is incremented (or decremented) by a predetermined amount so as to be ready for the next instruction cycle which accesses the circular buffer. In circular buffers, means must be provided for “wrapping” the address around when the increment (or decrement) causes the address in the pointer register to fall without the bounds of the buffer. In other words, means must be provided for causing the address generator for the buffer to generate modulo addresses with the modulus being the length of the buffer.
In circular buffers, software techniques are generally used for the modulo address generation. These software address mapping techniques, however, require several instruction cycles to perform the necessary address comparisons, arithmetic operations and replacement of the pointer register contents. Such software address mapping is not fast enough for certain types of uses. Applications such as digital filters, Fast Fourier transforms, matrix manipulations and other common digital signal processing routines require a very rapid generation of memory references. Accordingly, software modulo address generation can significantly decrease the speed of fast signal processing apparatus. Accordingly, addressing schemes implemented in hardware are sometimes desirable.
One such hardware implemented system is disclosed in U.S. Pat. No. 4,800,524. The apparatus described in U.S. Pat. No. 4,800,524 comprises three registers external to the buffer, including (1) an L register which contains the length of the buffer, (2) an A register which contains the last address accessed in the buffer (this is the pointer register) and (3) an M buffer which contains an increment (or decrement) value to be added (or subtracted) from the A register. The apparatus also comprises two separate adder/subtractors, the first of which generates an absolute buffer address which is simply the contents of the A register added to the contents of the M register and a second adder/subtractor which generates a wrapped address by either adding (if M is positive) or subtracting (if M is negative) from the absolute address generated by the first adder the length of the buffer. Additional logic selects either the absolute address or the wrapped address responsive to the carry bits from the first and second adders. If the carry bits indicate that the absolute address generated is outside the boundaries of the buffer, the wrapped address is used and placed in the A register ready for the next access. Otherwise, the absolute address is selected and placed in the A register. The invention disclosed in the U.S. Pat. No. 4,800,524 patent is limited, however, in that in order for the system of examining the carry bits to work, the lower K bits of the buffer's base address (lowest address) must be zero, where K is the number of bits required to represent the length of the buffer and the length of the buffer must be a power of two. These limitations can be extremely inconvenient in certain applications.
It is one object of the present invention to provide an improved address generator for a circular buffer.
It is a further object of the present invention to provide an address generator for a circular buffer which places no restrictions on the size or the position in memory of the circular buffer.
It is another object of the present invention is to provide an address generator for a circular buffer which is substantially faster than software address generators.
The address generator of the present invention comprises four registers. In one preferred embodiment, the registers are as follows:
In alternate embodiments, the Base or Length registers, but not both, can be replaced by an End register, E, which contains the highest address in the buffer.
In the preferred embodiment, when the circuit buffer is accessed by an instruction, the contents of the Index register are placed on the address bus and then the Index register is modified so as to be ready for the next access. When the modify value, M, is positive, adder/subtracters calculate the value of I+M (the absolute address) as well as I+M−L, (the wrap address). The output of the adder/subtractor which calculates I+M−L is compared to the output of register B. The output of the adder/subtractor which calculates I+M and the output of the adder/subtracter which calculates I+M−L are also placed as first and second inputs to a multiplexer. The output of the multiplexer is coupled to the input of the I register so as to select one of those two values as the new index value. If I+M−L is greater than or equal to B, the comparator controls the multiplexer to select the I+M−L input as the value to be loaded into the index register. Otherwise, the comparator controls the multiplexer to select the I+M input.
Alternate embodiments are possible where either the Length register or the Base register is replaced by an End register which contains the end value (i.e., the highest numbered address) of the buffer. Slight modification to the adder/subtracter circuitry would be necessary. In addition, any of these embodiments can be further modified for a system in which the modifier M is a negative value or where M may be positive or negative.
As stated above, in a circular buffer, means must be provided for wrapping the index pointer around when the increment amount would cause the index pointer to exceed the bounds of the buffer. For instance, in
In most circular buffer applications, the buffer pointer, i.e., the I register, is incremented the same amount every time. Accordingly, a number can be permanently stored in the M register 19. In situations where the increment, M, may vary, a multiplexer 20 is provided. Under the control of a processor (not shown), to avoid unnecessary obfuscation, multiplexer 20 can select as the increment either the data placed on the data bus by the processor or the output of the M register 19.
The contents of the I register 16 are placed onto the address bus 26 in response to a processor instruction such as the IWREN signal 28 in FIG. 2. The logic in the address generator of the present invention will then modify the contents of the I register so that it will be ready for the next access into the circular buffer. Accordingly, an instruction cycle instructing the I register to output its contents onto the address bus initiates the sequence to be described herein for modifying the contents of the I register.
As the contents of the I register are output onto the data bus, they are also fed into one input of an adder 22. The other input of the adder is coupled to the output of the multiplexer 20 which contains the selected increment, M0 The value I+M is output from the adder 22 and fed to one input of adder/subtractor 27. At its other input, adder/subtractor 27 accepts the output of the L register which contains the length of the buffer. In the case where M is always positive, the adder/subtractor is set up to subtract L from I+M. However, if M is negative, then the adder/subtractor is set up to add the value of L to I+M.
If M is positive, then the value of I+M−L is compared with the base address, B, of the circular buffer by comparator 30, as shown in FIG. 2. The output of comparator 30 is the control signal to multiplexer 32. Multiplexer 32 receives at input A the value of I+M−L output from adder/subtractor 27 and at input B the value of I+M output from adder 22. The comparator determines if I+M−L is greater than or equal to B. If so, the comparator 30 outputs a signal which instructs the multiplexer to place at its output the value at its A input, I+M−L. Otherwise, the comparator instructs the multiplexer 32 to place at its output, the value at its B input, I+M. The output of the multiplexer is fed back to the input of the I register and represents the new pointer address which will be stored in the I register.
The purpose of the above-described operation of adder 22, adder/subtractor 27, comparator 30 and multiplexer 32 is explained as follows. The value of I+M output from adder 22 represents the new absolute value of the pointer (i.e., the old pointer value plus the increment M, regardless of whether it is within the bounds of the buffer). If the absolute value is within the range of the buffer, then no “wrapping around” is necessary and it can be placed directly into the I register. However, if it is beyond the range of the buffer, then the length of the buffer, L, must be subtracted from the absolute value in order to “wrap around” the address to modulo style. Adder/subtractor 27 calculates I+M−L whether it will be needed or not. Obviously, if I+M is within the buffer range, then subtracting the length, L, of the buffer from the absolute address will cause the address to be less than the base address of the buffer, thus indicating that “wrapping” is unnecessary. However, if I+M is beyond the bounds of the buffer, then I+M−L will be greater than or equal to the base address, B, of the buffer. Accordingly, comparator 30 determines if I+M−L is greater than or equal to the base address, B. If so, then I+M must have been beyond the range of the buffer and the comparator causes multiplexer 32 to place in the I register the value of I+M−L, rather than the value of I+M.
If M is negative, the operation is slightly modified. In this situation, the adder/subtractor 27 calculates the value of I+M (M being negative)+L instead of I+M−L, and the B register contains the highest numbered, rather than lowest numbered, address in the buffer. Accordingly, the comparator operation also must be modified so that, if the value as its A input, I+M+L, is less than or equal to the value at its B input, the highest address in the buffer, B, then it instructs the multiplexer 30 to select I+M+L. Otherwise it selects its other input, I+M.
As described above, depending on the sign of M, the adder/subtractor 27 and the comparator 30 perform slightly different operations. However, from a manufacturing standpoint, it is desirable to produce a single address generator which can be used in applications where M is positive or negative, rather than producing a separate device for each situation. Accordingly, in the preferred embodiment, adder/subtractor 27 and comparator 30 are designed to perform the separate above-described functions responsive to the sign bit of the contents of the M register. Accordingly, not only is the address generator capable of handling both of these situations (where M is positive or where M is negative), but, with a small amount of additional circuitry, it will also function properly where the sign of M can change during operation as discussed below.
Although the description of the invention above has been limited to situations where M is either known to be positive or negative, there are applications where the offset, M, can change from positive to negative during operation. For example, in the fast generation of phase values in high speed spread spectrum systems, the direction of movement in the circular buffer can change. Similarly, in phase locked loop situations, the direction of the offset can change. The present invention can be adapted to handle such situations. One possible adaptation would be to provide a further adder which adds the contents of the B register and the L register to derive the highest numbered address in the buffer and a further multiplexer responsive to the sign bits of M for selecting either the output of the B register (defined herein as the lowest address in the buffer) or the output of the additional adders as an input to the comparator 30. The adder/subtracter is also responsive to the sign bit of the register for subtracting L from I+M, when the sign bit of M is positive or adding L to the I+M value, when the sign bit is negative. The comparator also is responsive to the sign bit. In the case where M is positive, if the comparator determines that its A input, I+M−L, is greater than or equal to its B input, the base address, B, then it instructs the multiplexer 32 to select its A input, I+M−L. However, if M is negative, the comparator output must be modified such that when the A input of the comparator, I+M+L, is less than or equal to the B input of the comparator, B+L, then the multiplexer must be instructed to select its A input, I+M, and its B input, I+M+L otherwise.
The speed of the calculation of the address can be further increased with a slight modification to the circuitry shown in FIG. 2. As shown in
Additional alternate embodiments of the invention are shown in
When M is positive, comparator 44 compares I+M−B+E to B. If I+M−E+B is less than or equal to B, then comparator 44 controls multiplexer 32 to select its A input, having the value I+M−E+B. Otherwise, multiplexer 32 is controlled by comparator 44 to select its B input, having the value I+M. When M is negative, the adder/subtractor 42 still calculates I+M−E+B and the comparator still compares I+M−E+B with the contents of the B register, but now must determine if I+M−E+B is less than or equal to B. If so, comparator 44 instructs multiplexer 32 to select its A input, the value I+M−E+B. Otherwise, multiplexer 32 is controlled by comparator 44 to select its B input, the value I+M. Minor modifications are necessary if M may be either positive or negative during operation.
In the embodiment of
The embodiment of
Having thus described a few particular embodiments of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art. Such alterations, modifications and improvements as are made obvious by this disclosure are intended to be part of this description though not expressly stated herein, and are intended to be within the spirit and scope of the invention. Accordingly, the foregoing description is by way of example only, and not limiting. The invention is limited only as defined in the following claims and equivalents thereto.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US3461433 *||Jan 27, 1967||Aug 12, 1969||Sperry Rand Corp||Relative addressing system for memories|
|US3813652 *||Jan 15, 1973||May 28, 1974||Honeywell Inf Systems||Memory address transformation system|
|US3931611 *||Dec 10, 1973||Jan 6, 1976||Amdahl Corporation||Program event recorder and data processing system|
|US3999052 *||Jun 18, 1975||Dec 21, 1976||International Business Machines Corporation||Upper bounds address checking system for providing storage protection for a digital data processor|
|US4169289 *||Jul 8, 1977||Sep 25, 1979||Bell Telephone Laboratories, Incorporated||Data processor with improved cyclic data buffer apparatus|
|US4187549 *||Sep 5, 1978||Feb 5, 1980||The United States Of America As Represented By The Secretary Of The Navy||Double precision residue combiners/coders|
|US4202035 *||Nov 25, 1977||May 6, 1980||Mcdonnell Douglas Corporation||Modulo addressing apparatus for use in a microprocessor|
|US4251860 *||Oct 23, 1978||Feb 17, 1981||International Business Machines Corporation||Virtual addressing apparatus employing separate data paths for segment and offset portions of a virtual address and utilizing only the offset portion to calculate virtual address|
|US4408274 *||Sep 29, 1980||Oct 4, 1983||Plessey Overseas Limited||Memory protection system using capability registers|
|US4432054 *||Aug 28, 1981||Feb 14, 1984||Hitachi, Ltd.||Loop data transmission control method and system|
|US4453209 *||Mar 24, 1980||Jun 5, 1984||International Business Machines Corporation||System for optimizing performance of paging store|
|US4453212 *||Jul 13, 1981||Jun 5, 1984||Burroughs Corporation||Extended address generating apparatus and method|
|US4485435 *||Mar 9, 1981||Nov 27, 1984||General Signal Corporation||Memory management method and apparatus for initializing and/or clearing R/W storage areas|
|US4623997 *||Dec 13, 1984||Nov 18, 1986||United Technologies Corporation||Coherent interface with wraparound receive and transmit memories|
|US4627017 *||May 2, 1983||Dec 2, 1986||International Business Machines Corporation||Address range determination|
|US4722067 *||Mar 25, 1985||Jan 26, 1988||Motorola, Inc.||Method and apparatus for implementing modulo arithmetic calculations|
|US4724479 *||Mar 29, 1985||Feb 9, 1988||Deutsche Gesselschaft fur Wiederfarbeitung von Kernbrennstoffen mbH||Shielded, highly radioactive, wet chemical cell for an atomic plant with a contrivance for drip leakage recognition and method for use in a cell of this type|
|US4800524 *||Dec 2, 1987||Jan 24, 1989||Analog Devices, Inc.||Modulo address generator|
|US4809156 *||May 13, 1987||Feb 28, 1989||Trw Inc.||Address generator circuit|
|US4819165 *||Mar 27, 1987||Apr 4, 1989||Tandem Computers Incorporated||System for performing group relative addressing|
|US4833602 *||Jun 29, 1987||May 23, 1989||International Business Machines Corporation||Signal generator using modulo means|
|US4908748 *||Jul 28, 1987||Mar 13, 1990||Texas Instruments Incorporated||Data processing device with parallel circular addressing hardware|
|US4935867 *||Mar 4, 1986||Jun 19, 1990||Advanced Micro Devices, Inc.||Signal processor memory management unit with indirect addressing using selectable offsets and modulo values for indexed address calculations|
|JPS61289440A *||Title not available|
|WO1979000035A1 *||Jun 22, 1978||Feb 8, 1979||Western Electric Co||Apparatus for use with a data processor for defining a cyclic data buffer|
|1||*||English translation of Japanes patent application No. Sho 61-289440.|
|2||*||TMS320C30 Data Book, pp. 6-5, 6-6, and 6-22 through 6-25, Aug. 1988.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8510503 *||Jan 6, 2010||Aug 13, 2013||Renesas Electronics Corporation||Ring buffer circuit and control circuit for ring buffer circuit|
|US9141569||Jan 10, 2013||Sep 22, 2015||International Business Machines Corporation||Tracking a relative arrival order of events being stored in multiple queues using a counter|
|US9189433||Dec 18, 2012||Nov 17, 2015||International Business Machines Corporation||Tracking a relative arrival order of events being stored in multiple queues using a counter|
|US20100174877 *||Jan 6, 2010||Jul 8, 2010||Nec Electronics Corporation||Ring buffer circuit and control circuit for ring buffer circuit|
|U.S. Classification||711/110, 711/217, 711/219, 711/218, 711/220|
|International Classification||G06F5/06, G06F9/355, G06F12/00, G06F7/72, G06F5/10, G06F12/02|
|Cooperative Classification||G06F2205/106, G06F5/10, G06F7/72, G06F9/3552|
|European Classification||G06F9/355B, G06F5/10|