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Publication numberUSRE40939 E1
Publication typeGrant
Application numberUS 10/929,152
Publication dateOct 20, 2009
Filing dateAug 27, 2004
Priority dateJun 14, 1999
Fee statusPaid
Also published asUS6442225
Publication number10929152, 929152, US RE40939 E1, US RE40939E1, US-E1-RE40939, USRE40939 E1, USRE40939E1
InventorsChen-Chih Huang
Original AssigneeRealtek Semiconductor Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Multi-phase locked loop for data recovery
US RE40939 E1
Abstract
The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (upk/dnk) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error θe and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.
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Claims(19)
1. A multi-phase-locked loop for data recovery comprising a phase detector, a charge pump, a loop filter and a voltage controlled oscillator, wherein:
said phase detector is constituted by N phase detection units (U1, U2, . . . , UN, N is even, N≧4); said N phase detection units are connected in cascade configuration, and each phase detection unit contains:
a data signal input terminal for receiving a data signal from outside;
a clock signal input terminal for receiving the one of multi-phase clock signals (CK1, CK2, . . . , CKN) from outside;
a delay signal input terminal for receiving a delay signal output from another phase detection unit;
a delay signal output terminal for outputting a delay signal of the phase detection unit; and
a charge/discharge control signal output terminal for outputting a control signals for charge/discharge operations;
each of said N phase detection units generates a delay signal (D1, D2, . . . , DN) according to an input the data signal and the complement of a the multi-phase clock signal; the delay signal (Dj+1) generated by the (j+1)th phase detection unit is input into the jth phase detection unit via the jth delay signal input terminal; the delay signal (D1) generated by the first phase detection unit is input into the Nth phase detection unit via the Nth delay signal input terminal;
the jth phase detection unit (Uj ′ U j, 1≦j<N, j is a positive integer) generates one of the control signals (dn1, dn2, . . . , dnN/2, upN/2, . . . , up2) for charge/discharge operations according to the delay signal (Dj) from the jth phase detection unit, the delay signal (Dj+1) from the (j+1)th phase detection unit, and the multi-phase clock signal (CKj) which is applied to the jth phase detection unit;
the Nth phase detection unit generates a charge control signal (up1) according to the delay signal (Dn) from the Nth phase detection unit, the delay signal (D1) from the first phase detection unit, and the multi-phase clock signal (CKN) which is applied to the Nth phase detection unit;
said charge pump being constituted by N/2 charge and discharge units (CP1, CP2, . . . , CPN/2), wherein the kth (CPk, 1≦k≦N/2) charge and discharge unit (CPk) is employed to receive the kth charge/discharge control signal set (upk/dnk) from said phase detector, and a current Ichk is generated by the charge/discharge control signal set (upk/dnk); the charge/discharge current Ichk=(wkupk−wkdnk)Iss, wherein wk is a weighting value, Iss is a fixed current value, and w1<w2< . . . <wN/2; the total charge/discharge current (Ich) from said charge pump equals to Ich1+Ich2+ . . . Ichk+ . . . +IchN/2; and
said voltage controlled oscillator is a multi-phase voltage controlled oscillator, which outputs N multi-phase clock signals (CK1, CK2 . . . , CKN), which are applied to said phase detectors phase detection units, respectively.
2. The multi-phase-locked loop for data recovery as described in claim 1, wherein the phase difference between the multi-phase clock signal (CKj+1) input to the (j+1)th phase detection unit (Uj+1) and the multi-phase clock signal (CKj) input to the je phase detection unit (Uj) equals to 2π/N.
3. The multi-phase-locked loop for data recovery as described in claim 1, wherein each of said N phase detection unit comprises: an inverter, a first flip-flop, an exclusive OR gate, and a second flip-flop;
said inverter inverting multi-phase clock signal which is to be input to each phase detection unit; the first flip-flop generating a delay signal according to the complementary multi-phase clock signal from said inverter and the data signal; the delay signal from said first flip-flop and the delay signal from the first flip-flop in another phase detection unit being input to the exclusive OR gate; the second flip-flop generating a charge/discharge control signal according to the multi-phase clock signal and the output signal from said exclusive OR gate.
4. The multi-phase-locked loop for data recovery as described in claim 3, wherein said first flip-flop and said second flip-flop are D flip-flops.
5. A multi-phase-locked loop comprising:
a phase detector configured to:
receive a data signal and a plurality of multi-phase clock signals;
detect a phase difference between the data signal and each multi-phase clock signal; and
output a plurality of control signals;
a charge pump, configured to receive the control signals and produce a total control current according to the control signals, the charge pump comprising a plurality of charge/discharge units, wherein at least one of charge/discharge units comprises a first current source, a second current source, and a switch module, and wherein each charge/discharge unit has a weighting value, and at least two of the weighting values are different;
a loop filter configured to receive the total control current and produce a control voltage according to the total control current; and
a voltage controlled oscillator (VCO) configured to produce the multi-phase clock signals according to the control voltage, wherein the multi-phase clock signals are at substantially the same frequency.
6. The multi-phase-locked loop of claim 5 , wherein the charge pump is controlled by the control signals such that the relation between the control voltage and the phase difference of the multi-phase-locked loop is adjusted to be nearly linear.
7. The multi-phase-locked loop of claim 5 , wherein the control signals are maintained as a fixed time period such that a dead zone of the multi-phase-locked loop is reduced.
8. The multi-phase-locked loop of claim 5 , wherein the control signals are maintained as a fixed time period such that jitter of the multi-phase clock signal is reduced.
9. A multi-phase-locked loop comprising:
a phase detector configured to:
receive a data signal and a plurality of multi-phase clock signals;
detect a phase different between the data signal and each multi-phase clock signal; and
output a plurality of control signals;
a charge pump, configured to receive the control signals and produce a total control current according to the control signals;
said charge pump including a first current source, a second current source, and a switch module;
a loop filter configured to receive the total control current and produce a control voltage according to the total control current; and
a voltage controlled oscillator (VCO) configured to produce the multi-phase clock signals according to the control voltage, wherein the multi-phase clock signals are at substantially the same frequency, wherein the phase detector comprises N phase detection units (N is even, N>=4 ), the N phase detection units being coupled in cascade configuration.
10. The multi-phase-locked loop of claim 9 , wherein a phase difference between a first multi-phase clock signal and a second multi-phase clock signal adjacent to the first multi-phase clock signal is 2π/N.
11. The multi-phase-locked loop of claim 9 , wherein each phase detection unit comprises:
a first flip-flop configured to generate a delay signal according to the corresponding multi-phase clock signal and the data signal;
an exclusive OR gate configured to receive the delay signal from the first flip-flop and another delay signal from another first flip-flop in another phase detection unit; and
a second flip-flop configured to output one of the plurality of control signals according to an output signal of the exclusive OR gate and the corresponding multi-phase clock signal.
12. The multi-phase-locked loop of claim 11 , wherein the first flip-flop and the second flip-flop are D flip-flops.
13. The multi-phase-locked loop of claim 5 , wherein each charge/discharge unit is configured to generate an output current according to the corresponding control signal,
wherein the charge pump is configured to receive the output currents and produce the total control current.
14. A phase detector for detecting phase differences between a data signal and a plurality of multi-phase clock signals and producing a plurality of control signals, wherein the frequencies of the multi-phase clock signals are substantially the same, the phase detector comprising:
a plurality of phase detection units, the phase detection units being coupled in cascade configuration, wherein each of the phase detection units comprises:
a first flip-flop configured to generate a delay signal according to the corresponding multi-phase clock signal and the data signal;
an exclusive OR gate configured to receive the delay signal from the first flip-flop and another delay signal from another first flip-flop in another phase detection unit; and
a second flip-flop configured to generate one of the plurality of control signals according to an output signal of the exclusive OR gate and the corresponding multi-phase clock signal.
15. The multi-phase-locked loop of claim 5 , wherein the charge pump is configured to produce a plurality of output currents according to the control signals, and the charge pump is configured to produce the total control current according to the output currents.
16. The multi-phase-locked loop of claim 15 , wherein each output current has a corresponding weighting value, and at least two of the weighting values are different.
17. The multi-phase-locked loop of claim 15 , wherein the charge pump includes a plurality of switching devices controlled by the control signals, and the charge pump produces the output currents selectively through the switching devices.
18. The multi-phase-locked loop, comprising:
a phase detector configured to:
receive a data signal and a plurality of multi-phase clock signals;
detect a phase difference between the data signal and each multi-phase clock signal; and
output a plurality of control signals;
a charge pump, configured to receive the control signals and produce a total control current according to the control signals;
a loop filter configured to receive the total control current and produce a control voltage according to the total control current; and
a voltage controlled oscillator (VCO) configured to produce the multi-phase clock signals according to the control voltage, wherein the multi-phase clock signals are at substantially the same frequency;
wherein the charge pump comprises a plurality of charge/discharge units, each charge/discharge unit has a corresponding weighting value, and at least two of the weighting values are different.
19. The multi-phase-locked loop of claim 5 , wherein the phase detector comprises:
a plurality of phase detection units, the phase detection units being coupled in cascade configuration, wherein each of the phase detection units comprises:
a first flip-flop configured to generate a delay signal according to the corresponding multi-phase clock signal and the data signal;
a logic circuit configured to receive the delay signal from the first flip-flop and another delay signal from another first flip-flop in another phase detection unit; and
a second flip-flop configured to generate one of the plurality of control signals according to an output signal of the logic circuit and the corresponding multi-phase clock signal.
Description
FIELD OF THE INVENTION

The present invention relates generally to a phase-locked loop for data recovery, and more particularly, to a multi-phase-locked loop that utilizes a multi-phase clock signal generated by a multi-phase voltage controlled oscillator (VCO) to detect received data.

BACKGROUND OF THE INVENTION

Due to the development of the network transmission technology as well as the demands in the installed base of computer networks, the network data transmission rate in hardware environment has been increased. Therefore, it becomes more and more important to recover data (clock signals) correctly.

At present, while data (clock) recovery is to be performed, a phase-locked loop is often utilized. During the data recovery process, usually the received data could be correctly recovered (read) by using a phase detector to synchronize the received data and recover the clock. In other words, the phase detector plays a very important role whether the data could be correctly recovered by a phase-locked loop.

FIG. 1 illustrates a prior art phase-locked loop for data recovery comprising a phase detector 11, a charge pump 12, a loop filter 13, and a voltage controlled oscillator 14. The phase detector 11 is used to receive a data (clock) signal from outside as well as a feedback clock signal CKvco from the voltage controlled oscillator 14. The phase detector 11 compares the two signals, in accordance with their phase difference θe edata−θclock), a control signal up or dn will be output to control the charge pump 12. As shown in FIG. 2(a), when the transition edge of the data (clock) signal data leads the falling edge of the feedback clock signal CKvco, the phase detector outputs an up signal. On the other hand, as shown in FIG. 2(b), when the transition edge of the data (clock) signal data lags behind the falling edge of the feedback clock signal CKvco, the phase detector 11 outputs a dn signal. The charge pump 12 is controlled by the up and dn control signals output from the phase detector 11 to perform charge/discharge operations, and generates a voltage signal Vd. The loop filter 13 receives the voltage signal Vd and generates an appropriate voltage Vc for controlling the voltage controlled oscillator 14. The voltage controlled oscillator 14 receives the voltage Vc and generates a clock signal CKvco to be input to the phase detector 11.

As shown in FIG. 3, the phase detector 11 of the phase locked loop 1 is constituted by four flip-flops 111, 112, 113,114, and two OR gates 115, 116. The flip-flops 111 and 112 receive the complement of data from outside (denoted by data) and the data itself (denoted by data), respectively. The clock signal CKvco from the voltage controlled oscillator 14 is applied to the inversion reset terminals (rb) of the flip-flops 111 and 112 such that two control signals up1 and up2 are generated, respectively. The flip-flops 113 and 114 receive the complement of data from outside (denoted by data) and the data itself (denoted by data), respectively. The complement of the clock signal CKvco (denoted by CKvco ) from the voltage controlled oscillator 14 is applied to the inversion reset terminals (rb) of the flip-flops 113 and 114 such that two control signals dn1 and dn2 are generated, respectively. According to the two signals up1 and up2, the OR gate 115 generates a control signal up for controlling the charge pump 12 (refer to FIG. 2(a)). Similarly, the OR gate 116 generates a control signal dn for controlling the charge pump 12 according to the two signals dn1 and dn2 (refer to FIG. 2(b))

Referring to FIG. 1, the voltage Vd is substantially controlled by the signals (up, dn). In other words, the variation of the control voltage Vd is related to the phase error θe. FIG. 4 illustrates the relation between the variation of Vd and the phase error θe. As shown in FIG. 4, when the data signal data has a phase lagging behind the clock signal CKvco, the smaller the phase error θe is, the more the voltage Vd varies. Therefore, phase error θe is theoretically supposed to approximate to zero and closely moves around the origin when the phase-locked loop is going to enter a phase-locked state. However, due to the above phenomenon, when the data signal data of the phase-locked loop has a phase lagging behind the clock signal CKvco, an obvious variation of Vd will be generated, which leads to clock jitter. And, the tolerance for data random jitter becomes worse. In other words, it is difficult to reduce the clock jitter for conventional phase-locked loops, large data random jitter is thus unaccepted.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide higher tolerance for data random jitter.

Another object of the present invention is to provide a multi-phase-locked loop without static phase error.

The present invention is characterized by a multi-phase-locked loop which can generate a plurality of multi-phase clock signals by a multi-phase voltage controlled oscillater to detect the transition edge of the data signal data. Accordingly, multiple sets of control signals (upk/dnk) are generated. Therefore, phase error θe and voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the output control signals. This prevents the multiphase-locked loop from having dead zone. Furthermore, the clock jitter can be reduced and provide greater tolerance for data random jitter.

To achieve the aforementioned object, a multi phase-locked loop for data recovery in accordance with the invention includes a phase detector, a charge pump, a loop filter and a voltage controlled oscillator (VCO).

The phase detector is constituted by N phase detection units (U1, U2, . . . , UN, N is even, N≧4). The phase detection units are connected in cascade configuration, and each of the phase detection unit contains a data signal input terminal for receiving the data signal from outside; a clock signal input terminal for receiving the multi-phase clock signals (CK1, CK2, . . . , CKN) from outside; a delay signal input terminal for receiving the delay signal output from another phase detection unit; a delay signal output terminal for outputting the delay signal; and a charge/discharge control signal output terminal for outputting charge/discharge control signals. Each phase detection unit generates a delay signal (D1, D2, . . . , DN) according to the input data signal and the complement of the multi-phase clock signal.

The delay signal (Dj+1) generated by the (j+1)th phase detection unit is applied to the jth phase detection unit via the jth delay signal input terminal. The delay signal (D1) generated by the first phase detection unit (U1) is applied to the Nth phase detection unit (UN) via the Nth delay signal input terminal. In addition, the jth phase detection unit (Uj′1≦j≦N′j is an integer) generates control signals (dn1, d2, . . . , dnN/2, upN/2, . . . , up2) for the charge/discharge operations according to the delay signal (Dj) from the jth phase detection unit, the delay signal (Dj+1) from the (j+1)th phase detection unit, and the multi-phase clock signal (CKj) which is applied to the jth phase detection unit. However, the Nth phase detection unit (UN) generates a charge control signal (up1) according to the delay signal (DN) from the Nth phase detection unit, the delay signal (D1) from the first phase detection unit, and the multi-phase clock signal (CKN) which is applied to the Nth phase detection unit.

The charge pump is constituted by N/2 charge and discharge units (CP1, CP2, . . . , CPN/2), wherein the kth (1≦k≦N/2) charge and discharge unit (CPk) receives the kth charge/discharge control signal (upk/dnk) from the above mentioned phase detector and generates a charge/discharge current Ichk, which equals to (wkupk−wkdnk)Iss, wherein wk is a weighting value; Iss is a fixed current value; and w1<w2< . . . <wN/2. The total charge/discharge current (Ich) output from the charge pump equals to Ich1+Ich2+ . . . Ichk+ . . . +IchN/2.

The VCO described above is a multi-phase VCO, it outputs N multi-phase clock signals (CK1, CK1 . . . CKN). These signals are applied to the phase detectors described above, respectively.

Under the circumstance described above, the phase difference between CKj+1 and CKj is 2π/N.

The multi-phase clock signal (CKj+1) which is applied to the (j+1)th phase detection unit (Uj+1) and the multi-phase clock signal (CKj) which is applied to the jth phase detection unit (Uj). In accordance with the invention, the relation between the phase error θe and the voltage Vd of the phase-locked loop can be adjusted to be nearly linear by employing these control signals. Therefore, a phase-locked loop without dead zone can be derived, which can reduce clock jitter and enhance the tolerance for data random jitter.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and the features and effects of the present invention can be best understood by referring to the following detailed descriptions of the preferred embodiment and the accompanying drawings, in which:

FIG. 1 is a block diagram showing a prior art phase-locked loop for data recovery;

FIG. 2(a) is a clock diagram showing the control signal (up) generated by a prior art phase detector when the transition edge of the data signal data leads the falling edge of the clock signal CKvco;

FIG. 2(b) is a clock diagram showing the control signal (dn) generated by a prior art phase detector when the transition edge of the data signal data lags behind the falling edge of the clock signal CKvco;

FIG. 3 depicts a circuit of a prior art phase detector;

FIG. 4 depicts the relation between the phase error θe and voltage Vd by using a prior art phase detector;

FIG. 5 is a block diagram showing a multi-phase-locked loop in accordance with the present invention;

FIG. 6 is a block diagram showing a phase detector in accordance with the present invention;

FIG. 7 is a detailed circuit showing a phase detector in accordance with the present invention;

FIG. 8 is a detailed circuit showing a charge pump in accordance with the present invention;

FIG. 9 is a state diagram showing the signals of data signal data employed in the multi-phase-locked loop, the multi-phase clock signals (CK1, CK2, . . . , CK10), and the charge/discharge control signals (upk/dnk) used in the present invention; and

FIG. 10 depicts the relation between the phase error θe and voltage Vd in the multi-phase-locked loop in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Before describing the preferred embodiment in accordance with the invention, it should be made clear that the loop filter in the multi-phase-locked loop of the invention are similar to that of the prior art and will not be explained here.

Firstly, referring to FIG. 5, the multi-phase-locked loop for data recovery in accordance with the invention includes: a phase detector 21, a charge pump 22, a loop filter 23, and a multi-phase VCO 24.

As illustrated in FIG. 6, the phase detector 21 is constituted by N phase detection units (U1, U2, . . . , UN), wherein N is even and N≧4. The phase detection units (U1, U2, . . . , UN) are connected in cascade configuration, and each phase detection unit contains: a data signal input terminal 61 for receiving a data signal from outside; a clock signal input terminal 62 for receiving multiphase clock signals (CK1, CK2, . . . , CHN) from outside; a delay signal input terminal 63 for receiving the output delay signal from another phase detection unit; a delay signal output terminal 64 for outputting a elay signal; and a charge/discharge control signal output terminal 65 for outputting charge/discharge control-signal.

Each phase detection unit (U1, U2 . . . UN) generates a delay signal (D1, D2, . . . , DN) according to the data signal data applied to the phase detection unit, and the complement of the multi-phase clock signals (CK1, CK2, . . . , CKN). Moreover, the delay signal (Dj+1) generated by the (j+1)th phase detection unit (Uj+1) is applied to the jth phase detection unit (Uj) via the delay signal input terminal 63 in the jth phase detection unit (Uj). And the delay signal (D1) generated by the first phase detection unit (U1) is applied to the Nth phase detection unit (UN) via the delay signal input terminal 63 in the Nth phase detection unit (UN)

The jth phase detection unit (Uj, 1≦j<N, j is a positive integer) generates charge/discharge control signals (dn1, dn2, . . . , dnN/2, upN/2, . . . , up2) according to the delay signal (Dj) from the jth phase detection unit (Uj), the delay signal (Dj+1) from the (j+1)th phase detection unit (Uj+1), and the multi-phase clock signal (CKj) which is applied to the jth phase detection unit (Uj). The Nth phase detection unit generates a charge control signal (up1) according to the delay signal (Dn) from the Nth phase detection unit (UN), the delay signal (D1) from the first phase detection unit (U1), and the multi-phase clock signal (CKN) which is applied to the Nth phase detection unit (UN).

As described above, the multi-phase clock signal (CKj+1) is applied to the (j+1)th phase detection unit (Uj+1) and the multi-phase clock signal (CKj) is applied to the jth phase detection unit (Uj). The phase difference between the two signals is 2π/N. Moreover, as described above, the plurality of multi-phase clock signals (CK1, CK2, . . . , CKN) are generated by the VCO 24.

Furthermore, FIG. 7 is utilized to illustrate the detailed circuit of phase detector 21 in accordance with the invention. As shown in FIG. 7, each phase detection unit (U1, U2, . . . , UN) of the phase detector 21 in accordance with the invention includes: an inverter 211, a first flip-flop 212, an exclusive OR gate 213, and a second flip-flop 214. The inverter 211 inverts the multi-phase clock signals (CK1, CK2, . . . , CKN) before these signals are applied to each first flip-flop 212, respectively. Each of the first flip-flops 212 generates a delay signal D. (1≦i≦N)according to the above mentioned data signal data, and the multi-phase clock signal which has been inverted by the inverter 2. The delay signal (Dj) from the first flip-flop 212 and the delay signal (Dj+1) from the first flip-flop 212 in next phase detection unit, are both applied to the exclusive OR gate 213. The second flip-flop 214 generates charge/discharge control signals (dn1, dn2, . . . , dnN/2, upN/2, . . . , up2) according to the above mentioned multi-phase clock signal and the signal output from the exclusive OR gate.

It should be mentioned that the charge control signal (up1) is generated by the second flip-flop 214 of the Nth sphase detection unit (UN), which is based on the above described multi-phase clock signal (CKN) and the output signal from its exclusive OR gate 213. The input signals of the exclusive OR gate 213 of the Nth phase detection unit (UN) are the delay signal (D1) from the first phase detection unit (U1) and the delay signal (DN) from itself. In addition, the first flip-flop and the second flip-flop are both D flip-flops in this embodiment.

As shown in FIG. 8, the charge pump 22 is constituted by N/2 charge and discharge units (CP1, CP2, . . . , CPN/2). The kth charge and discharge unit CPk (1≦k≦N/2) receives the kth charge/discharge control signal (upk′dnk) output from the phase detector 21 and generates a charge/discharge current Ichk according to the received signal. The charge/discharge current Ichk is determined by: (wkupk−wkdnk)Iss, wherein wk is a weighting value, Iss is a fixed current value, and w1<w2< . . . <wN/2. Therefore, the total charge/discharge current (Ich) output from charge pump 22 is:
Ich=Ich1+Ich2+ . . . Ichk+ . . . +IchN/2

In other words, the total charge/discharge current (Ich) is:
Ich={[w1up1+w2up2+ . . . +wN/2upN/2]−[w1dn1+w2dn2+ . . . +wN/2dnN/2]}Iss

A exemplified configuration of the multi-phase-locked loop is depicted below to further explain the method of using a couple of multi-phase clock signals.

[Exemplified Configuration]

Firstly it should be mentioned here, the preferred embodiment recited below includes ten phase detection units (U1, U2, . . . , U10) in the phase detector 21.

Secondly, referring to FIG. 7, when the data signal data and the multi-phase clock signal (CK1, CK2, . . . , CK10) shown in FIG. 9 are applied to each phase detection unit (U1, U2, . . . , U10), the first flip-flop 212 of the first phase detection unit (U1) outputs adelay signal (D1); the first flip-flop 212 of the second phase detection unit (U2) outputs a delay signal (D2); . . . etc.

As described above, the delay signal (D1) generated by the first phase detection unit (U1) as well as the delay signal (D2) generated by the second phase detection unit (U2) cooperatively generate an output signal (D1⊕D2) via the exclusive OR gate 213 in the first phase detection unit (U1). Similarly, the delay signal (D2) generated by the second phase detection unit (U2) as well as the delay signal (D3) generated by the third phase detection unit (U3) cooperatively generate an output signal (D2⊕D3) via the exclusive OR gate 213 in the second phase detection unit (U2). However, the delay signal (D10) generated by the tenth phase detection unit (U10) as well as the delay signal (D1) generated by the first phase detection unit (U1) cooperatively generate an output signal (D1⊕D1) via the exclusive OR gate 213 in the tenth phase detection unit (U10).

As described in the preceding paragraph, the second flip-flop 214 of the first phase detection unit (U1) generates a discharge control signal (dn1) according to the multi-phase clock signal (CK1) and the output signal (D1⊕D2) from the exclusive OR gate 213. Similarly, the second flip-flop 214 of the second phase detection unit (U2) generates a discharge control signal (dn2) according to the multi-phase clock signal (CK2) and the output signal (D2⊕D3) from the exclusive OR gate 213. Similarly as above, the third to fifth phase detection units (U3U5) generates a discharge control signal (dn3dn5), respectively. Furthermore, the sixth to ninth phase detection units (U6U9) generates a charge control signal (up5up2). The second flip-flop 214 of the tenth phase detection unit (U10) generates a charge control signal (up1) according to the multi-phase clock signal (CK10) and the output signal from the exclusive OR gate 213. It should be mentioned here, due to the phase difference between two consecutive multi-phase clock signals of (CK1, CK2, . . . , CK10) being 2π/10, the phase detection unit (U1, U2, . . . , U10) of the phase detection 21 respectively generate five discharge control signals (dn1′dn2′dn3′dn4′dn5) and five charge control signals (up1′up2′up3′up4′up5) in this preferred embodiment.

Referring to FIG. 8, the phase detector 21 in this preferred embodiment includes ten phase detection units (U1, U2, . . . , U10), the charge pump 22 contains five charge and discharge units (CP1, CP2, . . . , CP5). At this time, the charge/discharge control signals (up1/dn1′up2/dn2′up3/dn3′up4/dn4′up5/dn5) output from the phase detector 21 are respectively applied to the charge and discharge units (CP1, CP2, . . . , CP5). If Ich(t) represents the total charge/discharge current of charge pump 22 at time t, Iss represents a fixed current value, and w1w5 represent the weighting value of each charge and discharge unit, wherein w1<w2<w3<w4<w5, then
Ich(t)=
{[w1up1(t)+w2up2(t)+w3up3(t)+w4
up4(t)+w5up5(t)]−
[w1dn1(t)+w2dn2(t)+w3dn3(t)+w4
dn4(t)+w5dn5(t)]}Iss

Consequently, it is obvious that the total charge/discharge current Ich output from the charge pump 22 displays a nearly linear variation in the multi-phase-locked loop of this preferred embodiment. Therefore, the phase error θe and the voltage Vd in the multi-phase-locked loop in accordance with the invention can be adjusted to be nearly linear (as shown in FIG. 10) according to those control signals. To sum up, there are some advantages in the multi-phase-locked loop in accordance with the invention, which are listed as follows:

  • 1. From FIG. 10, it can be understood that there is no dead zone in the multi-phase-locked loop in accordance with the invention because all the up/dn are kept as a fixed time period. Therefore, enough loop signals (up or dn) can be generated even the phase error IIe is very small.
  • 2. Due to the linear relation between Vd and θe, a sudden voltage variation can be avoided. The condition illustrated in FIG. 4 can thus be prevented, and smaller recovering clock jitter can be acquired as well.
  • 3. Larger tolerance for data random jitter can also be derived because lower recovering clock jitter can be acquired by the phase detector in accordance with the invention.
  • 4. When the conventional phase detector 11 as illustrated in FIG. 1 is used to recover the data, another flip-flop needs to be incorporated to read the data in a steady locked phase. Therefore, the problems such as device coupling, parasitic capacitance and delay effects cannot be avoided, which is called static phase error. On the other hand, it is unnecessary to add another flip-flop to read the data in a steady locked phase by using CK6 to recover (read) data directly in the phase detector according to the invention to get the best recovered data (D6, not shown in the figure).

The-exemplified configuration and the preferred embodiment described in the description are only illustrative and are not to be construed as limiting the invention. Various modifications and applications can be made without departing from the true spirit and scope of the invention as defined by the appended claims.

Patent Citations
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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7782988 *May 2, 2005Aug 24, 2010Multigig Inc.Digital frequency synthesizer
US8315349 *Oct 26, 2008Nov 20, 2012Diablo Technologies Inc.Bang-bang phase detector with sub-rate clock
US20090110136 *Oct 26, 2008Apr 30, 2009Riccardo BadaloneBang-bang phase detector with sub-rate clock
Classifications
U.S. Classification375/376, 375/374
International ClassificationH03D3/24, H03L7/087, H03L7/089, H04L7/033
Cooperative ClassificationH03L7/0891, H03L7/087, H04L7/033
European ClassificationH03L7/087, H03L7/089C, H04L7/033
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