|Publication number||USRE40990 E1|
|Application number||US 11/805,866|
|Publication date||Nov 17, 2009|
|Filing date||May 23, 2007|
|Priority date||Aug 27, 2001|
|Also published as||US6904537|
|Publication number||11805866, 805866, US RE40990 E1, US RE40990E1, US-E1-RE40990, USRE40990 E1, USRE40990E1|
|Inventors||J. Zachary Gorman|
|Original Assignee||Gorman J Zachary|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (2), Classifications (8), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a reissue application for U.S. Pat. No. 6,904,537 issued on Jun. 7, 2005.
1. Field of the Invention
The present invention generally relates to the field of electronic circuits. More specifically, the present invention relates to a method and apparatus for passing data across an asynchronous clock boundary.
2. Background Information
With advances in integrated circuit, microprocessor, networking and communication technologies, an increasing number of devices, in particular, digital computing devices, are being networked together. Such devices are often first coupled to a local area network, such as an Ethernet based office/home network. In turn, the local area networks are interconnected together through wide area networks, such as ATM networks, Frame Relays, and the TCP/IP based global inter-networks, Internet. In transmitting from one network to another, data typically flows through one or more devices functioning e.g. as a network bridge or router. During the transition between such devices, and even between components within a single device, data will often be driven by multiple asynchronous clock signals regulating the respective traffic flows.
Depending upon how the clocks vary with respect to one another, there is the risk that invalid data may be passed from one time domain to the next. More specifically, there may be a point in time when the second clock samples data as it is transitioning in accordance with the transition of the first clock. If two asynchronous clocks are operating at the same frequency but vary in phase, it is possible to align the clocks to be synchronous by adjusting the phase of one or both clocks. If, however, two asynchronous clocks are operating at different frequencies, the respective clock edges may drift relative to each other in non-integer multiples resulting in unpredictable and perhaps invalid data.
Although asynchronous buffers (e.g. FIFO) with separate read and write clocks have traditionally been utilized to transfer multi-bit data from one time domain to another, it is difficult to design a circuit to accurately handle multi-bit data transfers/transitions commonplace in today's high-speed networks and computing devices without such buffers. Therefore, a novel technique to pass data between time domains while overcoming the limitations of the prior art is desired.
The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which:
In the following description, various aspects of the present invention will be described. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some or all aspects of the present invention. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will also be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the present invention. Further, the description repeatedly uses the phrase “in one embodiment”, which ordinarily does not refer to the same embodiment, although it may.
For example, in one embodiment, data source 210 may represent a network interface and data sink 220 may represent a microprocessor, while communication channels 205 and 215 may each represent a multi-bit bus architecture such as a universal serial bus (USB), a peripheral component interconnect (PCI) bus, an industry standard architecture (ISA) bus, and so forth. In an alternative embodiment, data source 210 and data sink 220 may represent independent devices interconnected with stability logic 200 by way of separate wire line and/or wireless network segments, each operating asynchronously with respect to the other. In one embodiment, communication channel 205 represents an Ethernet based network segment, whereas communication channel 215 represents a synchronous optical network (SONET) segment. Although in the illustrated embodiment data source 210, stability logic 200 and data sink 220 are depicted as separate devices and/or components, data source 210 and/or data sink 220 may instead be embodied with the functionality of stability logic 200. In one embodiment, stability logic 200 is implemented as an integrated circuit within data sink 220.
Data source 210 is shown including clock signal 206 having a first frequency (f1), and data signal 208 having been sampled by clock signal 206. Data signal 208 illustrates valid data segments as well as data transition points that correspond to the rising edges of clock signal 206. Each transition point indicates a point in time, including an amount of time preceding and following each transition (i.e. set up and hold times), when the value of the sampled data may change with the value of the clock. During these transitions, the data is considered to be unpredictable and may possibly be invalid. In contrast, between each transition of the sampling clock (e.g. between each rising clock edge), data signal 208 is considered to be valid.
Data sink 220 is shown including clock signal 216 having a second frequency of (f2) where f2>f1. In one embodiment clock signal 216 is the sole operational clock utilized by data sink 220, whereas in another embodiment, clock signal 216 is one of multiple clock signals generated and/or provided by data sink 220. In one embodiment of the present invention, stability logic 200 causes data (e.g. data signal 208) associated with a first time domain (e.g. clock signal 206) to be sampled with respect to a second time domain (e.g. clock signal 216) such that the transition of the sampling clock signal does not coincide with a data transition point, thereby avoiding stability concerns, associated with the prior art. For example, in the illustrated embodiment stability logic 200 aligns and samples data signal 208 based upon output clock 216 such that any given transition (e.g. rising edge) of clock signal 216 causes valid data to be sampled.
Selection logic 300 is equipped to receive the above-referenced output signal (SEL) from delay circuit 302, the input data signal (DATA), and the output data signal from delay circuit 304 (DATA′). Additionally, selection logic is equipped to receive an output clock signal that is asynchronous with respect to reference signal 306. In accordance with the teachings of the present invention, selection logic 300 samples both DATA and DATA′ based on the output clock and selects one of the data lines such that during each transition of the output clock, valid data is present on the selected data line. In one embodiment, selection logic 300 selects between data lines (DATA, DATA′) based at least in part upon the output of delay circuit 302 (SEL).
In the illustrated embodiment, registers 510-515 are implemented as edge triggered D flip-flops, however, in other embodiments, registers 510-515 may be implemented through various other types of flip-flops and/or latches known in the art. Together, registers 510-515 operate to further reduce potential metastability concerns with stability logic 300 by providing an additional stage of resolution before being propagated to MUX 520.
As was mentioned above, the novel relationship between the SEL, DATA and DATA′ signals, facilitates the selection of valid data from one of DATA and DATA′ regardless of whether SEL is transitioning or is stable. Although the data that is actually selected in accordance with the present invention will be valid, there is a chance that the same data may be selected two or more consecutive times due to the phase lag (or lead) of DATA′. In one embodiment of the invention, an extra signal (VALID SELECT) is added to e.g. the data bus that echoes the input clock (CLOCK A) at half the frequency of the clock. Depending upon the frequency difference between the clocks, VALID SELECT may be a single-bit or multi-bit signal.
Thus, fit can be seen from the above description, a novel method and apparatus for passing data across an asynchronous clock boundary has been described. While the present invention has been described in terms of the above-described embodiments, the present invention is not limited to the embodiments described. As the present invention can be practiced with further modification and alteration within the spirit and scope of the appended claims, the description is to be regarded as illustrative instead of restrictive on the present invention.
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|1||Notice of Allowance mailed Nov. 24, 2004 for U.S. Appl. No. 09/940,315.|
|2||Office Action mailed Sep. 15, 2004 for U.S. Appl. No. 90/940,315.|
|U.S. Classification||713/401, 375/354, 713/600|
|International Classification||H04L7/00, G06F1/12, G06F1/04|
|Aug 3, 2007||AS||Assignment|
Owner name: NETWORK ELEMENTS, INC., OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GORMAN, J. ZACHARY;REEL/FRAME:019646/0890
Effective date: 20010820
Owner name: NULL NETWORKS LLC, NEVADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRIQUINT SEMICONDUCTOR, INC.;REEL/FRAME:019646/0903
Effective date: 20050908
Owner name: TRIQUINT SEMICONDUCTOR, INC., OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NETWORK ELEMENTS, INC.;REEL/FRAME:019646/0897
Effective date: 20041217
|Dec 7, 2010||CC||Certificate of correction|
|Oct 4, 2012||FPAY||Fee payment|
Year of fee payment: 8