|Publication number||USRE40991 E1|
|Application number||US 11/362,564|
|Publication date||Nov 17, 2009|
|Priority date||May 15, 2001|
|Also published as||US6701479, US20020174399, WO2002093753A1|
|Publication number||11362564, 362564, US RE40991 E1, US RE40991E1, US-E1-RE40991, USRE40991 E1, USRE40991E1|
|Inventors||Richard B. Keller|
|Original Assignee||Keller Richard B|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Non-Patent Citations (2), Referenced by (3), Classifications (5), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to the field of data processing. More specifically, the present invention relates to high speed cyclic redundancy check (CRC) generation, having special application to high speed network traffic routing, such as Gigabit Ethernet packet switching.
2. Background Information
Cyclic Redundancy Check (CRC) has long been employed as a metric to facilitate detection of data transmission error. The technique is employed in a wide variety of data processing related disciplines, including in particular, networking. The underlying mathematics including the polynomial divisions involved in the generation of a CRC value for a data block is well understood among those ordinarily skilled in the art. Various hardware as well as software implementations are known. Examples of known hardware implementations include but are not limited to the implementations available from e.g. Actel of Sunnyvale, Calif.
With advances in integrated circuit, microprocessor, networking and communication technologies, increasing number of devices, in particular, digital computing devices, are being networked together. Devices are often first coupled to a local area network, such as an Ethernet based office/home network. In turn, the local area networks are interconnected together through wide area networks, such as ATM networks, Frame Relays, and the like. Of particular notoriety is the TCP/IP based global inter-networks, Internet.
As a result of this trend of increased connectivity, increasing number of applications that are network dependent are being deployed. Examples of these network dependent applications include but are not limited to, email, net based telephony, world wide web and various types of e-commerce. Successes of many of these content/service providers as well as commerce sites depend on high speed delivery of a large volume of data. As a result, high speed networking, which in turn translates into high speed CRC generation is needed.
Unfortunately, the current generation of CRC generators known in the art are generally unable to meet the speed requirement of the next generation IC based high speed network traffic routing devices. For these IC based devices, it is not only necessary for the CRC generation resource to be sufficiently fast to keep pace with the processing of a single network traffic flow, it is further desirable that the CRC generation resource to be sufficiently efficient and fast, such that it can be shared among the various flow processing units, thereby eliminating the need to have dedicated CRC generation resource for each of the flow processing units.
Thus, a highly efficient approach to CRC generation is needed.
A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a data block. In one embodiment, the CRC generation unit also includes a selector to select one of the remainder values, and a register to store the selected remainder value, return the stored remainder value to the PDCs for formation of different bit length dividends, and output the stored remainder value of the last iteration as the generated CRC value.
In one embodiment, the CRC generation unit further includes alignment circuitry to align the data block. In one embodiment, multiple CRC generation units are provided to generate the CRC values of successive variable length data blocks.
In one embodiment, the CRC generation units form a shared resource to multiple network traffic flow processing units of a network traffic routing device.
In one embodiment, the network traffic routing device is disposed on a single integrated circuit.
The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which:
In the following description, various aspects of the present invention will be described. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some or all aspects of the present invention. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will also be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well known features are omitted or simplified in order not to obscure the present invention. Further, the description repeatedly uses the phrase “in one embodiment”, which ordinarily does not refer to the same embodiment, although it may.
Referring now to
Except for fast CRC generator 106a/106b, data sender 102, data receiver 104 and communication link 107 are all intended to represent a broad range of data sending, data receiving and communication systems and/or components known in the art. Accordingly, except for fast CRC generator 106a/106b, data sender 102, data receiver 104 and communication link 107 will not be otherwise further described.
Referring briefly to
Referring back to
The n×polynomial division circuits 204a/204b collectively and iteratively generate the CRC value for the aligned variable length data block in m (or m−1) iterations (depending on where the starting and the ending bits of the variable length data block is located in the first and the last n-bit group). As will be described in more detail below, each collection of n×polynomial division circuits 204a/204b includes n sets of polynomial division circuits to facilitate performance of n polynomial divisions of n different length dividends in parallel, thereby allowing the successive CRC generation to be efficiently completed with the last n-bit group having anywhere from 1 to n “residual” bits of the variable length data block.
Further, one datapath 202a-204a/202b-204b may start the iteratively generation of the CRC value for an immediately following variable length data block while the other datapath 202a-204a/202b-204b is “finishing up” its iteratively generation of the CRC value for the immediately preceding variable length data, thereby speeding up the aggregate times incurred for generating CRC values for a large number of successive variable length data blocks, as in the case of multiple network flow processing.
As illustrated, fast CRC generator 106a/106b also includes selector 206 coupled to the two datapaths 202a-204a and 202b-204b to alternate between selecting the two outputs of datapaths 202a-204a and 202b-204b for output as the CRC values of the successive variable length data blocks.
Selector 504 is employed to select one of the remainder value outputs of the n polynomial division circuits 502a-502h, and to output the selected remainder value for CRC register 506. For most of the iterations, the remainder value selected is the remainder value outputted by polynomial division circuit 502a, until the last iteration, where the remainder value selected is the remainder value outputted by the appropriate one of the polynomial division circuits 502a-502h corresponding to the number of residual bits of the variable length data block included in the processed bit group.
CRC register 506 stores the remainder value selected at each iteration, and in turn, outputs it for the polynomial division circuits 502a-502h to form the new multi-bit dividends of the next iteration of the CRC generation, as described earlier. Eventually, the stored remainder value of the last iteration is outputted as the CRC value of the variable length data block.
For the illustrated embodiment, common/shared function units 708 include in particular a shared CRC generation function block, incorporated with the dual datapath architecture fast CRC generator of FIG. 2. Moreover, each collection of n×CRC polynomial circuits includes n polynomial division circuits as architected in FIG. 4. Accordingly, the common/shared CRC generator may alternate between generating CRC values for different data packets of the different flows being processed by per flow inbound/outboard processing units 708/710.
As a result, the amount of storage required for provisioning the CRC function for the various flows being processed in parallel is substantially reduced under the present invention. In turn, data routing device 702 may be advantageously disposed on a single integrated circuit. Thus, data routing device 702 is able to handle high speed line rate data packet switching for multiple data flows at the same time. In one embodiment, data routing device 702 is an IC component for routing packets transmitted over an optical medium onto an electrical medium at very high speed.
Thus, it can be seen from the above descriptions, a novel highly efficient method and apparatus for generating CRC for data blocks or data packets has been described. While the present invention has been described in terms of the above described embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The present invention can be practiced with modification and alteration within the spirit and scope of the appended claims. Thus, the description is to be regarded as illustrative instead of restrictive on the present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5130991 *||Dec 6, 1988||Jul 14, 1992||Hitachi, Ltd.||Method and apparatus for crc computation|
|US5323403 *||Oct 13, 1992||Jun 21, 1994||International Business Machines Corporation||Method and apparatus for maximizing process throughput|
|US5619516||Oct 11, 1995||Apr 8, 1997||Motorola, Inc.||Efficient CRC remainder coefficient generation and checking device and method|
|US5734826 *||Sep 17, 1992||Mar 31, 1998||International Business Machines Corporation||Variable cyclic redundancy coding method and apparatus for use in a multistage network|
|US5844923||Oct 24, 1996||Dec 1, 1998||At&T Corp||Fast framing of nude ATM by header error check|
|US6029186 *||Jan 20, 1998||Feb 22, 2000||3Com Corporation||High speed calculation of cyclical redundancy check sums|
|US6119263 *||Apr 28, 1998||Sep 12, 2000||Hewlett-Packard Company||System and method for transmitting data|
|US6128766 *||Nov 12, 1996||Oct 3, 2000||Pmc-Sierra Ltd.||High speed cyclic redundancy check algorithm|
|1||Monteiro et al., "A Polynomial Division Pipelined Architecture for CRC Error Detection Codes," 13.sup.th International Conference on Microelectronics, Oct. 29-31, 2001, pp. 133-166.|
|2||Monteiro et al., "Fast Configurable Polynomial Division for Error Control Coding Applications," IEEE, Jul. 2001, pp. 158-161.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8397305||Mar 12, 2013||Atwater Ventures Limited||System and method for connecting gaming devices to a network for remote play|
|US8959154||Dec 9, 2008||Feb 17, 2015||Zynga Inc.||System and method for connecting gaming devices to a network for remote play|
|US9251649||Mar 15, 2013||Feb 2, 2016||Zynga Inc.||System and method for connecting gaming devices to a network for remote play|
|International Classification||H03M13/00, H03M13/09|
|Cooperative Classification||H03M13/091, H03M13/617|
|Feb 23, 2006||AS||Assignment|
Owner name: NETWORK ELEMENTS, INC., OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KELLER, RICHARD B.;REEL/FRAME:017632/0191
Effective date: 20010511
Owner name: NULL NETWORKS LLC, NEVADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRIQUINT SEMICONDUCTOR, INC.;REEL/FRAME:017631/0388
Effective date: 20050908
Owner name: TRIQUINT SEMICONDUCTOR, INC., OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NETWORK ELEMENTS, INC.;REEL/FRAME:017630/0064
Effective date: 20041217
|Aug 24, 2011||FPAY||Fee payment|
Year of fee payment: 8
|Aug 25, 2015||FPAY||Fee payment|
Year of fee payment: 12
|Nov 6, 2015||AS||Assignment|
Owner name: XYLON LLC, NEVADA
Free format text: MERGER;ASSIGNOR:NULL NETWORKS LLC;REEL/FRAME:037057/0156
Effective date: 20150813