US RE40991 E1 Abstract A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a data block. In one embodiment, the unit also includes a selector to select one of the remainder values, and a register to store the selected remainder value, return the stored remainder value to the PDCs for formation of different bit length dividends, and output the stored remainder value of the last iteration as the generated CRC value. In one embodiment, the unit further includes alignment circuitry to align the data block. In one embodiment, multiple units are provided to generate the CRC values of successive variable length data blocks. In one embodiment, the units form a shared resource to multiple network traffic flow processing units of a network traffic routing IC.
Claims(37) 1. An apparatus comprising:
a plurality of polynomial division circuits to perform a plurality of different bit lengths polynomial divisions in parallel, including outputting a plurality of remainder values, for an iteration of an iterative CRC generation for a data block;
a selector coupled to the plurality of polynomial division circuits to select one of said remainder values outputted for the iteration of said iterative CRC generation; and
a register coupled to the selector and the polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the polynomial division circuits for use by the polynomial division circuits to form a plurality of different bit lengths dividends for the polynomial division circuits for a next iteration of the iterative CRC generation for the data block.
2. The apparatus of
3. The apparatus of
4. The apparatus of
5. The apparatus of
6. An apparatus comprising:
a first plurality of polynomial division circuits to perform a first plurality of different bit lengths polynomial divisions in parallel, including outputting a first plurality of remainder values, for an iteration of a first iterative CRC generation for a first variable length data block;
a first selector coupled to the first plurality of polynomial division circuits to select one of said first remainder values outputted for the iteration of said first iterative CRC generation;
a first register coupled to the first selector and the first polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the first polynomial division circuits for use by the first polynomial division circuits to form a first plurality of different bit lengths dividends for the first polynomial division circuits for a next iteration of the first iterative CRC generation for the first variable length data block;
a second plurality of polynomial division circuits to perform a second plurality of different bit lengths polynomial divisions in parallel, including outputting a second plurality of remainder values, for an iteration of a second iterative CRC generation for a second variable length data block immediately following said first variable length data block;
a second selector coupled to the second plurality of polynomial division circuits to select one of said second remainder values outputted for the iteration of said second iterative CRC generation;
a second register coupled to the second selector and the second polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the second polynomial division circuits for use by the second polynomial division circuits to form a second plurality of different bit lengths dividends for the second polynomial division circuits for a next iteration of the second iterative CRC generation for the second variable length data block.
7. The apparatus of
8. The apparatus of
9. The apparatus of
10. An apparatus comprising:
first alignment unit to align a first variable length data block received in first m groups of n-bit groups with the starting bit of the first variable length data block being located in one of the n-bits of the first n-bit group of the first m groups and the ending bit of the first variable length data block being located in one of n-bits of the last n-bit group of the first m groups, where m and n are integers greater than or equal to 1;
a first CRC generation unit coupled to the first alignment unit to iteratively generate a first CRC value for the first variable length data block, the first CRC generation unit including a first plurality of polynomial division circuits to perform a first plurality of polynomial divisions for a plurality of different length dividends in parallel for each iteration of the first iterative generation of the first CRC value of the first variable length data block;
second alignment unit to align a second variable length data block immediately following the first variable length data block, received in second m groups of n-bit groups with the starting bit of the second variable length data block being located in one of the n-bits of the first n-bit group of the second m groups and the ending bit of the second variable length data block being located in one of n-bits of the last n-bit group of the second m groups; and
a second CRC generation unit coupled to the second alignment unit to iteratively generate a second CRC value for the second variable length data block, the second CRC generation unit including a second plurality of polynomial division circuits to perform a second plurality of polynomial divisions for a plurality of different length dividends in parallel for each iteration of the second iterative generation of the first CRC value of the second variable length data block.
11. The apparatus of
a first/second selector coupled to the first/second plurality of polynomial division circuits to select one of first/second plurality remainder values outputted for an iteration of the first/second iterative CRC generation; and
a first/second register coupled to the first/second selector and the first/second polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the first/second polynomial division circuits for use by the first/second polynomial division circuits to form a first/second plurality of different bit lengths dividends for the first/second polynomial division circuits for a next iteration of the first/second iterative CRC generation for the first/second variable length data block.
12. The apparatus of
13. A method comprising:
aligning a first variable length data block received in first m groups of n-bit groups with the starting bit of the first variable length data block being located in one of the n-bits of the first n-bit group of the first m groups and the ending bit of the first variable length data block being located in one of n-bits of the last n-bit group of the first m-groups, where m and n are integers greater than or equal to 1;
iteratively generating a first CRC value for the first variable length data block, including for each iteration, performance of a first plurality of polynomial divisions for a plurality of different length dividends in parallel;
aligning a second variable length data block immediately following the first variable length data block, received in second m groups of n-bit groups with the starting bit of the second variable length data block being located in one of the n-bits of the first n-bit group of the second m groups and the ending bit of the second variable length data block being located in one of n-bits of the last n-bit group of the second m groups; and
iteratively generating a second CRC value for the second variable length data block, including for each iteration, performance of a second plurality of polynomial divisions for a plurality of different length dividends in parallel for each iteration of the second iterative generation of the first CRC value of the second variable length data block.
14. The method of
selecting one of first/second plurality remainder values outputted for an iteration of the first/second iterative CRC generation; and
storing the selected remainder value of the iteration, and output the stored remainder value for use to form a first/second plurality of different bit lengths dividends for a next iteration of the first/second iterative CRC generation for the first/second variable length data block.
15. An apparatus comprising:
a plurality of processing units to correspondingly process a plurality of network traffic flows; and
a shared CRC generation block coupled to the processing units to alternately generate a CRC value for a data block of a selected one of the network traffic flows, the shared CRC generation block including at least one CRC generation unit that iteratively generate a first CRC value for the data block of the selected one of the network traffic flows, the at least one CRC generation unit including a plurality of polynomial division circuits to perform a plurality of polynomial divisions for a plurality of different length dividends in parallel for each iteration of the iterative generation of the CRC value of the data block of the selected one of the network traffic flow.
16. The apparatus of
17. The apparatus of
a selector coupled to the plurality of polynomial division circuits to select one of a plurality remainder values outputted for an iteration of the iterative CRC generation; and
a register coupled to the selector and the polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to polynomial division circuits for use by the polynomial division circuits to form a plurality of different bit lengths dividends for the polynomial division circuits for a next iteration of the iterative CRC generation for the data block of the selected one of the network traffic flow.
18. The apparatus of
19. An apparatus comprising:
a plurality of processing units to correspondingly process a plurality of network traffic flows; and
a shared CRC generation block coupled to the processing units to alternately generate CRC values for data blocks of a selected one of the network traffic flows, the shared CRC generation block including a first and a second CRC generation unit that iteratively generate a first and a second CRC value for a first and a second data block of the selected one of the network traffic flows, the first and second CRC generation units correspondingly including first and second plurality of polynomial division circuits to perform first and second plurality of polynomial divisions for first and second plurality of different length dividends in parallel for a first and a second iteration of a first and a second iterative generation of the first and the second CRC value of the first and second data block of the selected one of the network traffic flow.
20. The apparatus of
19, wherein
the first CRC generation unit includes a first alignment unit to align the first data block received in first m groups of n-bit groups with the starting bit of the first data block being located in one of the n-bits of the first n-bit group of the first m groups and the ending bit of the first data block being located in one of n-bits of the last n-bit group of the first m groups, where m and n are integers greater than or equal to 1; and
the second CRC generation unit includes a second alignment unit to align the second data block, which immediately follows the first data block, received in second m groups of n-bit groups with the starting bit of the second data block being located in one of the n-bits of the first n-bit group of the second m groups and the ending bit of the second data block being located in one of n-bits of the last n-bit group of the second m groups.
21. The apparatus of
a first/second selector coupled to the first/second plurality of polynomial division circuits to select one of first/second plurality remainder values outputted for an iteration of the first/second iterative CRC generation; and
a first/second register coupled to the first/second selector and the first/second polynomial division circuits to store the selected remainder value of the iteration, and to output the stored remainder value to the first/second polynomial division circuits for use by the first/second polynomial division circuits to form a first/second plurality of different bit lengths dividends for the first/second polynomial division circuits for a next iteration of the first/second iterative CRC generation for the first/second data block of the selected one of the network traffic flows.
22. The apparatus of
23. An apparatus comprising:
a plurality of polynomial division circuits to perform a plurality of polynomial divisions in parallel to provide a plurality of remainder values for an iteration of an iterative CRC generation for a data block; a selector coupled to the plurality of polynomial division circuits to select one of said remainder values for the iteration of said iterative CRC generation; and a register coupled to the selector and the polynomial division circuits to store the selected remainder value of the iteration. 24. The apparatus of
25. The apparatus of
26. The apparatus of
27. An apparatus comprising:
a first plurality of polynomial division circuits to perform a first plurality of polynomial divisions in parallel to provide a first plurality of remainder values for an iteration of a first iterative CRC generation for a first variable length data block; a first selector coupled to the first plurality of polynomial division circuits to select one of said first remainder values for the iteration of said first Iterative CRC generation; a first register coupled to the first selector and the first polynomial division circuits to store said selected first remainder value; a second plurality of polynomial division circuits to perform a second plurality of polynomial divisions in parallel to provide a second plurality of remainder values for an iteration of a second iterative CRC generation for a second variable length data block immediately following said first variable length data block; a second selector coupled to the second plurality of polynomial division circuits to select one of said second remainder values for the iteration of said second iterative CRC generation; and a second register coupled to the second selector and the second polynomial division circuits to store said selected second remainder value. 28. The apparatus of
a first alignment unit to align said first variable length data block; and a second alignment unit to align said second variable length data block. 29. The apparatus of
30. An apparatus comprising:
a first alignment unit to align a first variable length data block; a first CRC generation unit coupled to the first alignment unit, said first CRC generation unit including a first plurality of polynomial division circuits to perform a first plurality of polynomial divisions for a plurality of dividends in parallel for iterations of a first iterative generation of a first CRC value associated with the first variable length data block; a second alignment unit to align a second variable length data block; and a second CRC generation unit coupled to the second alignment unit, said second CRC generation unit including a second plurality of polynomial division circuits to perform a second plurality of polynomial divisions for a plurality of dividends in parallel for iterations of a second iterative generation of a second CRC value associated with the second variable length data block. 31. A method comprising:
aligning a first variable length data block; iteratively generating a first CRC value for said first aligned variable length data block, including performing a first plurality of polynomial divisions for a plurality of dividends in parallel in iterations of said generating a first CRC value; aligning a second variable length data block, said second variable data block immediately following the first variable length data block; and iteratively generating a second CRC value for said second aligned variable length data block, including performing a second plurality of polynomial divisions for a plurality of dividends in parallel in iterations of said generations of said second CRC value of the second variable length data block. 32. The method of
selecting a remainder of at least one of said first plurality of polynomial divisions; and storing said selected remainder of said first plurality of polynomial divisions. 33. The method of
34. The method of
35. An apparatus comprising:
a plurality of processing units to process an associated plurality of network traffic flows; a shared CRC generation block including at least one CRC generation unit to iteratively generate a CRC value for a data block of an associated one of said network traffic flows, said at least one CRC generation unit comprising a plurality of polynomial division circuits to perform a plurality of polynomial divisions for a plurality of dividends in parallel for iterations of generation of said CRC value. 36. The apparatus of
a selector to select one of a plurality of remainder values resulting from an iteration of generation of said CRC value, and wherein said CRC generation unit is further adapted to iteratively generate a subsequent iteration of said generation of said CRC value based, at least in part, on said selected one of a plurality of remainders. 37. The apparatus of
Description 1. Field of the Invention The present invention relates to the field of data processing. More specifically, the present invention relates to high speed cyclic redundancy check (CRC) generation, having special application to high speed network traffic routing, such as Gigabit Ethernet packet switching. 2. Background Information Cyclic Redundancy Check (CRC) has long been employed as a metric to facilitate detection of data transmission error. The technique is employed in a wide variety of data processing related disciplines, including in particular, networking. The underlying mathematics including the polynomial divisions involved in the generation of a CRC value for a data block is well understood among those ordinarily skilled in the art. Various hardware as well as software implementations are known. Examples of known hardware implementations include but are not limited to the implementations available from e.g. Actel of Sunnyvale, Calif. With advances in integrated circuit, microprocessor, networking and communication technologies, increasing number of devices, in particular, digital computing devices, are being networked together. Devices are often first coupled to a local area network, such as an Ethernet based office/home network. In turn, the local area networks are interconnected together through wide area networks, such as ATM networks, Frame Relays, and the like. Of particular notoriety is the TCP/IP based global inter-networks, Internet. As a result of this trend of increased connectivity, increasing number of applications that are network dependent are being deployed. Examples of these network dependent applications include but are not limited to, email, net based telephony, world wide web and various types of e-commerce. Successes of many of these content/service providers as well as commerce sites depend on high speed delivery of a large volume of data. As a result, high speed networking, which in turn translates into high speed CRC generation is needed. Unfortunately, the current generation of CRC generators known in the art are generally unable to meet the speed requirement of the next generation IC based high speed network traffic routing devices. For these IC based devices, it is not only necessary for the CRC generation resource to be sufficiently fast to keep pace with the processing of a single network traffic flow, it is further desirable that the CRC generation resource to be sufficiently efficient and fast, such that it can be shared among the various flow processing units, thereby eliminating the need to have dedicated CRC generation resource for each of the flow processing units. Thus, a highly efficient approach to CRC generation is needed. A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a data block. In one embodiment, the CRC generation unit also includes a selector to select one of the remainder values, and a register to store the selected remainder value, return the stored remainder value to the PDCs for formation of different bit length dividends, and output the stored remainder value of the last iteration as the generated CRC value. In one embodiment, the CRC generation unit further includes alignment circuitry to align the data block. In one embodiment, multiple CRC generation units are provided to generate the CRC values of successive variable length data blocks. In one embodiment, the CRC generation units form a shared resource to multiple network traffic flow processing units of a network traffic routing device. In one embodiment, the network traffic routing device is disposed on a single integrated circuit. The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which: In the following description, various aspects of the present invention will be described. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some or all aspects of the present invention. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the present invention. However, it will also be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well known features are omitted or simplified in order not to obscure the present invention. Further, the description repeatedly uses the phrase “in one embodiment”, which ordinarily does not refer to the same embodiment, although it may. Referring now to Except for fast CRC generator Referring briefly to Referring back to The n×polynomial division circuits Further, one datapath As illustrated, fast CRC generator Selector CRC register For the illustrated embodiment, common/shared function units As a result, the amount of storage required for provisioning the CRC function for the various flows being processed in parallel is substantially reduced under the present invention. In turn, data routing device Thus, it can be seen from the above descriptions, a novel highly efficient method and apparatus for generating CRC for data blocks or data packets has been described. While the present invention has been described in terms of the above described embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The present invention can be practiced with modification and alteration within the spirit and scope of the appended claims. Thus, the description is to be regarded as illustrative instead of restrictive on the present invention. Patent Citations
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