US RE41031 E1 Abstract A frequency control system includes a voltage-controlled oscillator, a sampling circuit for sampling a clock signal produced by the oscillator for two consecutive transitions of an unstable incoming digital signal, and a frequency comparator for incrementing and decrementing a transition upcounter-downcounter controlling the oscillator. The system tolerates variation of the frequency of the incoming signal about a mean value, which has no effect on a clock signal to be extracted by means of a phase comparator or on the synthesized clock signal supplied by the oscillator if the incoming signal contains a high level of jitter and is supplied by a programmable frequency divider.
Claims(56) 1. A frequency control system comprising:
voltage-controlled oscillator means for generating a clock signal,;
means for receiving a digital incoming signal with unstable frequency for sampling said clock signal at two pairs of times corresponding to two consecutive transitions of said incoming signal in response to each of predetermined transitions of said incoming signal, said times of one pair being separated by a predetermined time-delay at most equal to half the period of said clock signal, to produce four state signals of said clock signal,;
a frequency comparator for combining said four state signals to form an upcounting signal only in response to the frequency of said clock signal being substantially less than the frequency of said incoming signal and to form a downcounting signal only in response to the frequency of said clock signal being greater than the frequency of said incoming signal,; and
upcounting and downcounting means for respectively upcounting and downcounting predetermined transitions of said incoming signal in response to said upcounting signal and said downcounting signal for applying a control voltage dependent on a content of said upcounting and downcounting means to said oscillator means via a digital-to-analog converter.
2. The system claimed in
3. The system claimed in
4. The system claimed in
5. The system claimed in
6. A system as claimed in
7. A system as claimed in
8. The system claimed in
9. The system claimed in
10. The system claimed in
11. The system claimed in
H+=(Q 1. 4 1 4)(Q2.Q3+ 2 3 H−=(Q 2. 3 2 3)(Q1.Q4+ 1 4 Q
1, Q2, Q3 and Q4 being said four state signals and 1 2 3 4 12. A frequency control signalssystem comprising:
a voltage-controlled oscillator for generating a clock signal,;
a sampler for receiving a digital input signal having an unstable frequency and for sampling said clock signal at two pairs of times corresponding to two consecutive transitions of said digital input signal, the sampler in response to being arranged to derive four state signals of said clock signal in response to predetermined transitions of said digital input signal, said times of one pair being separated by a predetermined time-delay at most equal to half the period of said clock signal,;
a frequency comparator for combining said four state signals to form an upcounting signal only in response to the frequency of said clock signal being substantially less than the frequency of said digital input signal and to form a downcounting signal only in response to the frequency of said clock signal being greater than the frequency of said incomingdigital input signal,; and
a counter for respectively upcounting and downcounting predetermined transitions of said digital input signal in response to said upcounting signal and said downcounting signal,; and
a converter responsive to the counter for deriving a control voltage dependent on the count of said counter, the oscillator being arranged to be responsive to the control voltage.
13. A system as claimed in
14. A system comprising:
a frequency comparator; a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal; a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the frequency comparator is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions; a voltage-controlled oscillator configured to generate the clock signal with a frequency determined by the count value. 15. The system of
16. The system of
a) assert the upcounting signal in response to said sample values indicating that the frequency of said clock signal is substantially less than a frequency associated with said digital input signal and (b) assert the downcounting signal in response to said sample values indicating that the frequency of said clock signal is substantially greater than the frequency associated with said digital input signal. 17. The system of
18. The system of
19. The system of
edge transitions of the digital input signal. 20. The system of
edge transitions of the digital input signal. 21. The system of
edge transitions and falling-edge transitions of the digital input signal. 22. The system of
23. The system of
two cascaded pairs of flip-flops configured to output the four sample values, wherein a first flip-flop of each pair is configured to receive the clock signal; a subcircuit configured to receive the digital input signal and to assert a pulse in response to each transition of said plurality of transitions of the digital input signal; wherein a first of the two cascaded pairs is clocked by the pulse, wherein a second of the two cascaded pairs is clocked by a delayed version of the pulse. 24. A system comprising:
a frequency comparator; a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values to the frequency comparator in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal; a voltage-controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal. 25. The system of
26. The system of
edge transitions of the digital input signal. 27. The system of
edge transitions of the digital input signal. 28. The system of
edge transitions and falling-edge transitions of the digital input signal. 29. The system of
30. The system of
two cascaded pairs of flip-flops configured to output the four sample values, wherein a first flip-flop of each pair is configured to receive the first clock signal; a subcircuit configured to receive the digital input signal and to assert a first pulse and a second pulse in response to each transition of said plurality of transitions of the digital input signal, wherein the second pulse is delayed relative to the first pulse; wherein a first of the two cascaded pairs is clocked by the pulse, wherein a second of the two cascaded pairs is clocked by the second pulse. 31. The system of
a programmable frequency divider configured to generate the digital input signal with a programmable frequency, wherein the programmable frequency divider includes an adder, a register and a flip-flop, wherein the adder is configured to receive a programmably-selected integer value at its first input and to receive an output of the register at its second input, wherein the register is configured to receive an output of the adder, wherein the register is configured to receive a clock signal HU at its clock input, wherein a most significant bit of the register output is coupled to a clock input of the flip-flop, wherein an output of the flip-flop is coupled to a data input of the flip-flop. 32. A method comprising:
receiving a clock signal and a digital input signal; outputting at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal; changing a count value in response to transitions of said plurality of transitions; operating on said at least four sample values outputted in response to each transition of said plurality of transitions in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions; generating the clock signal with a frequency determined by the count value. 33. The method of
34. The method of
(a) asserting the upcounting signal in response to said sample values indicating that the frequency of said clock signal is substantially less than a frequency associated with said digital input signal and (b) asserting the downcounting signal in response to said sample values indicating that the frequency of said clock signal is substantially greater than the frequency associated with said digital input signal. 35. The method of
increasing the count value in response to a transition of said plurality of transitions if the upcounting signal is asserted, and, decreasing the count value in response to the transition if the downcounting signal is asserted. 36. The method of
37. The method of
edge transitions of the digital input signal. 38. The method of
edge transitions of the digital input signal. 39. The method of
edge transitions and falling-edge transitions of the digital input signal. 40. The method of
41. A method comprising:
receiving a first clock signal and a digital input signal; and outputting at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal; changing a count value in response to transitions of said plurality of transitions; generating a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal. 42. The method of
43. The method of
edge transitions of the digital input signal. 44. The method of
edge transitions of the digital input signal. 45. The method of
edge transitions and falling-edge transitions of the digital input signal. 46. The method of
47. A telecommunication device comprising:
a frequency comparator; a voltage-controlled oscillator configured to generate the clock signal with a frequency determined by the count value. 48. The telecommunication device of
49. A telecommunication device comprising:
a frequency comparator; a voltage-controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal. 50. The telecommunication device of
51. A system comprising:
a sampling circuit configured to receive a clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the clock signal; a counter configured to change a count value in response to transitions of said plurality of transitions; a frequency comparator that is distinct from the sampling circuit and is configured to operate on said sample values in order to generate one or more control signals that determine whether the counter increases or decreases the count value in response to a transition of said plurality of transitions; a voltage-controlled oscillator configured to generate the clock signal with a frequency determined by the count value. 52. A system comprising:
a sampling circuit configured to receive a first clock signal and a digital input signal and to output at least four sample values in response to each transition of a plurality of transitions of the digital input signal, wherein each of said sample values is a sample of the first clock signal; a voltage-controlled oscillator configured to generate a second clock signal with a frequency determined by the count value, wherein the first clock signal has a frequency dependent on the frequency of the second clock signal. 53. A system comprising:
decision logic configured to receive said at least four outputted sample values from the sampling circuit and to operate on said at least four outputted sample values in order to generate one or more control signals; a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the one or more control signals determine whether the counter increases, decreases or maintains the count value in response to said transition of said plurality of transitions; a voltage-54. A system comprising:
a counter configured to change a count value in response to transitions of said plurality of transitions, wherein the one or more control signals that determine whether the counter increases, decreases or maintains the count value in response to said transition of said plurality of transitions; a voltage-55. A system comprising:
a sampling circuit configured to receive a clock signal and a digital input signal and to capture a pair of samples of the clock signal in response to each of a plurality of transitions of the digital input signal, wherein the sampling circuit is configured so that the samples of each pair are separated in time by a fixed delay, wherein the sampling circuit is configured to output a current one and a previous one of said pairs in response to each transition of said plurality of transitions; decision logic configured to operate on said current pair and said previous pair of samples in order to generate one or more control values; a counter configured to increase, decrease or maintain a count value based on the one or more control values; and a voltage-56. A system comprising:
a sampling circuit configured to receive a first clock signal and a digital input signal and to capture a pair of samples of the first clock signal in response to each of a plurality of transitions of the digital input signal, wherein the sampling circuit is configured so that the samples of each pair are separated in time by a fixed delay, wherein the sampling circuit is configured to output a current one and a previous one of said pairs in response to each transition of said plurality of transitions; a voltage-Description 1. Field of the Invention The present invention relates to a frequency control system for extracting a clock signal from a high bit rate digital signal or for synthesizing a frequency. The system comprises a circuit loop including a voltage-controlled oscillator (VCO) slaved to an incoming signal of unstable frequency. 2. Description of the Prior Art The frequency control of a VCO is used in a receiver in order to extract from a digital data signal an original clock signal produced by a transmitter which transmitted the data signal. Frequency synthesis using a VCO is used in radio transmitters and receivers when it is necessary to generate precise frequencies for selecting a channel. In these two applications, the main technical problem is to extract the clock signal contained in the received digital data signal, which is affected by noise, i.e. which contains jitter, and to synthesize a precise frequency based on an unstable reference frequency. The invention has applications in the field of digital transmissions at high bit rates, up to several hundred Mbit/s, for recovering the clock signal needed to process the received data, and in the field of radio equipments, for synthesizing high frequencies, typically up to a few GHz. In the two fields of applications previously cited, it is standard practice to use a phase-locked loop (PLL) which comprises a VCO, a frequency divider which can be programmable and which is connected to the output of the oscillator to provide a divided frequency signal, and a phase comparator which delivers an error signal based on comparing the phases of the divided frequency signal and a reference signal. The amplified and then filtered error signal controls the oscillator VCO. A first difficulty encountered in the prior art, when the required frequency is high, is that of providing a divide-by-N frequency divider which is needed to synthesize any frequency equal to k.N.Fr where k is a constant, N is a variable coefficient and Fr is the frequency of the reference signal. If N is an integer, frequencies multiple of the frequency Fr of the reference signal are generated by the oscillator VCO. However, it is routine practice not to limit N to integer values, which increases the complexity of the frequency divider included in the loop and leads to insurmountable technical implementation constraints at high frequencies. A second difficulty results from the necessity to apply a very stable reference signal to the phase comparator; if this is not achieved, noise in the reference signal is multiplied by a factor k.N in the synthesized signal output by the oscillator. The main object of this invention is to overcome the aforementioned difficulties by providing a frequency control system which is based on comparing the frequencies of an incoming digital signal which has an unstable clock frequency and a clock signal generated directly or indirectly by an oscillator VCO and which is used both to extract the clock signal and for frequency synthesis, with the aim of tolerating variation in the frequency of the incoming signal about a mean value without any effect on the clock signal to be extracted or on the clock signal to be synthesized, whose frequency remains stable even in the presence of high jitter in the incoming signal. Accordingly, a frequency control system comprising voltage-controlled oscillator means generating a clock signal, means receiving a digital incoming signal with unstable frequency for sampling the clock signal at two pairs of times corresponding to two consecutive transitions of the incoming signal in response to each of predetermined transitions of the incoming signal, the times of one pair being separated by a predetermined time-delay at most equal to half the period of the clock signal, to produce four state signals of the clock signal, a frequency comparator combining the four state signals to form an upcounting signal only when the frequency of the clock signal is substantially less than the frequency of the incoming signal and to form a downcounting signal only when the frequency of the clock signal is greater than the frequency of the incoming signal, and upcounting and downcounting means for respectively upcounting and downcounting predetermined transitions of the incoming signal in response to the upcounting signal and the downcounting signal in order to apply a control voltage depending on a content of the upcounting and downcounting means to the oscillatory means. The frequency comparison in accordance with the invention is effected on the basis of two transitions of the incoming signal and not on one transition, as is generally the case in the prior art. The four state signals resulting from sampling the incoming signals at the two pairs of times for each transition can be combined by means for producing the upcounting signal for as long as three of the state signals corresponding to consecutive sampling times of the clock signal are identical, and means for producing the downcounting signal for as long as one of two state signals corresponding to sampling times of the clock signal lying between sampling times of the clock signal corresponding to the other two state signals is different from the other three state signals. In a preferred embodiment of the invention, the functions of the aforementioned two producing means are implemented in the frequency comparator by means of a first EXCLUSIVE-OR gate receiving two state signals corresponding to sampling times of the clock signal between which are sampling times of the clock signal corresponding to the other two state signals, a second EXCLUSIVE-OR gate receiving the other two state signals, a first AND gate connected directly to the first EXCLUSIVE-OR gate and via an inverter to the second EXCLUSIVE-OR gate to produce said upcounting signal and a second AND gate connected directly to the second EXCLUSIVE-OR gate and via an inverter to the first EXCLUSIVE-OR gate to produce the downcounting signal. The sampling means comprises preferably means for detecting predetermined transitions in the incoming signal in order to produce a transition signal and another transition signal delayed by the predetermined time-delay, and two pairs of flip-flops respectively producing the state signals. Each pair of flip-flops has a first flip-flop receiving the clock signal and a second flip-flop having an input connected to the direct output of the first flip-flop. The transition signal and the delayed transition signal are respectively applied to clock inputs of the pairs of flip-flops. In particular, when the incoming signal is a clock signal with an unstable frequency, the sampling means is entirely digital. In this case, the transition detecting means comprises a divide-by-four frequency divider to produce a clock signal at half the frequency of the incoming signal, and means for selecting a transition of said incoming signal and a transition in the complementary signal of the incoming signal when it has been complemented, during one half-period in two of the half-frequency clock signal in order to produce the transition signal and the delayed transition signal, respectively. When the frequency control system is used to extract a clock signal contained in an incoming digital data signal affected by noise, the system comprises means connected to the sampling means for comparing the phases of the incoming signal and the clock signal as a function of two of the four state signals in order to select from the clock signal and the complementary signal thereof an outgoing clock signal which is more in phase with the incoming signal and which is used to read the incoming signal. In this way, the outgoing clock signal is the recovered clock signal originally produced by the transmitter. In a preferred embodiment of the invention, the phase comparing means comprises latch logic means connected to the sampling means for selecting from the clock signal and the complementary signal thereof an outgoing clock signal which is more in phase with the incoming signal when the state signals produced by the first or second flip-flops of said pairs of flip-flops are respectively at first and second states and at second and first states, and a flip-flop for reading the incoming signal as a function of the outgoing clock signal. When the frequency control system is used to synthesize frequencies, it comprises divider means for generating the input signal to be applied to the sampling means in the form of an unstable reference clock signal having a mean frequency over a respective number of periods equal to a programmed frequency from a unit clock signal having a stable frequency not less than four times the programmed frequency, the ratio between the programmed frequency and the respective number of periods being constant. The frequency of the unit clock signal is therefore more than four times the highest frequency that can be programmed in the programmable frequency divider. The reference clock signal has a variable frequency resulting from programmed integer or non-integer division of the stable frequency of the unit clock signal, which is delivered by a quartz-crystal-controlled clock, for example. Variation of the reference signal frequency is inhibited in the control loop consisting essentially of the sampling means, the frequency comparator, the upcounting and downcounting means and the oscillator, with the result that the synthesized frequency produced by the oscillator is the required stable frequency, which is equal to a multiple of the mean reference clock frequency. In contrast to the prior art, the invention replaces the programmable frequency divider of prior art synthesis loops with a fixed frequency divider. Frequency divider means comprises in a preferred embodiment of the invention an adder and a buffer register clocked at the frequency of the unit clock signal and storing a sum at outputs of the adder, wherein the adder adding the sum to the respective number associated with the programmed frequency. To eliminate any distortion of the duty cycle of the reference clock signal, frequency divider means comprises a divide-by-two frequency divider receiving the most significant bit of the sum from the buffer register to generate the reference clock signal. For the application to frequency synthesis in particular, oscillatory means comprises at least one voltage-controlled oscillator controlled by the upcounting and downcounting means via a loop filter, and a frequency divider for dividing the frequency of the signal generated by the oscillator by a fixed ratio in order to generate the clock signal. The fixed ratio is preferably a power of two. The loop filter filters in particular harmonics of the unit clock signal resulting from frequency division in the programmable frequency divider. The foregoing and other objects, features and advantages of the invention will be apparent from the following detailed description of several embodiments of the invention with reference to the corresponding accompanying drawings in which: FIG. 1 is a schematic block diagram of a clock extractor circuit according to the invention; FIG. 2 shows in detail a sampling circuit included in the clock extractor circuit shown in FIG. 1; FIG. 3 shows in detail a phase comparator included in the clock extractor circuit shown in FIG. 1; FIG. 4 shows in detail a frequency comparator included in the clock extractor circuit shown in FIG. 1; FIG. 5 is a block diagram of a frequency synthesizer according to the invention; FIG. 5 shows in detail a programmable frequency divider included in the frequency synthesizer shown in FIG. 6; and FIG. 7 shows in detail a sampling circuit included in the frequency synthesizer shown in FIG. 5. Referring to FIG. 1, a frequency control system serving as a clock extractor circuit EH in telecommunication terminal or receiver includes a phase and frequency comparator CPF and a voltage-controlled oscillator VCO. The comparator CPF has two inputs to which are applied a digital incoming data signal Din, which is reshaped after transmission by a telecommunication transmitter, and a clock signal H supplied by the oscillator VCO. In the comparator CPF, comparing the phases of the signals Din and H produces an outgoing data signal Dout and an outgoing recovered clock signal Hout which are synchronized and in phase. Comparing the frequencies of the signals Din and H in the comparator CPF produces a variable voltage analog control signal VC for direct control of the oscillator VCO, in order to generate the clock signal H having a frequency set to the mean clock frequency of the data signal Din. The phase is compared in the phase and frequency comparator CPF by means of a four-state sampling circuit Referring to FIG. 2, the sampling circuit The sampling circuit The rising and falling edges of the data signal Din are detected by the EXCLUSIVE-OR gate As an alternative to this, instead of detecting the rising and falling edges of the signal Din, only the rising edges or only the falling edges are detected. For example, predetermined falling edges are detected by inserting an inverter on the output side of the delay line The flip-flops The third delay line Each delay line can be implemented using a string of inverters. Referring to FIG. 3, the phase comparator The output Q For reading the incoming data signal Din, the phase comparator When Q The logic states of the phase comparator
Alternatively, the inputs of the converters In the frequency comparator If three consecutive states out of four are identical, i.e. if For example, if at times T The truth table for the frequency comparator
In the above table, the out of band decision signifies that the received data signal Din is at much too high or too low a frequency outside the lock-on band of the oscillator VCO or contains non-conform jitter. In this case, it is preferable for a logic circuit (not shown) implementing the logic function ( The above truth table satisfies the following logic equations:
In conformance with the above two logic equations, the frequency comparator Accordingly, the frequency comparator For as long as it is at 1, the upcounting logic signal H+ sets the upcounter-downcounter The capacity of the upcounter-downcounter If the data signal Din is subject to jitter, the amplitude of the jitter can reach the peak value Gmax such that Gmax=TD/2−dt, where TD is the period corresponding to the bit rate of the incoming data signal Din. A second embodiment of the frequency control system according to the invention is a frequency synthesizer SF as shown in FIG. 5. The synthesizer includes a sampling circuit The frequency synthesizer SF therefore uses loop circuits for the frequency comparison, like the clock extractor circuit EH. The frequency synthesizer SF also comprises a programmable frequency divider The frequency FS of the clock signal HS from the oscillator VCO is divided by the fixed integer ratio M in the frequency divider To obtain a set of I ordered frequencies FS The frequency synthesizer SF according to the invention is based on the hypothesis that the reference frequencies Fr -
- TB=N.TU=1/p
- frequency unit FU=1/TU=p.N, and
- the period of the selected reference signal Tri=1/Fri=TU.N/Pi.
As a result, computing the period Tri of the reference signal Hri amounts to computing how many times the number Pi is contained in the number N. For this, the invention proposes to add the number Pi to itself at the timing rate TU until the number N is obtained and on each computation to produce a sample at 0 if the computation result is less than N/2 and a sample with value 1 otherwise. However, the number Pi associated with the frequency Fri of the reference signal Hri to be synthesized is not necessarily an integer factor of the integer N after the computation. Let r
the numbers (N+r _{1}), (N−r_{1}+r_{2}), (N−r_{2}+r_{3}), . . . , (N−r_{Pi-1}+r_{Pi}) being integer multiples of Pi. The last overflow rPi is equal to zero since the sum of the latter numbers NPi=r_{Pi }is a multiple of Pi.
The sum of Pi consecutive synthesized periods Tri is therefore equal to N.TU and the mean period generated over the duration N.TU is equal to:
The mean of the periods generated by the synthesizer is indeed equal to the required value Tri. The generated signal is frequency-modulated because a period Tri is generated to within TU in each computation cycle that corresponds to the first, second, third, . . . or Pth period Tri. The maximum amplitude of the jitter is therefore equal to TU. As indicated hereinafter, the frequency comparator Furthermore, the signal generated by the cyclic additions does not have a duty cycle equal to 0.5. It is necessary to divide the frequency of this signal by two to eliminate the distortion of the duty cycle; this condition is complied with by applying the conditions FU≧2.FrI=4.Fr. FIG. 6 shows the programmable frequency divider The reference signal Hr is frequency-modulated because it is generated in the programmable frequency divider Referring again to FIG. 6, the binary word Pi on q bits and the cumulative result R delivered by the register To summarize, the equations of the programmable frequency divider are as follows: -
- FU
_{min}=2.FrI - N
_{min}=FU_{min}/p, - N being preferably as N=2
^{q}>N_{min}; - FU=p.N
- Tri=TU.N/Pi=1/(p.Pi)
- Fri=p.Pi.
- FU
A numerical example is given below. Consider an oscillator VCO which must generate frequencies FS equal to 1200, 1250, 1300, 1350 and 1400 MHz. Knowing that the divider Fr From this it can be deduced that:
For example, for Pi=26 the reference frequency is Fr=Fri/2=p.Pi/2=1.26953125 MHz. In the sampling circuit In a preferred embodiment of the invention shown in FIG. 7, the sampling circuit The digital means Because the programmable frequency divider -
- where TD is the period of the clock signal at the input
**1**H. Because the period TD is obtained from the period Tr of the reference signal Hr by integer division by M, the following equation applies: TD=M.Tr, - from which the time-delay is deduced:
dt=M.Tr/4−Tr/2. For the smallest time-delay dt=Tr/2 which can be obtained in a digital circuit from a signal of period Tr, the optimum solution deduced from the above equation is M=4.
- where TD is the period of the clock signal at the input
In the embodiment of the invention shown in FIG. 7 the aforementioned digital means The two clock signals H Patent Citations
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