|Publication number||USRE41040 E1|
|Application number||US 11/115,103|
|Publication date||Dec 15, 2009|
|Priority date||Nov 19, 2001|
|Also published as||US6556461|
|Publication number||11115103, 115103, US RE41040 E1, US RE41040E1, US-E1-RE41040, USRE41040 E1, USRE41040E1|
|Inventors||Yuri Khersonsky, Robert H. Lee|
|Original Assignee||Power Paragon, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Non-Patent Citations (2), Referenced by (1), Classifications (5), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to the field of DC to AC inverters, particularly those producing power at a high voltage sinusoidal waveform for powering equipment requiring high voltage AC power at frequencies or voltages that are independent of the frequency or voltage of a conventional AC power source.
In the past, systems to convert DC to high voltage AC suffered from various shortcomings. The available AC output voltage from inverters was generally limited by the voltage rating of available power semiconductors in the converter. In the past, operating power semiconductors in series had not been seen as a practical solution because of the difficulty in achieving simultaneous switching of series sets. Nevertheless, in the present invention, several methods are described for operating a number of AC power stages in series wherein the output AC voltage can be achieved at arbitrarily high levels.
The need for such inverters is usually in the operation of high power motors. It is common for such motors to require input voltages in the range of 4.16 KVAC to 13 KVAC. If a voltage of 4.16 KVAC is to be generated in a single stage, and if the power semiconductors are selected to have a conservative 50% voltage margin, then the DC source voltage must be approximately 3600 VDC and the semiconductors would require a rating of 5400 Peak volts. In order to deliver controlled AC voltage with low harmonics to an AC load, it is generally a requirement that the switching speed be high. However, high voltage devices tend to have high switching losses and so it is not practical to use high voltage power semiconductors to control high AC output voltages in systems requiring high repetition rates for the switching devices.
One alternative is to use a plurality of series connected pulse width modulation (PWM) inverters to achieve high AC output voltages. However this alternative is relatively expensive and complicated.
The present invention achieves high frequency switching and use of high voltage semiconductors without incurring high switching power losses. The present invention utilizes a pair of step wave generators in conjunction with a single PWM inverter in series connection to generate each phase of the AC output voltage. Since the step wave generators are operated at a relatively low frequency (low repetition rate), high voltage devices are readily available for such duty. A single set of relatively low voltage power semiconductors are operated in PWM mode (at a relatively higher frequency) to “fill in” the steps in the waveform generated by the step-wise output of the step wave generators or inverters.
The present invention uses a pair of step wave generators (SWG) or voltage inverters along with a pulse width modulator (PWM) to form waveform segments to “build” a sinusoidal voltage waveform having a voltage in excess of the voltage of any of the step wave voltages or the pulse width modulated waveform alone. In particular, in a preferred embodiment, two step wave generators have an amplitude ratio of 6 to 2, along with a pulse width modulator having an amplitude of 1. More particularly, one step wave generator has an output of ±6 units, while the other step wave generator has an output of ±2 units, and the pulse width modulator has an amplitude of ±1 unit. Such an arrangement enables utilization of power semiconductors to deliver an ultimate voltage waveform output that is higher than the voltage ratings of the devices used, without subjecting the semiconductors to over voltage stresses, while not requiring dedicated balancing circuitry or a control to regulate the voltages across series connected devices.
Referring now to
Referring now also to
Referring now also to
Waveform 52 illustrates the output of the SWG 14 on line 18 18′ (without showing the PWM waveform superimposed). A sine wave output appears on line 26 as indicated by waveform 60. As indicated in
The SWG (sine step wave generator) subsystem 14 produces a quasi-square wave waveform 52 having three states: a +ON state 54 with a magnitude of +2, a ZERO state 56 (connected to circuit common 24) with a magnitude of 0, and a −ON state 58 with a magnitude of −2. It is to be understood that the SWG subsystem is controlled to be in the ZERO state 56 during half segments 42 and 50 as well as during segment 46. In operation, the SWG waveform 52 will repeat itself over and over, controlled by the control subsystem 16 to be synchronized with the segments 42-50 of the PWM subsystem 12. In a manner to be described in more detail infra, waveform 52 is added to the pulse train represented by waveform 40, resulting in sine wave 60 having a maximum amplitude of 3. It is to be understood that the magnitude values expressed above are merely relative numbers, and that the actual voltages may be as desired. It should also be noted that the waveform targeted may be other than sinusoidal, if desired, and furthermore, harmonics may be included in the target.
Once the waveforms 40 and 52 are added together, the result is passed through the filter 20, resulting in an actual sinusoidal waveform corresponding to sine wave target 60. It is to be understood that the sine wave output can be generated with a high level of precision, so that it is substantially free of harmonics. Remaining traces of the PWM frequency in the sine wave can be reduced using conventional filtering.
A simple L-C filter can be used to reduce the PWM voltage magnitude to an arbitrarily low value. For example, if it is desired to provide a 60 Hz sine wave with an RMS magnitude of 1 unit, with the PWM voltage limited to 0.1% of the sine wave. The PWM switching bridge circuit can be made up of two IGBT transistor pairs. Each IGBT pair will be switched at a 6 KHz rate.
The two pairs are operated in combination so that the resultant PWM output is doubled to 12 KHz. Simultaneously, the operation of the two pairs in combination can be made to reduce the PWM voltage to half the magnitude of a single set of IGBT's. Referring to
As an approximation, the PWM component of voltage is 60% of the sine wave output voltage. The expression “PWM component of voltage” means all frequencies that are at the PWM frequency or harmonics of the PWM frequency. This is because the RMS value of voltage having a sine wave form is 0.707 of the peak voltage, whereas the RMS value of a square wave is 1.0 times the peak voltage. A square or rectangular wave can be considered to be the sum of harmonics in a Fourier series that represents a square wave. With a square wave having a magnitude of 1, the “nth” harmonic will have a magnitude of 4/(n×pi) or 1.27/n. Setting n=1 yields the result that the peak magnitude of the fundamental frequency in the PWM waveform may be as high as 1.27 for a square wave of magnitude 1.
The PWM waveform higher harmonics are attenuated by an LC filter inversely as the harmonic magnitude squared. For example, the 5th harmonic has a magnitude of only 20% of the fundamental. It is attenuated by an L-C filter as 1/(5)2=1/25. Thus the 5th harmonic has a magnitude of 1/25th of the fundamental at the output of the filter. Higher harmonic frequencies that are in the PWM waveform are attenuated by much higher factors than the fundamental frequency in the PWM waveform.
The magnitude of PWM voltage that represents a sine wave is varying in effective magnitude throughout the sine wave cycle. As the sine wave crosses zero, the PWM fundamental component output from the bridge circuit is equal to 1.27×0.5=0.635×the sine wave magnitude. The effective PWM voltage magnitude changes with each cycle, until it has a minimum value when the sine wave is at a peak. As a practical matter, the PWM waveform maximum voltage must be higher than the magnitude of any waveform that is being targeted and defined by the PWM switching pattern. Because of the variations in the PWM waveform over a full cycle of the target waveform, the effective fundamental component in the PWM waveform can only be approximated. The 60% magnitude value mentioned above is only an estimate of what might be expected in practice.
When a step wave of magnitude double that of the PWM bridge is added to the output of the PWM bridge, the PWM voltage becomes 60%/3=20% of the targeted sine wave voltage. Using an L-C circuit to filter the AC output, an inductor may be used which has an impedance of 0.05 of the load impedance, it being understood that one unit of load impedance is equal to the output voltage rating of an inverter divided by the output current rating. For example, using a 100 KVA 60 Hz inverter with an output voltage of 3 phase 480 VAC line to line or 277 VAC line to neutral, the rated output current is 100,000/(sqrt 3×480)=120 amperes. One unit of voltage is 277 VAC, and one unit of current is 120 Amps, AC. For a WYE connected load, one unit of impedance is 277/120=2.3 ohms. An impedance of 0.05 units for this example will be 0.05×2.3=0.115 ohms. Corresponding inductance is: impedance/(2×pixfrequency)=0.115/(2×pix60)=0.000305 Henrys. If the PWM frequency is 12 KHz, the PWM frequency impedance (i.e., the impedance at the PWM frequency) is then 0.115×12,000/60=23 units. Since one unit is 2.3 ohms, the actual impedance of the inductor at the PWM frequency will be 2.3×23 or 52.9 ohms. It is to be understood that the process of selecting the filter inductor starts with an estimate of what remaining value of PWM current will be acceptable in the output to the filter capacitor and load circuit. Then an estimate is made of the maximum fundamental value of PWM current that will be present at the source. The filter inductor impedance must then be equal to (PWM voltage)/(acceptable maximum PWM current). In making such calculations, it has been found convenient to user per unit values. It is also to be understood that for conventional filter values, the resistance is negligible, permitting use of scalar arithmetic, instead of vector arithmetic.
A capacitor of conductance 0.1 at 60 Hz will have a conductance of 200×0.1 =20 units at 12 KHz. The attenuation of the PWM voltage will then be approximately 1/(20×10)=0.05. This value multiplied by the 20% PWM voltage equals a factor of 0.001 or 0.1%.
Turning now to control subsystem 16, the most direct strategy for control is to utilize a real time digital controller which will compute the target value of currents (or voltages) ahead of each time cycle. If a 12 KHz PWM frequency is used, then a time interval for the period of the PWM waveform will be 1/12000 seconds, or 83 microseconds. This provides adequate time to determine the source voltage which is made up of the step waves and the PWM wave for the next portion of the cycle. The fact that the calculation is made in the time interval before action takes place is compensated by taking into account where the target voltage must be at the (subsequent) time of execution. By using digital control, harmonics generated by the load can also be compensated, so that the sine wave will be accurate regardless of non-linearities in the load. One known simple and effective method for harmonic removal is to digitize the output waveform and analyze the digital data to extract and then subtract the fundamental component from the data, leaving only harmonic data. Next, the difference data (the harmonic data) is subtracted from a subsequent waveform, and the process is repeated, with confirmation of the result obtained by digitizing a following actual waveform. The process is preferably repeated, which will also take harmonic variations due to time varying load changes into account.
Referring now to
The system 70 of
The objective is to create a relatively smooth target voltage waveform, which usually would be a sinusoidal voltage, although it is within the scope of the present invention to form waveforms other than sinusoids, if such is desired. Bridge A has the switches numbered 1 through 4, as shown in FIG. 6. In
To obtain a zero output from bridge A, switches 2 and 4 are closed while switches 1 and 3 are open. Alternatively, switches 1 and 3 may be closed while switches 2 and 4 are held open. To obtain a positive voltage from bridge A, switches 2 and 3 are closed while switches 1 and 4 are opened. To obtain a negative voltage from bridge A, switches 1 and 4 are closed while switches 2 and 3 are opened. To obtain a quasi voltage waveform the switches 1-4 are operated synchronously with the target AC output voltage at the same frequency and in phase.
A second quasi waveform 80 from bridge B may be added to the waveform 82 from bridge A, with the quasi waveform 80 from bridge B changed in timing as compared to that from bridge A, so that the summation more closely approaches the target waveform. Similarly, it is to be understood to be within the scope of the present invention to add additional quasi-square waves, such as 3rd, 4th, 5th etc. quasi-square waves to more closely approach the target waveform.
Bridge C (in block 12) is operated in a PWM mode at a frequency very much higher than the fundamental frequency of the target voltage waveform. Bridge C is operated in such a manner as to fill in the steps of the quasi square wave forms, so that the resulting waveform can quite precisely approach the targeted sinusoidal voltage waveform.
Filter 20 preferably has a low pass characteristic to eliminate or minimize harmonics resulting from the PWM output on line 18, and the result is a relatively smooth sine wave 84. This can provide a waveform in which undesired harmonics are substantially eliminated.
It is to be noted that each switching bridge circuit requires its own isolated DC power source. Thus for the circuit 70 illustrated in
The various circuits of the present invention are well suited for applications extending up to high voltage, high power AC motor control systems. In such high power applications it is often the case that no individual power semiconductor is available with adequate current rating to match up with the actual load. In this event, multiple bridge semiconductor bridge circuits are required in order to manage the power. In the practice of the present invention, placing switching bridge circuits in series assures current sharing between stages. Operation of the motor at a high AC voltage keeps the AC current levels at low values that reduce current loading of the conductors in the motor stator.
When the neutral is floating, triplen harmonics may be deliberately introduced into the target waveform. Introduction of these harmonics permits operation at a lower DC voltage applied to each switching section and the triplen harmonics are eliminated in the line to line voltages by the floating neutral connection. If approximately 15% of 3rd harmonic is introduced into the target sine wave form in phase with the fundamental, then the peak of the resulting voltage wave is reduced in the ratio of 1:1.15, or about 0.87%, of the sine wave by itself. Now the DC voltage at the source can be reduced in this same ratio. The result will be an output waveform of the same shape as the target, which is the combination of a fundamental and a 3rd harmonic. However, in the 3 phase configuration the 3rd harmonics cancel, leaving only a relatively pure sine wave in the line to line connection.
If the target waveform is 4160 VAC line to line, the line to neutral will be 2400 VAC. This sine wave will have a peak value of 1.41 times the RMS value and to make up for losses this is desirably increased to approximately 1.5. Multiplying 1.5×2400 VDC=3600 VDC. If the lowest voltage semiconductor must support ⅕ of this value, the DC voltage for the PWM stage must be 3600/5=720 VDC. However, with the introduction of the 3rd harmonic in the target waveform this is reduced by a factor of 0.87=626 VDC. This would permit use of 1200 volt IGBTs instead of 1400 volt rated IGBTs. There will then be a substantial reduction in switching losses in the lower voltage IGBTs. Similarly, the high power stages must each support 20% of 3600=1440 VDC, and this is reduced to 0.87×1440=1250 VDC. This permits use of readily available 2500 VDC IGBTs for the square wave switching semiconductors.
The quasi-square waveforms have the advantage that the repetition rate is low and so switching losses are low. The disadvantage of using only quasi waveforms to construct a target voltage is that the steps create low frequency harmonics that are difficult to filter.
The advantage of using PWM switching waveforms to create the target waveform is that all of the low frequency harmonics that are not targeted can be eliminated by the switching algorithm, leaving only the high PWM frequencies to be filtered. If the low frequency harmonics were allowed to remain, they would be difficult to filter in that components required are tend to be large and heavy, and incur high losses. In contrast, the filter components for the higher frequency harmonics only require small, light weight, and low loss components. Furthermore, low frequency harmonics are particularly bad for motor drives, because they cause torque ripple and heating in the motor. Torque ripple can cause an increase in audible noise in the motor, and may limit the motor from being able to supply rated output torque.
Reduction of low frequency harmonics in a non-linear load can be accomplished by the control algorithm, with only a small additional cost. In contrast, however, the PWM frequency can only be removed by filtering.
In the system described for
The switching algorithm is a mathematical process by which the magnitude and timing of the step waveforms and the PWM waveforms are calculated in order to achieve the target value of the desired waveform. In general, more than one technique is available to accomplish this task. When a “real time” algorithm is used (in contrast to a look-up table) the equations must generally use only few steps because of time of execution limitations. One method to establish a switching pattern to create the PWM waveform is as follows.
This method involves the control of the output current, I, and as consequence, the output voltage ET is controlled. The target current waveform illustrated in
If it is assumed that the output voltage is sinusoidal (in response to a sinusoidal current flowing in a linear load) then the drive voltage will be the instantaneous difference between the PWM voltage and the output voltage. Whenever the current reaches the upper target level, the PWM voltage is reversed. Current then falls at a rate equal to (−1−ET)/L. When the current reaches the lower limit, the PWM voltage goes to +1 and the current rises in ratio to (1−ET)/L until it reaches the upper limit. Thus the actual current is oscillating between preset limits above and below the target current.
It is to be understood that this type of PWM control does not have a fixed cycle time, the PWM cycle time is set by the integration process that causes current changes. Consequently, the PWM rate varies throughout the sine wave cycle. This type of control has been found to be satisfactory for motor speed and torque controls, since torque is approximately in ratio to the current. This means that motor torque can be controlled independently of motor speed, over a relatively wide range.
The particular method described above has been used successfully in actual applications, even though it has a disadvantage in that the PWM waveform is not synchronous with the waveform copied, possibly introducing unwanted “noise” in the waveform.
A second alternative control algorithm is as follows. A digitized sine wave is established in the control logic. The sine wave is approximated by making it stepped. In order to make the calculations simple, the steps are made to correspond to a fixed time interval, preferably 2 degrees. It is preferable to make the PWM frequency an integer divisor of the period of the output waveform. If it is not, undesirable sub harmonics will result and the positive and negative half cycles may not have symmetry. If the output waveform is to be 60 Hz and the PWM operation is at 180 steps per cycle, then the PWM rate would be 180×60=10,800 Hz. Each step is assumed to cross an ideal sine wave at the center of the step. The objective is to make the output from each step have an average value that is equal to the waveform value in the logic that is the target. The DC source voltage must be higher in magnitude than the peak of the target sine wave. Assume a DC voltage of 1.2 units. This value applies to the output voltage. For example, the step that extends from 179 to 181 degrees must provide an average voltage of zero, corresponding to 180 degrees. The time interval [T] for one step is 1/(60×180)=92.6 microseconds. Here the PWM voltage must be at +1.2 units for half of the step interval and −1.2 for the balance of the step interval, in order to achieve an average voltage of zero. The time intervals for positive and negative voltages required to achieve the correct voltage for 45 degrees where the average value of voltage=0.7071 is as follows. For a time interval [a], the value is positive, and for a time interval [T−a] the value is negative. Using 0.7071=[1.2×a−1.2×(T−a)]/(92.6×10−6), a=73.58 microseconds with a value of +1.2 and [T−a]=19.02 microseconds with a value of −1.2. It is to be understood that if the DC voltage changes, the averaging process will make the necessary correction in the positive time interval and the negative time interval for each PWM cycle.
It is to be understood that the PWM cycles apply to each IGBT pole pair. When the complete bridge circuit is operated with 2 pole pairs, the PWM output frequency is doubled and the PWM output has 3 states which are −E, 0 and +E. (It is to be understood that “E” is equal to the value of the DC bus, and “0” indicates a positive connection to circuit common enabling current flow without any voltage potential at the output terminal, in each case ignoring the forward drop of the conducting power devices in the bridge.) This has the effect of reducing the PWM voltage at the bridge output to half of the PWM magnitude for each pole pair. In the example above the apparent PWM frequency becomes 2×10.8=21.6 KHz and the peak to peak voltage is E and not 2E as in the calculation.
A feedback circuit and voltage attenuator are connected to the actual AC output voltage so that the sine wave in the logic and the sampled and attenuated actual output waveforms will be matched. The overall magnitude of the actual output voltage is controlled by adjustment of the attenuated sample waveform. The feedback circuit automatically changes the output by multiplying the error signal by the gain in the logic to provide the correct target sine wave of voltage. If harmonic correction is to be included, the harmonics must be added to the target waveform in the logic. This correction is done not more than once per complete 360 degree cycle. Since a harmonic frequency is always an integer multiple of the fundamental waveform, one complete cycle of the AC output fundamental and the desired harmonic must be presented as the target for the PWM operation to copy.
One disadvantage (of using a PWM switching waveform to create the target waveform) is that the semiconductors that are typically used for PWM duty usually exhibit high switching losses. Further disadvantages are that the high switching frequencies create high losses in filter components and may cause substantial audible noise. In the practice of the present invention, these disadvantages are reduced in their effect because the PWM is used only for a portion of the output waveform, in contrast to using a PWM alone.
By means of a combination of quasi-square waves and PWM waves, the best features of both can be used. Most of the fundamental power is switched in quasi square wave mode, and the PWM is used only to trim the waveform so that the low frequency harmonics that would be exhibited by the quasi square waves alone are eliminated. The PWM waveform in this example deals with a maximum of 20% of the total power. Consequently, low voltage switching devices can be used, which may be operated at high frequencies, limiting switching losses to relatively low levels. In the embodiment illustrated in
The PWM control can be fast acting and can cause corrections within a few PWM cycle intervals, whereas the step waves can only control each half cycle of the target waveform. In general, there may be a 100:1 or greater difference between the two cycle times. The control applies to both the step wave and the PWM waveforms. The step wave “on time” is a function of the magnitude of the target waveform. For a lower value of target sine wave, the step is made more narrow. For a very low value of target voltage, the steps may not be required, and only the PWM waveform is used to control the output voltage. It should be noted that in spite of using steps, the magnitude of the output voltage may be considered to approximate a continuously variable quantity by making the increment or decrement of the AC output voltage arbitrarily small.
It is to be understood that the control system takes account of the target value of sine wave voltage and the program utilizes only those steps of the SWG blocks that are required, combined with the PWM voltage to achieve the target voltage. The sequence is to first determine the states required by the step waves and then with the knowledge of the value of the sum of the step voltage, the PWM voltage (as determined by control of or relative duration of the +E and −E outputs of the PWM) must be controlled to deliver the difference between the target sine wave and the sum of the step voltages. The process is to determine the entire PWM waveform by calculations that are typically 1 to 2 PWM time steps prior to action. The appropriate interval in which the step waves are turned on is controlled by the logic that regulates the magnitude of the PWM waveform. When the PWM action represents the highest value of voltage of which it is capable, then on the next step, the square wave is utilized and the PWM calculation takes account of having added a step. The result is that the next PWM waveform represents the minimum value of which it is capable. In the output waveform this appears as an average PWM voltage with a value that is close to its neighboring PWM voltage. It is to be understood that the total PWM width of time at maximum and time at minimum is fixed by the logic during the cycle prior to execution. The ratio is changed to obtain a target value of PWM voltage which is defined as the average value of voltage within the PWM time interval. The PWM interval is the time during which one cycle of PWM action takes place. If the PWM action is at 10 KHz, then the time interval is 100 milliseconds. A change in step wave is inserted whenever the ability to represent the target output voltage with the PWM action has reached an upper or lower limit. The PWM action must be capable of more range of voltage than just enough to match the incremental step wave voltage change. If not, the step wave change may be required to switch during a following cycle. To avoid this requirement, the PWM voltage range is extended slightly beyond the incremental value of the step wave change. For example, if the step wave change has a value of 1 unit, the PWM waveform must be able to generate output voltage to slightly more than ½ unit. If the PWM is carried, e.g., to 0.52 units, and the step wave is incremented, on the return during the next quadrant the sum of the PWM and step wave may be carried to 0.48 units before the step wave is switched to the ZERO state and the PWM thereafter operates with the step wave at 0 units.
Target voltage is to be understood to be the complete waveform that is desired in one complete cycle. Consider the waveform to be sliced into segments at time intervals equal to the PWM cycle time. The algorithm makes the segment voltage average value equal to the target voltage over one particular PWM cycle. Within each time segment, the voltage is at maximum positive value for a time interval and maximum negative for the balance of the PWM time interval. The sequence of all segment voltages is a stepped waveform which approximates the target voltage when filtered.
It is to be understood that each PWM cycle must provide an average voltage during the interval that is equal to the target voltage for that interval. For example, suppose that the target voltage is +300 volts and the source DC voltage is 400 volts. Then during the interval, the voltage must be equal to 400 volts for 75% of the time and equal to zero for the balance of the time. Note that in the bridge configuration, the available voltage is not just plus 400 or minus 400, but may also take the value of zero.
The segment voltage must be determined so that when added to the step waves, the target value of sine wave is attained during that interval. When this is done for each interval, the result is a relatively smooth sine wave. It is to be understood that the target voltage is the complete waveform that is desired in one complete cycle.
It is to be understood that a look up table can be used for control in the practice of the present invention. However one cannot then correct for non-linearity in the load, which may be generating undesirable harmonics. The lookup table can be used to provide numerical values for the target waveform. The digitized target harmonic voltages can be added, and the sum of these becomes the target voltage.
As has been mentioned, it may be found practical to utilize high voltage IGBTs in the step waveform stages, and low voltage IGBTs for PWM switching. High voltages IGBTs exhibit high power losses if the switching is at high frequency. Losses in the high voltage IGBTs are thus reduced to low levels, while low voltage IGBTs are used in PWM mode.
It can be seen that in this mode, two step waves are used in series with the PWM waveform. While the circuit of
A relatively low output magnitude condition is shown for system 70 in FIG. 11. In this condition, a sine wave target wave 120 has a magnitude of 0.2 of the maximum, or 1.8 units. In this condition, the output 122 of the first step wave generator 14 remains at zero, and the output 124 of the second step wave generator 72 operates at the base frequency, with an amplitude of 2 units. The PWM 12 has an output waveform 126 in this condition with an amplitude of 1 unit. A staircase waveform 128 is the same as the second step waveform 124.
With respect to the operation depicted in
It is to be understood that the invention described herein is illustrative and not exhaustive of the various ways of carrying out the present invention. For example, the series connection of the subsystems 12, 14 and 72 may be rearranged, as desired, provided that all three subsystems remain in electrical series connection.
By way of further explanation of the present invention, the following may also be used using the same three stages of switching power semiconductors. For the following example, the voltages of operation are in the ratios of ±1 for the PWM, and ±2 and ±6 for the two SWG stages. The semiconductors in set A are the PWM which uses a DC supply voltage with a relative magnitude of 1 and operates to deliver a pulse width modulated output. Set B uses a DC supply voltage magnitude of 2 and operates in a quasi-square wave output mode, but at three times the fundamental frequency. Set C operates with a DC supply voltage of magnitude 6 and operates in SWG mode. The summation of sets B and set C provide voltage magnitude values (or more precisely ratios) of 0,±2,±4,±6 and ±8. To obtain a voltage of magnitude +4, set C has no output of +6 and set B has a magnitude of −2 and the sum is then +4. To obtain a voltage of magnitude +8 set C has an output of +6 and set B has an output of +2 so that the summation has the desired magnitude of +8. The total magnitude of the voltage by summation of sets A+B+C can be 9 (by the addition of 6+2+1), with a resolution of “2” in the stepped voltage. The PWM will provide a much finer resolution (typically, <<1), depending upon the operating frequency of the PWM and the filtering used.
If this method is used to obtain an AC output with a peak AC voltage magnitude of 3600 volts, then one unit of peak output voltage would have a magnitude of 3600/9=400 volts. Thus set A would operate at 6×400=2400 DC volts. Set B would operate at 2×400=800 volts DC. Set C would operate at 400 volts DC. In this, instance the semiconductors are preferably either thyristors such as silicon controlled rectifiers (SCRs) (with conventional commutation circuits) or GTOs because of the high operating voltages.
Using the techniques of the present invention, alternative circuits may be constructed to deliver higher AC voltages such as three phases 13.8 kV. In this instance, the summation of DC voltages must add to 11,300 volts. Using 3 units configured as C, one as B and one as A, the total number of voltage units would be 3×6+2+1=21 units. 11,300/21=538 volts per unit. Thus each configuration C stages would operate with a DC voltage of 6×538=3228 VDC. The B set would operate at 2×538=1076 VDC, and the A set would operate at 538 VDC.
Another example of the present invention is as follows. If a target load of 10 MVA at 3 phase 4160 VAC is desired, with the ability to vary the AC voltage from 0 to 4160 VAC and the frequency from 0 to 120 Hz, rated load current would then be 1390 amps AC[10 MVA/4160/sqrt(3)]. For a motor drive there is desirably 50% over current capacity in the power section, for a total of 2100 amps.
For a 3 phase 4160 VAC line to line system, the line to floating neutral voltage is 2400 VAC. The peak AC voltage in each phase is then 1.41×2400=3393 volts. Additional voltage is required to compensate for losses, resulting in a 3600 volt DC source required. The quasi square wave at base frequency must provide ⅔ of the AC voltage or 2400 VAC peak, and so this SWG must have a 2400 VDC source. The quasi square wave at 5× base frequency must have a magnitude of ⅓ of this value, or 800 VAC and must therefor have an 800 VDC source. The source for the PWM must produce a waveform having peak values of +400 VAC and must therefor have a source slightly greater than 400 VDC, because it is not practical to deliver a PWM output equal to the dc source value. A practical value would be 500 VDC for this application example. A disadvantage of this arrangement is that 3 different ratings of semiconductors are required. IGBTs having a rating of up to 3300 peak volts would be suitable for the first step wave generator, and IGBTs with a rating of 1400 peak volts would be suitable for the second step wave generator. The PWM IGBTs could be rated at 1000 peak volts, with capability of PWM rates above 10 KHz, with relatively low power losses.
The IGBT devices selected to switch the 800 VDC source will operate at the rate of 720 Hz. These devices are preferably selected to have a peak voltage rating of 1400 volts and a current rating of 1200 amps. For this application, three such devices are connected and operated in parallel for each switch position.
In the 5 step arrangement, the source voltage for PWM operation is ⅕×3600=720 VDC. The source voltage requirement for the first and second step waves is ⅖3600=1440 volts peak. In this instance, two types of IGBT semiconductors are preferred. An IGBT with a rating of 2500 peak volts is desirable for the quasi square waves of the first and second square wave generators, and an IGBT with a 1400 peak volt rating is desirable for the PWM operation at frequencies up to approximately 5 KHz.
Some power semiconductor devices which are suitable for application in embodiments of the present invention include a Mitsubishi Electric Corporation Gate Turn-Off Thyristor, model FG4000BX-90DA for high voltage, low frequency duty. Suitable IGBT modules may be obtained from eupec, Inc. under model numbers FZ2400R17KF6C B2 (for a mid voltage PWM at, for example, 5 times base frequency) and FZ 2400R 12 KL4C (for low voltage PWM duty at, for example, 12 KHz). It is to be understood that other GTO and IGBT devices and modules (from the same or different manufacturers) may be appropriate, depending upon the parameters of the embodiment application.
It is to be noted that the rectifiers for the DC sources must be transparent to power flow. One practical rectifier system is to use a synchronous rectification using the same technology as that described for the SWG. Such a system will be able to provide DC power with no ripple and negligible harmonic feedback to the AC power mains. A synchronous rectifier system permits back flow of power and can present unity power factor to the source at all load conditions.
It is to be further understood that snubbers are required in all high voltage switching circuits. These generally take the form of a small value of capacitor and a series resistor. The snubbers add to losses, but are a requirement to protect the power semiconductors from excessive dV/dt stress.
The feedback voltage regulator control system must be responsive to the load requirements and is preferably not affected by source impedance or output impedance of the inverter. It is to be understood that the DC power supplies for the PWM and the step wave generators for magnitude 2 must be transparent to power flow because the power flow reverse under some operating conditions. The stages with magnitude 6 do not require reversible power flow because in every cycle the net power flow from the source is positive. Typical line voltage may vary as much as ±10% from rated values.
To prevent EMI interference in equipment associated with high power inverters and to prevent interference with the function of the control circuits on the inverters and the rectifiers, conventional EMI filters are preferable, along with conventional shielding.
According to one aspect of the present invention, additional stages may be added to increase the output magnitude as desired, using additional square wave generators having a relative magnitude of ±6 units. Because the additional stages are are each limited to 6 units, the system output can be increased as desired, using relatively low rated components in the individual added stages. According to this aspect of the invention, “n” additional square wave generators can be added in series with the 1 unit PWM and 2 and 6 unit SWG's, where “n” is a positive integer, taking on a value from the series: 1, 2, 3, . . .
This invention is not to be taken as limited to all of the details thereof as modifications and variations thereof may be made without departing from the spirit or scope of the invention.
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|US8525328||Jul 14, 2011||Sep 3, 2013||Industrial Technology Research Institute||Power device package structure|
|U.S. Classification||363/41, 363/71|
|Sep 23, 2010||FPAY||Fee payment|
Year of fee payment: 8
|Jul 18, 2011||AS||Assignment|
Owner name: L-3 COMMUNICATIONS CORPORATION, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:POWER PARAGON, INC.;REEL/FRAME:026609/0401
Effective date: 20110119
|Dec 5, 2014||REMI||Maintenance fee reminder mailed|
|Apr 29, 2015||LAPS||Lapse for failure to pay maintenance fees|