|Publication number||USRE41068 E1|
|Application number||US 09/968,977|
|Publication date||Jan 5, 2010|
|Priority date||Aug 31, 1995|
|Also published as||US5640023, US5804472|
|Publication number||09968977, 968977, US RE41068 E1, US RE41068E1, US-E1-RE41068, USRE41068 E1, USRE41068E1|
|Inventors||Artur P. Balasinski, Kuei-Wu Huang|
|Original Assignee||Stmicroelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (23), Classifications (17)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation application of U.S. patent application Ser. No. 09/334,877, filed Jun. 17, 1999, and is now abandoned, which is a reissue of U.S. patent application Ser. No. 08/521,709, filed Aug. 31, 1995, which is now U.S. Pat. No. 5,640,023, issued Jun. 17, 1997.
The present invention relates generally to integrated circuit memory devices, and more specifically to integrated circuit memory devices which employ thin-film transistor (TFT) technology.
Thin-film transistors (TFTs) are becoming the load devices of choice in many integrated circuit memory devices, particularly in static random access memory (SRAM) cells. TFTs are superior to standard polysilicon resistor load devices, in that TFTs have an inherently lower OFF current—an advantage which is particularly relevant in low—and zeropower SRAM applications which feature extended battery operation. In spite of this advantage, however, the bitline to supply (Vcc) leakage of TFTs designed and fabricated in state-of-the-art technology is still too significant to enable battery operation of high-density memory devices, such as SRAMs, over an extended period of time.
The most common approach taken to reduce this bitline to supply leakage has been to reduce the cross-sectional area of the TFT channel, such that the TFT channel is made as thin and as narrow as possible. To this end, technologies which are capable of depositing extremely thin polysilicon layers, having a thickness of approximately 100 Å for instance, have been developed. Unfortunately, the resultant polysilicon grain size of these layers is also very small. Alternately, the width of a TFT of a memory cell may be made much smaller than any other critical dimension (CD) in the circuit. Thus, there are currently available products which feature TFTs having channel widths of 0.3 to 0.4 μm wide while all other CDs are 0.5 μm or larger. As would be anticipated, this difference between the width dimension and other CDs of the memory device places considerable pressure on the photolithography aspect of manufacturing and thus makes manufacturing of a device using such geometries very difficult. Additionally, there are processes which fully enclose the TFT channel by the device gate. This results in process complications which do not render a viable manufacturing approach.
It would be advantageous in the art to minimize bitline to supply (Vcc) leakage of thin-film transistors (TFTs).
It would further be advantageous in the art to be able to reduce the cross-sectional area of a TFT channel in order to minimize bitline to supply (Vcc) leakage of a thin-film transistor (TFT).
Therefore, according to the present invention, the cross-sectional area of a thin-film transistor (TFT) is decreased in order to minimize bitline to supply leakage of the TFT. This is accomplished by utilizing a spacer etch process to manufacture a TFT having a very narrow and thin channel in a controllable manner. The spacer dimensions of the TFT may be adjusted by simply modifying the thicknesses of the poly gate and the channel poly. The channel thickness is limited by the thickness; of deposited channel polysilicon which may be as thin as approximately 300 Å to 500 Å, and the channel width of the TFT corresponds to the height of the spacer etched along the polysilicon gate of the device which may be as small as approximately 0.15 to 0.25 μm.
A first preferred embodiment of the present invention employs at least two polysilicon layers to effect a spacer etch process which allows the cross-sectional area of a transistor channel of a TFT to be minimized in a controllable manner, thereby reducing the bitline to voltage supply leakage of the TFT. The first preferred embodiment provides planarization as an option. A second preferred embodiment of the present invention also utilizes a spacer etch process by selective etching a poly spacer of a spacer-TFT load structure formed around a first poly gate layer in order to achieve the desired channel length. The second preferred embodiment offers the advantage of requiring just two polysilicon layers; planarization is not required.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:
The present invention utilizes a spacer etch process to make the transistor channel of the TFT both very narrow and thin in a controllable manner. The channel thickness is limited by the thickness of the deposited channel polysilicon which may be as small as approximately 300 to 500 Å, and the channel width corresponds to the height of the spacer etched along the polysilicon gate of the device. The height of the spacer may only be approximately 0.15 to 0.25 μm. These geometries possible with the present invention represent an improvement of more than two times the capabilities of the optical lithographic techniques used to manufacture standard products. The spacer dimensions of the TFT may be adjusted by simply modifying the thickness of the poly gate and the channel poly.
A first preferred embodiment of the present invention produces a TFT device having a channel that is both very narrow and thin, resulting in a small cross sectional area of the TFT channel such that bitline to supply leakage is dramatically reduced.
Prior to formation of the TFT, standard layer deposition and etching of contacts for an integrated circuit device well known in the art is performed. These standard process steps typically involve the formation of one or two polysilicon (poly) layers on top of a silicon substrate where the integrated circuit memory device will be formed. Following these standard steps, planarization of the device substrate 12, as shown in the TFT structure 10 of
Next, the TFT channel is developed. Referring to
The final TFT structure 10 of
An understanding of the first preferred embodiment of the present invention is further aided by comparing the cross-sectional view of a conventional TFT structure of
The process steps and structure of the first preferred embodiment of the present invention, represented in
Several standard process steps are first performed before the TFT spacer definition occurs. First, referring to
To reduce the poly resistance, a polycide layer is usually deposited on top or created by the salicide (self-aligned silicide) process. The gate polycide should be WSi2 (Tungsten Silicide) rather than TaSi2 (Tantalum Silicide) in order to avoid extrusions. The thickness of polycide may be about 1000 to 2000 Å. Polycide or salicide formation would be followed by an etching step. Following the formation of gate poly layer 36 of
Following the N-/P- implantation, nitride liner 38 is deposited over an end of the gate poly layer 36 and a portion of the isolation region 34 and subsequently patterned. Referring to
The bulk transistor formation now needs to be completed by N+ and P+ implants using the appropriate masks; again, P+ implantation occurs only in the periphery of the cell area and thus the masks are not shown on the drawings. N+ implant may be Arsenic followed by Phosphorous at dosages of 1-10e15 and 1-10e14, respectively, and energies of approximately 30-50 keV, such as is known in the art, depending on the design rules and the desired final electrical properties of the circuitry. P+ implant is BF2 or Boron at dosages of 1-10e15 and appropriate energies, such as 30 keV, again depending on the desired junction depth/drive current, etc. The mask layers corresponding to the process steps shown and described in conjunction with
Next, process steps necessary to form a polysilicon spacer for a TFT, according to the second preferred embodiment of the present invention, are performed. Referring to
In addition to utilizing only two poly layers rather than three poly layers and not requiring planarization, the second embodiment of the present invention offers other desirable features. The simultaneously salicided Vss and Vcc voltage supply lines of the second preferred embodiment allow for reduced series resistance. Additionally the TFT source (P+) connected to the pull-down gate (N+) through the TaSi or WSi layer ensures that there is no problematic N+/P+ parasitic junction.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
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|U.S. Classification||257/66, 257/67, 257/217, 257/69, 257/213|
|International Classification||H01L27/11, H01L21/336, H01L29/786, H01L21/8244, H01L29/76, H01L31/036|
|Cooperative Classification||H01L29/78696, H01L27/11, H01L27/1108|
|European Classification||H01L27/11, H01L29/786S, H01L27/11F2|