|Publication number||USRE41325 E1|
|Application number||US 12/363,461|
|Publication date||May 11, 2010|
|Filing date||Jan 30, 2009|
|Priority date||May 5, 2006|
|Also published as||DE602007012956D1, EP1852872A1, EP1852872B1, US7471588, US20070258313|
|Publication number||12363461, 363461, US RE41325 E1, US RE41325E1, US-E1-RE41325, USRE41325 E1, USRE41325E1|
|Inventors||Haiming Yu, Tony K. Ngai, Kok Heng Choe|
|Original Assignee||Altera Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (1), Referenced by (4), Classifications (13), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of provisional patent application No. 60/797,884, filed May 5, 2006, which is hereby incorporated by reference herein in its entirety.
This invention relates to dual port random-access-memory circuits, and more particularly, to dual port random-access memory circuits with clamping circuitry to limit maximum bit line voltage swings in read bit lines during concurrent read and write operations.
Dual port memory arrays are used in integrated circuits such as integrated circuit memories and programmable logic devices.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design (CAD) tools to design a custom logic circuit. These tools help the designer to implement the custom logic circuit using the resources available on a given programmable logic device. When the design process is complete, the CAD tools generate configuration data files. The configuration data is loaded into programmable logic devices to configure them to perform the desired custom logic function.
Programmable logic devices generally contain arrays of random-access memory (RAM). These memory arrays, which are sometimes referred to as embedded array blocks (EABs) are used to handle the storage needs of the circuitry on the device. During normal operation of a programmable logic device, the hardwired and programmable circuitry of the device performs read and write operations on the memory of the blocks. Memory arrays on a programmable logic device typically range in size from a few kilobits to about a megabit or more.
Integrated circuits such as programmable logic devices are often configured to implement memory-based circuits such as clock conversion first-in-first-out (FIFO) circuits. In a typical scenario, data is written into a FIFO using one clock signal and is read out of the FIFO using another clock signal.
Circuits such as FIFO circuits on programmable logic devices are implemented using dual port random-access-memory arrays. Dual port memory arrays are also used in application specific integrated circuits and stand-alone memory chips.
Dual port memory arrays have two independent ports, which can be used for read and write operations. On programmable logic device integrated circuits with dual port memory arrays, programmable logic circuitry and a dual port memory array can be configured to implement a FIFO. One of the dual port memory array's ports is used for write operations, while the other of the dual port memory array's ports is used for read operations.
Dual port memory arrays contain rows and columns of memory cells. Dual port memory array cells are accessed using word lines and bit lines. Because they are two ports associated with each cell, there are two sets of word lines and two sets of bit lines associated with each memory array.
Normal operation of a dual port memory can be disrupted if a write operation on one port occurs during a read operation on the other port.
One way to avoid this type of overlap between read and write operations involves using a common clock for both ports. When a common clock is used, read and write operations can be performed using distinct clock phases, thereby preventing undesirable overlap. However, certain applications such as clock conversion FIFO circuits involve two independent clocks. If it is desired to implement a FIFO circuit of this type, it is not possible to use a common clock for the two ports of the dual port memory array.
Another way to address the disruptions involved when read and write operations overlap involves extending the write clock period. When a longer write lock period is used, the memory cell is less likely to function improperly when a write operation overlaps a read operation.
However, the use of an enlarged write clock cycle slows circuit operation. Moreover, larger write clock cycles will not always ensure proper operation of a memory cell, particularly when the memory cell exhibits large variations due to changes in process, voltage, and temperature (so-called PVT variations). As device sizes and operating voltages become smaller with successive generations of semiconductor manufacturing technology, PVT variations become increasingly important and are expected to be responsible for a growing portion of memory array operational failures such as the disruptions that arise during concurrent read and write operations.
It would therefore be desirable to be able to avoid the deleterious effects of concurrent write and read operations in a dual port memory array without using enlarged write clock cycles.
In accordance with the present invention, dual port memory array circuitry is provided that has bit line voltage clamping circuitry. The dual port memory array circuitry may be used on an integrated circuit such as an application specific integrated circuit, a memory chip, or a programmable integrated circuit.
The dual port memory array circuitry has a dual port memory array formed of rows and columns of dual port memory cells. Each memory cell is formed from a pair of cross-coupled inverters. Two pairs of address transistors are associated with each memory cell. One pair of address transistors is used by one port and the other pair of address transistors is used by the other port.
The dual port memory array supports simultaneous read and write operations. For example, a write operation can be performed on one port while a read operation is being performed on the other port.
Bit lines and word lines are associated with the rows and columns of the dual port memory array. During read operations, a word line is asserted and data is read from cells in an associated column using sense amplifiers. The read operation tends to pull the bit voltages low. Because of the presence of the bit line voltage clamping circuitry, the minimum voltage to which a read line can be pulled is limited (e.g., to within 10-32% of a positive power supply voltage). During write operations, word lines are asserted and appropriate write drivers are used to drive write signals onto bit lines in the array. When a write operation is performed during a read operation, the write drivers must overcome the loads produced by the bit line capacitances and pulled-down voltages on the read bit lines. Because the voltage clamping circuitry prevents the bit line voltages on the read port from being pulled too low, write-during-read operations are successful, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.
The present invention relates to dual port memories. The dual port memory circuitry of the present invention may be used in any suitable integrated circuit. For example, the dual port memory circuitry may be used in an integrated circuit memory device or an application specific integrated circuit (ASIC). The dual port memory circuitry may also be used in a programmable logic device integrated circuit or a programmable integrated circuit of a type that is not traditionally referred to as a programmable logic device such as a digital signal processor containing programmable logic or a custom integrated circuit containing regions of programmable logic. The present invention will generally be described in the context of programmable logic device integrated circuits as an example.
An illustrative programmable logic device 10 in accordance with the present invention is shown in FIG. 1.
Programmable logic device 10 has input/output circuitry 12 for driving signals off of device 10 and for receiving signals from other devices via input/output pins 14. Interconnection resources 16 such as global and local vertical and horizontal conductive lines and busses may be used to route signals on device 10. Interconnection resources 16 include conductive lines and programmable connections between respective conductive lines and are therefore sometimes referred to as programmable interconnects 16.
Programmable logic device 10 contains programmable logic 18 and memory arrays 22.
Programmable logic 18 may include combinational and sequential logic circuitry. The programmable logic 18 may be configured to perform a custom logic function. The programmable interconnects 16 may be considered to be a type of programmable logic 18.
Programmable logic device 10 contains programmable memory elements 20. Memory elements 20 can be loaded with configuration data (also called programming data) using pins 14 and input/output circuitry 12. Once loaded, the memory elements each provide a corresponding static control output signal that controls the state of an associated logic component in programmable logic 18. Memory elements 20 may use any suitable volatile and/or non-volatile memory structures such as random-access-memory (RAM) cells, fuses, antifuses, programmable read-only-memory memory cells, mask-programmed and laser-programmed structures, etc. Because memory elements 20 are loaded with configuration data during programming, memory elements 20 are sometimes referred to as configuration memory.
Memory arrays 22 contain volatile memory elements such as random-access-memory (RAM) cells. The memory arrays 22 are used to store data signals during normal operation of device 10. The memory arrays 22 need not all be the same size. For example, small, medium, and large memory arrays 22 may be included on the same programmable logic device. There may, for example, be hundreds of small memory arrays each having a capacity of about 512 bits, two to nine large memory arrays each having a capacity of about half of a megabit, and an intermediate number of medium size memory arrays each having a capacity of about 4 kilobits to 8 kilobits. These are merely illustrative memory block sizes and quantities. In generally, there may be any suitable size and number of memory arrays 22 on device 10. There may also be any suitable number of regions of programmable logic 18.
During normal use in a system, memory elements 20 are generally loaded with configuration data from a configuration device integrated circuit via pins 14 and input/output circuitry 12. The outputs of the loaded memory elements 20 are applied to the gates of metal-oxide-semiconductor transistors in programmable logic 18 to turn certain transistors on or off and thereby configure the logic in programmable logic 18. Programmable logic circuit elements that may be controlled in this way include pass transistors, parts of multiplexers (e.g., multiplexers used for forming routing paths in programmable interconnects 16), look-up tables, logic arrays, AND, OR, NAND, and NOR logic gates, etc.
The circuitry of device 10 may be organized using any suitable architecture. As an example, the logic of programmable logic device 10 may be organized in a series of rows and columns of larger programmable logic regions each of which contains multiple smaller logic regions. The resources of device 10 such as programmable logic and memory 22 may be interconnected by programmable interconnects 16. Interconnects 16 generally include vertical and horizontal conductors. These conductors may include global conductive lines that span substantially all of device 10, fractional lines such as half-lines or quarter lines that span part of device 10, staggered lines of a particular length (e.g., sufficient to interconnect several logic areas), smaller local lines, or any other suitable interconnection resource arrangement. If desired, the logic of device 10 may be arranged in more levels or layers in which multiple large regions are interconnected to form still larger portions of logic. Still other device arrangements may use logic that is not arranged in rows and columns.
Memory 22 preferably includes at least some dual port memory. A dual port memory array 22 has two independent ports for writing and reading data. In a typical scenario, user logic that is implemented from a portion of programmable logic 18 generates data. The data is stored in a dual port memory array 22. Data is stored by writing the data into memory cells at a particular address within the memory array. The stored data can be accessed by performing a read operation. Because the memory array has two ports, one port may be used to perform read or write operations at the same time that the other port is being used to perform read or write operations. Separate clocks may be used for each port.
An illustrative dual port memory array 22 is shown in FIG. 2. Array 22 has a number of memory cells 24 in which data can be stored and from which data can be retrieved. The illustrative memory array 22 of
Array 22 has bit lines 26 and word lines 28. Bit lines 26 and word lines 28 are used to select which cells 24 are accessed. For example, if a particular word line 28 is asserted during a read operation, the data stored in the cells 24 that are connected to that word line will pass their stored data onto the bit lines 26. During a write operation, data that is to be written into array 22 is placed on bit lines 26 while an appropriate word line 28 is asserted.
Because the array 22 has two ports, there are two word lines 28 associated with each column of memory cells 24. The first word line in each column of cells 24 in
Memory array 22 may use a different bit line arrangement or a single bit line arrangement. In a single bit line arrangement, each row of the memory array 22 has two associated bit lines, one of which is used for the first port (port A) and the other of which is used for the second port (port B). The illustrative arrangement shown in
An illustrative memory cell 24 is shown in FIG. 3. Memory cell 24 has two cross-coupled inverters 34 and 40. Inverter 34 has p-channel metal-oxide-semiconductor (PMOS) transistor 36 and n-channel metal-oxide-semiconductor (NMOS) transistor 38. Inverter 40 has PMOS transistor 42 and NMOS transistor 44. The inverters 34 and 40 are powered with a positive power supply voltage Vcc supplied to terminals 30 (power supply source 30) and a ground power supply voltage Vss supplied to terminals 32. In a typical integrated circuit, Vcc may be 1.1 volts and Vss may be 0 volts. In general, any suitable values of Vcc and Vss may be used.
Memory cell 24 has four associated bit lines 26. During read operations through port A, data is read out of memory cell 24 over bit lines BITA and BITNA and is sensed using associated differential sense amplifier circuitry. During write operations through port A, data on bit lines BITA and BITNA is loaded into memory cell 24. Similarly, data is read out of memory cell 24 over bit lines BITB and BITNB during read operations through port B. During write operations through port B, data on bit lines BITB and BITNB is loaded into memory cell 24.
Memory cell 24 has four address transistors 46. One pair of address transistors 46 is controlled by the word line for port A (WLA) and is associated with port A. The other pair of address transistors 46 is controlled by the word line for port B (WLB) and is associated with port B. When WLA is asserted, the gates of the port A address transistors go high and the port A address transistors are turned on. With the port A transistors turned on, the bit lines BITA and BITNA are connected to nodes N1 and N2, respectively. When WLB is asserted, the gates of the port B address transistors go high and the port B address transistors are turned on. With the port B address transistors turned on, the bit lines BITB and BITNB are connected to nodes N1 and N2, respectively.
As shown in
During a read operation, the two address transistors associated with a given port are turned on, so that the contents of the cell may be sensed over a differential bit line 26. For example, during a read operation on port A, word line signal WLA is asserted, which turns on the port A address transistors, so that signals DATA and DATAN are conveyed to a differential sense amplifier over bit lines BITA and BITNA, respectively.
During a write operation, the two address transistors associated with a given port are also turned on using a word line. For example, during a write operation on port B, word line signal WLB is asserted, which turns on the port B address transistors. The data that is to be loaded into cell 24 is provided by a bit line driver over differential bit lines BITB and BITNB. When the bit lines BITB and BITNB are connected to nodes N1 and N2 by turning on the port B address transistors, the data on lines BITB and BITNB is driven into the memory cell 24. For example, if a logic one is being loaded into cell 24, node N1 will be driven high (e.g., Vcc) by a high signal on bit line BITB while node N2 is being driven low (e.g., Vss) by a low signal on complementary bit line BITNB.
It is often desired to operate the two ports of a dual port memory array asynchronously. In this type of situation, each port uses an independent clock. For example, a dual port memory array that is used as a clock conversion FIFO circuit uses a first clock (CLKA) for port A and uses a second clock (CLKB) for port B. Because there is no fixed rate and phase relationship between CLKA and CLKB, overlaps sometimes result between read and write events. In conventional dual port memory arrays, overlaps can lead to performance degradations and, in worse-case scenarios, can prevent an operation from being performed successfully.
As an example, consider a conventional dual port memory cell in which a write operation is initiated on port B during a read operation on port A. During the read operation on port A, a word line such as word line WLA of
A timing diagram that illustrates this worse-case write-during-read scenario for a conventional memory cell is shown in FIG. 4. In the example of
In the example of
At time t1, the clock signal CLKA, which serves as a read clock for port A, goes high. After a short delay due to address decoding and word line driver delays, the word line WLA goes high (time t2). This initiates the read operation for the cell. Both of the port A address transistors are turned on, so that the sense amplifier associated with the port A bit lines can sense the signals on nodes N1 and N2. Because node N1 is at Vcc, the state of bit line BITA remains high at time t2. Node N2 is at Vss. When its associated address transistor is turned on at time t2, the low voltage on node N2 pulls down the voltage on bit line BITNA from Vcc towards Vss. As shown in the third trace of
At time t3, the clock signal CLKB, which serves as a write clock for port B, goes low. Data write operations are triggered by the falling edge of the write clock, so that in situations in which a single clock is used (i.e., when CLKB enters CLKA), the write word line WLB will go high after the read operation is complete and the read word line WLA is low. This ensures that in a single-clock environment, a read will be executed before a write when both a read and write command are issued simultaneously.
After a short delay associated with address decoding and word line driver delays on port B, the write word line signal WLB goes high (time t4). The write word line pulse defined by WLB is generally much shorter than the read word line pulse defined by WLA. In the example of
When signal WLB goes high at the beginning of the write word line pulse, the port B address transistors are turned on and the port B write drivers attempt to drive a logic zero into the memory cell. As shown in the second-to-last trace of
There is a non-negligible capacitance associated with the bit lines such as the BITA and BITNA bit lines. When the port A address transistors are on (as is the situation during a read operation), this capacitance is connected to the nodes N1 and N2 and serves as a undesirable load on nodes N1 and N2. For example, when the address transistor associated with bit line BITNA is turned on, the bit line BITNA becomes electrically connected to node N2.
The presence of capacitive loading from the port A bit lines that are connected to nodes N1 and N2 during a read operation makes it difficult for conventional memory cells circuits to switch properly when the write word line is asserted. As shown in the last trace of
As shown in
A conventional technique for improving write performance during read operations involves lengthening the amount of time that the write word lines is asserted. When the write pulse length is enlarged sufficiently, there is enough time for the signals DATA and DATAN to switch to their desired values. This conventional approach for ensuring proper write-during-read performance is shown in FIG. 5. As shown in
Although it may be possible to ensure successful write-during-read operations using a lengthened write pulse as shown in
In accordance with the present invention, successful write-during-read operations are ensured by using clamping circuitry to limit the voltage pull-down effect on the bit lines during read operations. The clamping circuitry may, as an example, prevent read bit line voltages from dropping below about 25-32% of their high values during a read (e.g., to about 0.75 volts from 1.1 volts), rather than dropping to extremely low levels such as the 300 mV level described in connection with the conventional arrangement of FIG. 4. Because the read port bit line voltages and internal nodes of the memory cells fall to only moderately low voltages, the write bit line drivers can successfully overcome these voltages when needed during a concurrent write operation.
A dual port memory array circuit with bit line voltage clamping circuitry in accordance with the present invention is shown in FIG. 6. As shown in
During read operations, data is read from array 22 and is passed to input-output logic 52 via bit line read-write circuitry 54. Bit line read-write circuitry 54 contains sense amplifier and write driver circuitry 56. Differential sense amplifiers in bit line read-write circuitry 54 receives differential bit line signals from array 22 over respective pairs of bit lines 26. The outputs of the sense amplifiers are high or low digital signals that are provided to input-output logic 52. Sense amplifiers are typically responsive to voltage differentials on there inputs that are about 10% of Vcc. If a voltage difference greater than this amount develops across a pair of bit lines 26, the output of the sense amplifier will be either a valid high or low logic signal, depending on the polarity of the bit line signals.
Path 50 is used to pass the data that has been read from the array 22 to circuitry on the integrated circuit in which circuitry 48 is being used. For example, in a programmable logic device integrated circuit 10 of the type described in connection with
During write operations, data from user logic or other suitable circuitry is provided to input-output logic 52 over path 50. Input-output logic 52 passes the data to bit line read-write circuitry 54. Sense amplifier and write driver circuitry 56 contains write drivers that drive appropriate data signals into the array 22 over pairs of bit lines.
Dual port memory array circuit 48 has read-write control circuitry 60. Read-write control circuitry 60 generates a pair of read-write enable signals RWENA and RWENB. The read-write enable signals RWENA and RWENB are provided to bit line read-write circuitry 54 and address circuitry 62 over paths 70. The read-write enable signal RWENA is used to enable reading and writing on port A. The read-write enable signal RWENB is used to enable reading and writing on port B. With one suitable arrangement, the read-write enable signals are taken high when it is desired to enable writing and are taken low during read operations. As an example, when it is desired to write data into array 22 using port B while reading data from array 22 using port A, RWENA is a logic low (e.g., Vss) and RWENA is a logic high (e.g., Vcc).
Address circuitry 62 is used to control word lines 28. Address circuitry 62 has an address register 64, decoder 66, and word line drivers 68. Address register 64 is provided with address signals over path 71 (e.g., from user logic or other suitable circuitry on the integrated circuit in which dual port memory array circuit 48 is contained. The address signals that are provided to address register 64 are binary-encoded signals that define word line locations in array 22. The binary-encoded address signals in register 64 are decoded by decoder 66 so that individual columns of cells in array 22 may be addressed. Word line drivers 68 receive decoded address signals from decoder 66 and take associated word lines 28 high. As described in connection with
Bit line voltage clamping circuitry 58 prevents the voltages on bit lines 26 from becoming too low during read operations. Because the minimum bit line voltages that can be produced during a read operation are limited, the write drivers in sense amplifier and write driver circuitry 56 are able to overcome the low memory cell voltages and bit line capacitances that are present when a write operation is performed during a read operation. The use of clamping circuitry 58 avoids the need for increasing the length of the write pulses, which allows dual port memory array circuit 48 to operate more rapidly than would be possible using a conventional lengthened write pulse arrangement of the type described in connection with FIG. 5. Moreover, the use of clamping circuitry 58 ensures that array 22 will function properly when write-during-read operations are performed even if the performance of the memory cells has been adversely affected by PVT variations that would otherwise result in write failures during read operations.
Illustrative bit line voltage clamping circuitry 58 of the type that may be used in dual port memory array circuitry 48 is shown in FIG. 7. The clamping circuitry 58 that is shown in
As shown in
Clamping circuit 72 has PMOS transistors 76, 78, 80, and 82. Clamping circuit 74 has PMOS transistors 86, 88, 90, and 92. Transistors 78 and 80 in circuit 72 are controlled by the read-write enable signal RWENA on line 84. Transistors 88 and 90 in circuit 74 are controlled by the read-write enable signal RWENB on line 94. Lines 84 and 94 receive signals from the two lines in path 70 (FIG. 6). Transistors 78, 80, 88, and 90 serve as control transistors that can enable or disable the clamping functions of circuitry 58 as appropriate.
During write operations, read-write enable signals on lines 84 and 94 are high, which turns off control transistors 78, 80, 88, and 90 and disables the clamping circuits 72 and 74. During read operations, the read-write enable signals are low, which turns on control transistors 78, 80, 88, and 90 and enables the clamping circuits 72 and 74. Read-write enable signal RWENA and RWENB are generated independently by read-write control circuitry 60, so the clamping circuits on each port can be enabled and disabled independently. For example, when a write is being performed on port B while a read is being performed on port A, RWENA will be low to enable bit line voltage clamping on the port A bit lines, while RWENB will be high to disable voltage clamping on the port B bit lines.
Circuits 72 and 74 are connected to positive power supply voltage terminals 96. Each terminal 96 supplies a positive power supply voltage Vcc. The positive power supply voltage Vcc may have any suitable value. With one suitable arrangement, Vcc is 1.1 volts.
Transistors 76, 82, 86, and 92 serve as voltage regulator transistors. When clamping circuits 72 and 74 are enabled, transistors 76, 82, 86, and 92 are connected between positive power supply voltage Vcc and respective bit lines 26a, 26b, 26c, and 26d using a feedback arrangement. This ensures that the minimum voltage drop that can develop on the bits lines 26a, 26b, 26c, and 26d is limited to about Vcc-Vt, where Vt is the threshold voltage of transistors 76, 82, 86, and 92.
As shown in
If desired, the number of transistors that are used in implementing the bit line clamping circuitry 58 may be minimized by using a clamping circuit of the type shown in FIG. 8. As with the clamping circuitry 58 of
As shown in
Clamping circuit 72 has NMOS transistors 100 and 102. Clamping circuit 74 has NMOS transistors 104 and 106. Transistors 100 and 102 in circuit 72 are controlled by the complement of read-write enable signal RWENA (called NRWENA) on line 108. Transistors 104 and 106 in circuit 74 are controlled by complementary read-write enable signal NRWENB on line 110. Lines 108 and 110 receive these control signals from the two lines in path 70 (FIG. 6). Transistors 100, 102, 104, and 106 are activated when it is desired to electrically connect bit lines 26a, 26b, 26c, and 26d to positive power supply voltage source (terminal) 96 during clamping operations. Source 96 supplies a positive power supply voltage Vcc. The positive power supply voltage Vcc may have any suitable value. With one suitable arrangement, Vcc is 1.1 volts.
During write operations, the complementary read-write enable control signals on lines 108 and 110 are low, which turns off transistors 100, 102, 104, and 106 and deactivates clamping. During read operations, the complementary read-write enable control signals are high, which activates transistors 100, 102, 104, and 106 and enables clamping by circuits 72 and 74. Complementary read-write enable control signals NRWENA and NRWENB are generated independently by read-write control circuitry 60, so the clamping circuits on each port can be enabled and disabled independently. For example, when a write is being performed on port B while a read is being performed on port A, NRWENA will be high and NRWENB will be low. This activates transistors 100 and 102 and connects bit lines 26a and 26b to Vcc to clamp the voltage on the port A bit lines, while voltage clamping operations are disabled on the port B bit lines 26c and 26d.
During clamping, the gates of transistors 100 and 102 are held high (in this example). If the voltage on bit lines 26a or 26b were to fall sufficiently to turn transistors 100 and 102 on, the voltage on the bit lines would be pulled high by source 96. Transistors 100 and 102 (and transistors 104 and 106) have an associated threshold voltage Vt. If a clamped bit line voltage starts to drop below Vcc-Vt, the transistor gate-source voltage Vgs will start to exceed Vt, which will turn the appropriate transistor 100 or 102 on and pull the bit line voltage back towards Vcc. Accordingly, once enabled by appropriate control signals on lines 108 and 110, the transistors 100, 102, 104, and 106 serve as clamping transistors that prevent the voltage on the bit lines from dropping too low. This ensures that write operations that occur during read operations will be successful.
Dual-port random-access memory arrays such as array 22 of
The memory cell that is actively connected to the sense amplifier through the bit line multiplexing circuitry is exposed to the capacitance of the sense amplifier. This memory cell is said to be experiencing a “normal read.” Other memory cells are not actively connected to the sense amplifier because they are isolated by the bit line multiplexing circuitry. These inactive memory cells are not exposed to the capacitance of the sense amplifier. Memory cells in this condition are said to be experiencing a “phantom read.”
The cells involved in a phantom read operation experience less loading than the cells involved in normal read operations, so these cells are generally able to pull their associated bit lines to lower voltages than the cells involved in normal reads. As a result, cells involved in phantom read operations are more likely to experience write failures during read operations than cells involved in normal read operations. By using clamping circuitry such as the clamping circuitry described in connection with
The impact of the clamping circuitry 58 on the operation of a dual port memory array circuit 48 when performing write-during-read operations is shown in FIG. 9. In the example of
In the scenario depicted in
At time t1, the read clock signal CLKA goes high. The word line WLA goes high at time t2 after a short delay due to address decoding and word line driver delays. This initiates the read operation for the cell and turns on both of the port A address transistors. The sense amplifier associated with the port A bit lines can therefore sense the signals on nodes N1 and N2. Because node N1 is at Vcc, the state of bit line BITA remains high at time t2. Node N2 is at Vss. When its associated address transistor is turned on at time t2, the low voltage on node N2 pulls down the voltage on bit line BITNA from Vcc towards Vss. As shown in the third trace of
When the clamping circuit of
When the clamping circuit of
Prior to time t4, at time t3, the clock signal CLKB, which serves as a write clock for port B, goes low. Data write operations are preferably triggered by the falling edge of the write clock, so that in situations in which a single clock is used (i.e., when CLKB equals CLKA), the write word line WLB will go high after the read operation is complete and the read word line WLA is low. This ensures that the read will be executed before the write when both a read and write command are issue simultaneously in a single-clock environment.
In the example of
The higher voltage on bit line BITNA at time t5 of
The write operation is therefore successful at flipping the state of the memory cell so that a logic zero is stored instead of a logic one. In contrast, the attempt at writing the logic zero into the memory cell using the conventional arrangement of
The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.
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|U.S. Classification||365/230.05, 365/226|
|Cooperative Classification||G11C8/16, G11C8/18, G11C7/12, G11C7/04, G11C7/1075|
|European Classification||G11C8/16, G11C7/10T, G11C7/04, G11C8/18, G11C7/12|