|Publication number||USRE41336 E1|
|Application number||US 10/334,709|
|Publication date||May 18, 2010|
|Filing date||Jan 2, 2003|
|Priority date||Jan 31, 1995|
|Also published as||US5937274, USRE38072|
|Publication number||10334709, 334709, US RE41336 E1, US RE41336E1, US-E1-RE41336, USRE41336 E1, USRE41336E1|
|Inventors||Masahiko Kondow, Kazuhisa Uomi, Hitoshi Nakamura|
|Original Assignee||Opnext Japan, Inc|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Non-Patent Citations (11), Referenced by (1), Classifications (58)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a Divisional application of application Ser. No. 08/381,418, filed Jan. 31, 1995, now abandoned.
Notice: more than one Reissue application has been filed for the reissue of U.S. Pat. No. 5,937,274, granted Aug. 10, 1999. The Reissue applications are application Ser. No. 10/334,709, filed Jan. 2, 2003, and application Ser. No. 09/924,504, filed Aug. 9, 2001, now issued as RE 38,072, issued Apr. 8, 2003.
The semiconductor technology has advanced centering around silicon. The scale of integration has increased from transistor devices to IC (integrated circuit) and VLSI (very large scale integrated circuit), and the increase in scale of integration is expected to continue in the future. With an increase in scale of integration, however, it is feared that corresponding increases in the operation speed is limited by the delay of electric signal through wiring. As the counter-measure for this, optical interconnections are drawing attention, and the monolithic integration of silicon based electronic devices with III-V compound semiconductor optical devices is considered the important basic technique whereby to realize optical interconnections.
For use in forming the III-V compound semiconductor optical devices on a Si substrate, the following two methods are being studied. One is the so-called super-heteroepitaxial method for epitaxially growing a III-V compound semiconductor, such as a GaAs or InP, which differs in lattice constant from Si, on a Si substrate, and forming an optical semiconductor of an AlGaAs, InGaAs or other system formed on top of the grown III-V compound semiconductor. An example of this method is disclosed in “Gallium arsenide and other compound semiconductors on silicon” by S. F. Fang, K. Adomi, S. Iyer, H. Morkoc, and H. Zabel in J. Appl. Phys. 68(7), Oct. 1, 1990.
The other is a direct bonding method in which optical semiconductors are first grown on a GaAs or InP substrate and then bonded to a Si substrate, and then the GaAs or InP substrate is removed. Such direct bonding method is disclosed in “Semiconductor lasers on Si substrate using the technology of bonding by atomic rearrangement” by Y. H. Lo et al., Appl. Phys. lett. Vol. 62, pp 1038-1040, 1993.
Regarding the materials used to date for the III-V compound semiconductors, as written in H. C. Casey, Jr. and M. B. Panish, “Heterostructure Lasers—Part B”, Academic Press, New York, 1978, pp. 8-9, binary compound semiconductors made up of Al, Ga or In as a group III element and P, As or Sb as a group V element, and alloy semiconductors including those elements have long been used. With progress of the crystal growth techniques, N-containing alloy semiconductors have recently come to be formed, such as GaNP (J. N. Baillargeon, K. Y. Cheng, G. E. Holfer, P. J. Pearch, and K. C. Hsieh, Appl. Phys. Lett. Vol. 60 pp. 2540-2542, 1992) and GaNAs (M. Weyers, M. Sato and H. Ando, Jpn. J. Appl. Phys. Vol. 31, 1992, pp. L853-L855). This has widened the range of choice of materials. In addition, a case where the N-containing alloy semiconductors are grown epitaxially on Si substrates is disclosed in JP-A-1-211912. When an N-containing alloy semiconductor is actually applied to form a semiconductor device like a laser diode, it is necessary to design a multi-layer structure by calculating the band gap and the amount of lattice strain. Because the N-containing alloy semiconductors show a huge bowing occurring in the band gap owing to N's extremely high electro-negativity, which will be described later, such special consideration which is not needed for the conventional alloy semiconductors is required in designing the band gap of the multi-layer structure of the N-containing alloy semiconductors. However, in all the cases of the N-containing alloy semiconductors grown to date, only an epitaxial monolayer is grown on the substrate crystal and, therefore, there has never been a case where N-containing alloy semiconductors are deposited in a multi-structure and applied to form semiconductor devices.
Both in the super-heteroepitaxial method and the direct bonding method, the lattice constant of the materials constituting the optical semiconductor device differs greatly (more than 4%) from that of the Si substrate, so that there is a problem that a misfit dislocation occurs in the crystal near the interface between the Si substrate and the III-V compound semiconductor. Another problem is that due to the difference in thermal expansion coefficient between the Si substrate and the III-V compound semiconductor, the dislocations, which have been generated in the cooling process after a heating process in the epitaxial growth or the bonding, move and increase. As a result, there are problems regarding the characteristics and the device lifetime of the optical semiconductor device produced. Therefore, the monolithic integration of silicon based electronic devices with the III-V compound semiconductor optical devices has not been put into practical application.
An object of the present invention is to provide a semiconductor device of a multi-layer structure free of misfit dislocations, fabricated from a nitrogen-containing alloy semiconductor and also provide a method for manufacturing this semiconductor device.
Another object of the present invention is to provide an optical semiconductor device which can be manufactured by growing an III-V alloy semiconductor on a Si substrate.
A further object of the present invention is to monolithically integrate silicon based electronic devices and optical semiconductor devices fabricated of III-V alloy semiconductors on the substrate.
In the semiconductor device according to the present invention, a semiconductor device includes a plurality of semiconductor layers. The plurality of semiconductor layers include at least a layer of N-containing alloy semiconductor of AlaGabIn1-a-bNxPyAszSb1-x-y-z (0≦a≦1, 0≦b≦1, 0<x<1, 0≦y<1, 0≦z<1). In at least two semiconductor layers of the plurality of semiconductor layers, each semiconductor layer has the value of lattice strain thereof set at less than the critical strain at which misfit dislocations are generated at the interface between this semiconductor layer and a semiconductor layer adjacent thereto. In the manufacturing method of semiconductor devices according to the present invention, Al, Ga, In, N, P, and As are prepared as materials for semiconductor devices, and a plurality of semiconductor layers including a layer of the N-containing alloy semiconductor AlaGabIn1-a-bNxPyAszSb1-x-y-z (0≦a≦1, 0≦b≦1, 0<x 1, 0≦y<1, 0≦z<1) are grown epitaxially using nitrogen radical as nitrogen material in a vacuum of substantially 10−2 Torr or higher vacuum.
Still other objects and effects of the present invention will become apparent from the following detailed description of embodiments with reference to the accompanying drawings.
In embodiments of the present invention, the optical semiconductor device is manufactured such that the lattice strain of each semiconductor layer as a material for the optical semiconductor device is kept lower than the critical strain which causes a misfit dislocation, in the whole temperature range of the manufacturing process. When the total thickness of the strained layers exceeds the critical thickness, it is necessary to compensate the stress and use an N-containing alloy semiconductor of AlGaInNPAsSb to form the layer having tensile strain. The strained layer of AlGaInNPAsSb, as there is difficulty in its production, should preferably have a thickness of 2 nm or more, and the lattice mismatch should be less than ±4% in relation to the critical thickness. For example, in the case of GaN(x)As(1-x), the range of the alloy composition x of 0.02<x<0.36 is recommended.
Description will be made of the devices constituting an optoelectronic integrated circuit (OEIC) according to the present invention.
When a light emitting diode is a laser diode (LD), a strained layer of a direct transition type N-containing alloy semiconductor of AlGaInNPasSb is used for the active layer.. When the strained layers are to be grown to a total thickness larger than the critical thickness, the stress is offset by depositing a layer having a tensile strain on top of a layer having a compressive strain or depositing a layer having a compressive strain on top of a layer having a tensile strain. To improve the carrier injection efficiency, it is only necessary to place a guide layer made of Al(a)Ga(1-a)N(x)P(1-x) (0≦a≦1, 0≦x≦1), Si adjacent to the active layer. When the lasing wavelength is longer than the band gap of Si, the Si can be used as the material for the clad layer or guide layer. When a laser diode is of a surface emitting type, as shown in
When a light detector is a photodiode (PD), to reduce the band gap to expand the detecting wavelength range, an N-containing alloy semiconductor of AlGaInNPAsSb should be used as the material for the light absorbing layer. When the photodiode is an avalanche photodiode, a Si material having a large difference in ionization coefficient between electrons and holes can be used for the multiplication layer.
If an N-containing alloy semiconductor of AlGaInNPAsSb with a narrow band gap of 0.5 eV or less or with a nature of a semimetal is used for the electrode contact layer, a good quality ohmic electrode can be formed. It ought to be noted that the electrode contact layer of N-containing alloy semiconductor is used widely not only in optical devices but also in electronic devices. For the electrode contact layer, silicon is also used regardless of whether it is monocrystal or polycrystal. When the wavelength of light used with the optical semiconductor device is transparent to Si, the Si electrode functions as a transparent electrode.
The N-containing alloy semiconductor of AlGaInNPAsSb can be grown epitaxially to obtain a good-quality crystal without occurrence of misfit dislocations, by using nitrogen radical as the material for N content in a greater vacuum than 10−2 Torr. For the AlGaInNPAsSb semiconductor, C or Be is used as the p-type impurity and Si or Sn is used as the n-type impurity.
If the wavelength of light used with the optical semiconductor device in an optoelectronic integrated circuit is transparent to Si, an optical circuit can be formed using Si and can be formed in an Si substrate, too. The optical circuit can be fabricated in a layer structure, and when a signal is transmitted to multiple points like a clock signal, a light waveguide need not be formed in the layer structure.
The problem that dislocations are generated when the lattice constant of the material of the optical semiconductor differs greatly from that of Si can be solved by controlling the thickness of the semiconductor layers constituting the optical semiconductor device.
With the N-containing alloy semiconductors, owing to the extremely high electro-negativity of N, a huge bowing occurs in the band gap. To show an example, as the N content which is added to GaAs and GaP is increased, their band gaps gradually decrease and do not increase toward the GaN bandgap of 3.4 eV. This is different from the tendency of the band gaps of the conventional alloy semiconductors. A compound semiconductor of GaN0.19As0.81 lattice matched to Si has the band gap reduced to 0 and becomes a semimetal.
Let us consider the difference in thermal expansion coefficient between Si and III-V compound semiconductors. Since the thermal expansion coefficient of Si is 2.6×10−6/° C. and the thermal expansion coefficient of GaAs is 6.0×10−6/° C., if GaAs and Si are cooled from a high temperature process at 630° C. to a room temperature of 30° C., a thermal strain of 0.2% occurs. From
Illustrative embodiments of the semiconductor device according to the present invention will be described.
In this embodiment, an opto-electronic integrated circuit (OEIC) was formed by integrating 10,000 Si-based electronic devices such as MOS-FETs (metal-oxide-semiconductor field-effect transistors), 100 surface emitting diodes of III-V alloy semiconductors, and 100 PIN photodiodes of III-V alloy semiconductors on the same Si substrate.
The method for forming this OEIC will be described. Description will start with the method for forming the optical circuits. In
As a preparatory step prior to forming an electronic device, ions are implanted into the Si substrate in which a light waveguide has been formed. As shown in
Next, a group III-V optical semiconductor device is formed by selective layer growth. The surface emitting laser diode LD is 5 μm in diameter. In
The Si wafer on which the group III-V optical semiconductor devices have been formed are coated with an SiO2 oxide film for use under the gate electrode of the MOS-FET and also for protection of the surfaces of the group III-V optical semiconductor devices LD and PD. Then, the thus formed optical semiconductor devices and electronic devices are provided with metal interconnection circuits by multi-layer wiring using Al and SiO2.
Finally, to form mirrors M1 and M2 in the optical circuits, grooves 26 and 27 are cut, which is tilted 45° to the surface of the Si substrate, by a halogen-applied reactive ion beam, by which step the OEIC is completed. The grooves can be made in an easier direction of work whether from the top or bottom side of the substrate.
The operation principle of the OEIC will next be described. When a voltage VIN is applied to the gate electrode of the MOS-FET for driving the laser diode LD, a current is conducted into the surface emitting laser diode LD, and the laser diode LD oscillates. The laser beam is radiated into the substrate, then totally reflected by the 45° inclined mirror M1, and guided to the light waveguide 13. The guided laser beam is totally reflected again by the other mirror M2 and guided to the photodiode PD. The detected laser beam is converted by the photodiode PD into a current, and this current is converted by the resistor into a voltage, and this voltage is amplified by the MOS-FET, and finally a voltage Vout is output to the source electrode.
The layers constituting the laser diode LD and the avalanche photodiode APD were formed by growing crystals in a high vacuum of 1×10−5 Torr in an chemical beam epitaxial system. In growing Si layers, a polysilicon was used as the material, and Sb and B were used respectively to provide the n-type and p-type dopants. In growing the III-V semiconductor layers, ethyl-based organometallic compounds were used as group III materials, and phosphine and arsine were used as materials for P and As, and nitrogen was obtained by activating ammonia molecules by ECR plasma. Sn and Be were used to provide the n-type and p-type dopants. The crystal growth was performed at 400° C., and the stress compensated superlattice layer and the single-composition layers were all designed to be lattice matched to Si at 300° C. The Si wafers 30 and 31 on which the group III-V optical semiconductor devices have been formed are coated with a SiO2 film for protection of the surfaces of the group III-V optical semiconductor devices LD and APD and also for use under the gate electrode of the MOS-FET. Then, the optical semiconductor devices and electronic devices thus formed are provided with metal interconnection circuits by multi-layer wiring using Al and SiO2.
The operation principle of this OEIC will now be described. When a voltage Vin is applied to the gate electrode of the MOS-FET for driving the laser diode LD, a current is supplied into the surface emitted laser diode LD, and the laser oscillates. The laser beam is introduced into an optical fiber 40, and the introduced laser beam is guided into the avalanche photodiode APD. The detected laser beam is converted by the photodiode APD into a current, this current is converted by the resistor into a voltage, this voltage is amplified by the MOS-FET, and is finally output to the source electrode Vout.
In this embodiment, the photoemitter and the photodetector are formed on the separate substrate crystals, and are used for signal transmission between the IC chips, but like in Embodiment 1 described earlier, the photoemitter and the photodetector may be used for signal transmission within an IC chip by using a light waveguide or an optical fiber.
In this embodiment, an independent surface emitting laser diode is formed on a Si substrate. The sectional view of its structure is shown in FIG. 7. The diameter of the surface emitting laser diode is 10 μm. In
In this embodiment, an independent avalanche photodiode was formed on a Si substrate inclined 5 degrees from (100) to the direction of . A detection light is introduced from the rear side of the substrate crystal of this device.
With regard to the optical devices in the above embodiments, the fabrication of the laser diode, photodiode and light emitting diode has been described, but needless to say, the present invention can be applied to other optical semiconductor devices, such as an optical modulator. It is also needless to say that the present invention can be applied to electronic devices other than the MOS-FET, and that Si-ICs already in practical use can be applied. The materials in the present invention can be applied to electronic devices, such as transistors and so on. The optical devices in Embodiments 1 and 2 are integrated with electronic devices but, of course, the optical devices can operate as independent devices. In Embodiments 1 to 5, Si was used as the substrate crystal, but GaP and AlP having almost the same lattice constant as Si may be used. In the stress compensated strained superlattice layer, a wide variety of N-containing AlGaInNPAsSb other than GaNP and AlP may be used as the material for the component layers under compressive strain.
According to the present invention, III-V alloy semiconductors can be epitaxially grown on Si substrates without generating of misfit dislocations, so that it has become possible to provide semiconductor devices which can be monolithically integrated with Si based electronic devices and can apply this technique to OEIC.
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|11||Official Action dated January 14, 2003 issued in connection with Application No. JP-5-141750.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US20150180210 *||Dec 19, 2013||Jun 25, 2015||Taiwan Semiconductor Manufacturing Company Limited||Semiconductor arrangement and formation thereof|
|U.S. Classification||257/79, 257/E31.127, 438/46, 438/91, 257/186, 257/184, 257/189, 438/47, 438/45, 257/82|
|International Classification||H01S5/343, H01L33/30, H01L27/144, H01L31/0232, H01S5/02, H01L31/0304, H01S5/323, H01L33/00, H01L27/06, H01L21/20, H01L27/15, H01L21/00|
|Cooperative Classification||H01L27/15, H01L31/107, H01L33/30, H01L33/007, H01S5/32375, H01S5/32366, H01L21/0262, H01L27/0605, B82Y20/00, H01L21/02458, H01S5/3434, H01L21/02381, H01L21/02392, H01L31/03048, H01L21/02507, H01L27/1446, H01L31/125, H01S5/021, H01L21/02461, Y02E10/544, H01L21/02538|
|European Classification||B82Y20/00, H01L21/02K4B1B1, H01L21/02K4A1B2, H01L21/02K4B1B2, H01L31/12B, H01L21/02K4A1A3, H01L27/144R, H01L21/02K4E3C, H01L21/02K4B5L3A, H01L31/107, H01L21/02K4C1B, H01L31/0304E2, H01L33/00G3B2, H01L27/06C, H01L33/30|