|Publication number||USRE41355 E1|
|Application number||US 11/429,635|
|Publication date||May 25, 2010|
|Filing date||May 5, 2006|
|Priority date||Mar 17, 1999|
|Also published as||US6734093|
|Publication number||11429635, 429635, US RE41355 E1, US RE41355E1, US-E1-RE41355, USRE41355 E1, USRE41355E1|
|Inventors||Gregory D. Sabin, William J. Gross, Jung-Yueh Chang|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (20), Classifications (41), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention relates to the field of integrated circuit devices, and more specifically, to the design of a bonding pad structure for such devices.
2. Background Information
Integrated circuit chips (dice) are manufactured by fabricating a plurality of identical circuits on a semiconductor wafer, scribing the wafer between the circuits, and subsequently breaking apart the wafer into individual chips. The chips are then mounted on lead frames or substrates for packaging and wire bonded for chip external connections. The bonding wire connects the bonding pads on the chip with the lead frame. IC chips can be bonded using thermocompression or ultrasonic techniques. In thermocompression bonding, heat and pressure are applied to the pad and to the underlying substrate in order to achieve the bond. In ultrasonic bonding, sufficient energy is supplied by ultrasonic vibration to achieve the bond.
Active circuit elements, including transistors, resistors, capacitors, inductors, and the like, are generally located in the central portion of the semiconductor device, while bonding pads have been located around the periphery of the active region on the chip. Bonding pads are generally not located above the active circuits in order to protect the active circuit elements during bonding processes.
In many instances, it may be desirable to place active circuits beneath the bonding pads. For example, it may advantageous to place active circuits under bonding pads in order to decrease die area and to reduce parasitic resistance due to long interconnection wires between bonding pads and active regions. However, due to thermal and mechanical stresses occurring during the bonding process, the underlying circuits may become damaged. For example, as the wire and the die are heated during the process of connecting the wire to the bonding pad, the bonding wire is pressed onto the bonding pad. Additional energy may be supplied by ultrasonic vibration in order to form the bond. When pressure or vibration is exerted upon the bonding pad, the bonding pad can be perforated and the underlying circuits may crack which degrades device performance.
Therefore, what is needed is a method for fabricating a bonding pad structure which allows the placement of active circuits beneath a bonding pad, without damaging or otherwise affecting the performance of the active circuits, and a method that enables the manufacture of semiconductor devices with smaller die sizes.
A method for forming a bonding pad structure over an active circuit of an integrated circuit device is disclosed. A plurality of metal layers are deposited over the active circuit. The uppermost metal layer is patterned and etched to form an array of openings in the metal layer. A dielectric layer is deposited over the uppermost metal layer and over the array of openings in the metal layer. A bonding pad is formed over the dielectric layer.
Additional features and benefits of the present invention will become apparent from the detailed description, figures, and claims set forth below.
The present invention is illustrated by way of example and not limitation in the accompanying figures in which:
A method for placing active circuits beneath bonding pads of an IC device is disclosed. In the following description, numerous specific details are set forth such as specific materials, methods, etc., in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that these specific details may not be needed in order to practice the present invention. In other instances, well-known processing steps have not been described in detail in order to avoid unnecessarily obscuring the present invention.
The present invention is a method for forming a bonding pad structure for integrated circuit devices which allows active circuits to be placed under bonding pads of the device. The bonding pad of the present invention is able to protect the underlying active circuits from shear and compressive stresses occurring during bonding processes. Thus, the die area that would otherwise be reserved just for bonding pads can now be used for active circuits. Additionally, using the present invention, the bonding pads may not necessarily have to be located on the outer edge of the chip.
Next, dielectric layer 30 is etched to form vias 40. Vias 40 provide for electrical coupling between active circuits 10 and bonding pad 50. In one embodiment of the present invention, vias 40 are formed on the edges of bonding pad 50. Bonding pad 50 is formed by depositing a metal layer over dielectric layer 30 such that the active circuits 10 are placed as much as possible in the center of the bonding pad 50.
In one embodiment of the present invention, there are several metal layers deposited over active circuits 10. As illustrated in
It should be noted that any of a number of materials may be used to form both the metal layers and the bonding pad. For example, aluminum, aluminum alloys, copper, copper alloys, gold, gold alloys, polysilicon, silicon alloys, or any combination thereof may be used to form the bonding pad and the underlying metal layers.
The bonding pad structure protects the underlying active circuits during the process of attaching the bonding wire onto the bonding pad. The bonding pad is subjected to mechanical shock as the bonding tool brings down the wire and exerts pressure or vibration on the bonding pad. Additionally, the bonding pad is subjected to heat in order to achieve a good quality bond.
Slotting the metal layer 20 underlying the bonding pad allows the metal to expand while subjected to mechanical and thermal stresses. In one embodiment of the present invention, the metal layer is etched, as illustrated in
One additional advantage of the present invention is that it allows the formation of IC devices with smaller die areas. Typically, a square bonding pad has dimensions of 85 microns to 125 microns. Additionally, prior art IC design rules do not allow the placing of any circuit within 25 microns of a bonding pad. Thus, if the bonding pads are placed on top of active circuits, the bonding pads placement is no longer restricted to just the edges of the die. According to the present invention, the bonding pads can be placed anywhere on the die area. Such a process will reduce the die area by the amount of the combined surface area of each bonding pad and the amount of space required by the design rules.
It should be noted that the method of the present invention may be practiced using many types of active circuits. For example, transistors, resistors, etc., or any combination of active circuits may be placed under the bonding pad structure, according to the present invention.
In one embodiment of the present invention, the bonding pad is formed over electrostatic discharge (ESD) protection circuits. ESD protection circuits protect active devices from destructive static charge build-up due to various transient charge sources such as human or machine handling of the IC chip during processing, assembly, and installation of the chip. The ESD structure would be placed directly underneath the bonding pad structure and approximately in the center of the bond pad area.
Thus, the present invention provides a bonding pad structure for integrated circuit devices which protects the underlying circuits from shear and compressive stresses during bonding processes. The present invention accomplishes a reduction in the chip area and eliminates the parasitic resistance due to long interconnection wires between bonding pads and active regions. Although certain specific embodiments have been described, various modifications and changes to the disclosed embodiments will be apparent to one of ordinary skill in the art upon reading this disclosure. Therefore, it is to be understood that the specifications and drawings are merely illustrative of and not restrictive on the broad invention, and that this invention is not limited to the specific embodiments shown and described.
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|U.S. Classification||438/614, 257/773, 438/622, 257/E23.142, 257/737, 257/784, 438/613, 438/612, 257/E23.145, 438/617, 438/615, 257/758, 257/781, 257/786, 257/E23.019|
|International Classification||H01L23/485, H01L23/52, H01L23/48, H01L29/40, H01L21/44, H01L23/053, H01L21/4763|
|Cooperative Classification||H01L24/05, H01L2924/01033, H01L2924/01014, H01L2224/05624, H01L2224/0569, H01L2224/05647, H01L2924/19043, H01L2924/19042, H01L2924/01082, H01L2224/05644, H01L2924/01079, H01L2924/351, H01L2924/01013, H01L2924/01029, H01L2924/19041, H01L2924/14, H01L24/03|
|European Classification||H01L24/03, H01L24/05|
|Sep 21, 2011||FPAY||Fee payment|
Year of fee payment: 8
|Oct 28, 2015||FPAY||Fee payment|
Year of fee payment: 12