|Publication number||USRE41464 E1|
|Application number||US 10/000,944|
|Publication date||Jul 27, 2010|
|Priority date||Jan 31, 1996|
|Also published as||US5999981|
|Publication number||000944, 10000944, US RE41464 E1, US RE41464E1, US-E1-RE41464, USRE41464 E1, USRE41464E1|
|Inventors||Avigdor Willenz, David Shemla, Yosi Sholt|
|Original Assignee||Marvell Israel (M.I.S.L) Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (18), Classifications (14), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to switched Ethernet controller devices and more specifically to switched Ethernet controller devices for providing processor based intervention in the packet routing decision process.
Traditional Ethernet switching hub equipment operates by examining Ethernet header information to perform local switching functions. If it is determined that a frame is destined for a local port, the hub transfers the frame between the inbound port and the outbound port. Typically this transfer occurs between multiple switching Ethernet controller devices in hardware using a direct memory access transfer scheme, common in many computer designs. The disadvantage of using direct memory transfer to transfer Ethernet frames is that it precludes the provision of any upper OSI level processing such as Level 3 processing or routing. The OSI stack defines seven levels or layers that operate independently of one another. Each level or layer has a distinct task or function to perform. In the OSI model Level 1 is defined as the physical layer, Level 2 as the link layer, and Level 3 as the network level. Traditional Ethernet switching is performed at the Level 2 layer. However, in many situations it is desirable to be able to perform some Level 3 processing also (i.e. by a processing device other than the switching Ethernet controller device), using suitable hardware or software techniques. Using direct memory transfer techniques to transfer the frame from one port to another makes this possible.
Accordingly, it is an object of the present invention to provide a switched Ethernet controller device able to intervene in the packet routing decision mechanism.
It is another object of the present invention to provide a switched Ethernet controller device able to intervene in the packet routing decision mechanism for both multicast and unicast packets.
A switched Ethernet controller (SEC) device and associated method that provides processor based intervention in the packet routing decision process is disclosed. A suitably programmed processor in combination with the switched Ethernet controller device enables a user or network designer to exert control over the packet routing decision process. Thus, routing capabilities can be incorporated in a switching hub constructed using SEC devices of the present invention. Processes are disclosed for handling both multicast and unicast packets. For multicast packets, rather than perform conventional lookup operations to determine the destination device and corresponding port number, a method is disclosed whereby the multicast packet, received from a source device, is first sent to the processor. The processor, in turn, examines the Level 3 or network layer routing information in the payload of the Ethernet frame and determines the destination device and corresponding port to transfer the packet to. For unicast packets, a buffer request is first sent to the processor rather than being immediately sent to all ports. The processor, based on an examination of the Level 3 data contained in the payload of the Ethernet frame, either discards the packet, causes the packet to be transferred from the source device to the destination device or requests to receive the packet directly.
Thus, there is provided in accordance with a preferred embodiment of the present invention, a method of routing a multicast packet between a source port on a source device and a plurality of destination ports on a plurality of destination devices, utilizing a processor, the method including the steps of the source device receiving the multicast packet via the source port, the source device sending the multicast packet to the processor, the processor examining the multicast packet, the processor determining the plurality of destination devices and corresponding the plurality of destination ports based on the results obtained during the step of examining, the processor transferring the multicast packet to the plurality of destination devices, and the plurality of destination devices sending the multicast packet to the plurality of destination ports.
In accordance with a preferred embodiment of the present invention, the step of causing the source device to send the unicast packet to the destination device, includes the steps of the processor sending a second buffer request to the destination device, transferring the unicast packet from the source device to the destination device, and the destination device sending the unicast packet to the destination port. In addition, said step of transferring includes transferring the unicast packet utilizing direct memory transfer.
The step of receiving the unicast packet from the source device includes the steps of the processor sending a second buffer request message to the source device, and the source device sending the unicast packet to the processor.
The invention is herein described, by way of example only, with reference to the accompanying drawings, wherein:
A high level block diagram of an example switching hub built using switched Ethernet controller devices constructed in accordance with a preferred embodiment of the present invention is illustrated in FIG. 1. The switching hub, generally referenced 10, comprises a processor 12 coupled to memory 14. Processor 12 can be any suitable processor, such as a microprocessor or equivalent. Memory 14 can be any suitable memory device or devices, such as random access memory (RAM), either of the dynamic or static type. In the example illustrated in
The present invention provides the network with the ability to both transfer data directly between SEC devices and to enable the processor 12 to intervene in the switching operations. Such an intervention is typically software controlled such that the criteria regarding the decisions to be made can be changed overtime.
In a preferred embodiment, each SEC device is coupled to its own memory array. SEC 16 is coupled to RAM 18 and SEC 20 is coupled to RAM 22. External Ethernet devices are coupled to the Ethernet ports on the SEC devices. Ethernet port 30 is coupled to the external Ethernet device 34 and Ethernet port 32 is coupled to external Ethernet device 36. Both external Ethernet devices are coupled to their respective Ethernet ports through a wire connecting the two.
The manner of performing Ethernet switching between switches (i.e. non-intervention mode) will now be described, with reference to the high level flow diagram illustrated in FIG. 2. First, a packet is received over the wire from an external Ethernet device, in this example, Ethernet device 34. The packet is received by SEC device 16, designated as the source SEC device, for purposes of this example (step 40). Source SEC 16 stores the packet in RAM 18 (step 42). Source SEC 16 determines the destination SEC device and the appropriate port number within the SEC device to send the packet to (step 44). For the purposes of this example, SEC 20 is designated the destination SEC. Each SEC device maintains an address table within its associated memory with includes, among other things, the 48 bit media access control (MAC) address, device number and port number. Source SEC 16 looks up the destination address included in the received packet. If the destination address is found, source SEC 16 reads the corresponding device and port numbers from the table. As described in more detail in Applicant's co-pending application Ser. No. 08/790,151 entitled “A Bus Protocol” and filed on the same day herewith, the SECs transfer data therebetween in accordance with a “write-only” data transfer protocol. Other data transfer protocols are also incorporated in to the present invention.
In accordance with the write-only data transfer protocol, once source SEC 16 has determined where to send the data, it first writes a buffer request to destination SEC 20 (i.e. the SEC device found during step 44), requesting that the destination device prepare for a packet transfer (step 46). Destination SEC 20 then allocates a buffer for the packet to be received and writes a start of packet message to source SEC 16 with an indication of the location of the allocated buffer. A direct memory access (DMA) transfer then occurs directly between RAM 18 and RAM 22, thus transferring the packet to the allocated buffer in destination SEC 20 (step 48). Once the DMA transfer is complete, destination SEC 20 outputs the packet to the proper port (step 50). In this example, the packet is transferred between Ethernet port 32 and external Ethernet device 36 over the wire.
As discussed previously, it would be beneficial to network hardware and software application designers if it were possible to control the routing mechanism within a switching hub. Thus, a preferred embodiment of the present invention teaches a hardware/software intervention mechanism. The intervention mechanism allows a user or network designer to exert finer control over the packet routing decision process than is possible with just switch to switch transfers. To achieve an intervention function, processor 12 examines the Level 3 or network layer header information in the payload of the Ethernet frame. The intervention process is different for multicast packets and for unicast packets. The intervention process for multicast packets will be described first.
For multicast packets, a high level flow diagram of the process of intervening in the packet routing decision mechanism is illustrated in FIG. 3. Referring also to
For unicast packets, a high level flow diagram of the process of intervening in the packet routing decision mechanism is illustrated in FIG. 4. Referring also to
To discard a packet (step 86), processor 12 sends a start of packet message to the source SEC device 16 with the byte count field set to zero. If processor 12 decides to forward the packet to a destination device, it first sends a buffer request to destination SEC 20 device (step 90). In response to the buffer request, destination SEC device 20 allocates buffer space and sends a start of packet message to source SEC device 16. Source SEC device 16 performs a DMA transfer of the packet to destination SEC 20 (step 92). When the DMA transfer is complete, source SEC 16 sends an end of packet message to destination SEC 20. Subsequently, destination SEC 20 transfers the packet to the appropriate port (step 94).
If processor 12 decides to request the packet, it first sends a buffer request start of packet message to source SEC 16 with the target device, within the buffer request start of packet message, set to correspond to the processor itself (step 100). Source SEC 16 then sends the packet to processor 12 followed by an end of packet message (step 102).
Thus, for both multicast and unicast packets, the SEC provides a mechanism, for a device other than itself (i.e. processor 12), to intervene in and play a role in the packet routing process. Processor 12 can be suitably programmed by the user to tailor the decision process to a set of particular user defined requirements.
While the invention has been described with respect to limited number of embodiments, it will be appreciated that many variations, modifications and other applications of the invention may be made.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4947390 *||Mar 22, 1989||Aug 7, 1990||Hewlett-Packard Company||Method for data transfer through a bridge to a network requiring source route information|
|US5058109 *||Jun 28, 1989||Oct 15, 1991||Digital Equipment Corporation||Exclusionary network adapter apparatus and related method|
|US5130981 *||Dec 14, 1990||Jul 14, 1992||Hewlett-Packard Company||Three port random access memory in a network bridge|
|US5163131 *||Sep 8, 1989||Nov 10, 1992||Auspex Systems, Inc.||Parallel i/o network file server architecture|
|US5274631 *||Mar 11, 1991||Dec 28, 1993||Kalpana, Inc.||Computer network switching system|
|US5291481 *||Oct 4, 1991||Mar 1, 1994||At&T Bell Laboratories||Congestion control for high speed packet networks|
|US5521913 *||Sep 12, 1994||May 28, 1996||Amber Wave Systems, Inc.||Distributed processing ethernet switch with adaptive cut-through switching|
|US5598581 *||Aug 6, 1993||Jan 28, 1997||Cisco Sytems, Inc.||Variable latency cut through bridge for forwarding packets in response to user's manual adjustment of variable latency threshold point while the bridge is operating|
|US5632021 *||Oct 25, 1995||May 20, 1997||Cisco Systems Inc.||Computer system with cascaded peripheral component interconnect (PCI) buses|
|US5633865 *||Jul 29, 1996||May 27, 1997||Netvantage||Apparatus for selectively transferring data packets between local area networks|
|US5634138 *||Jun 7, 1995||May 27, 1997||Emulex Corporation||Burst broadcasting on a peripheral component interconnect bus|
|US5724529 *||Nov 22, 1995||Mar 3, 1998||Cirrus Logic, Inc.||Computer system with multiple PC card controllers and a method of controlling I/O transfers in the system|
|US5740175 *||Oct 3, 1995||Apr 14, 1998||National Semiconductor Corporation||Forwarding database cache for integrated switch controller|
|US5761431 *||Apr 12, 1996||Jun 2, 1998||Peak Audio, Inc.||Order persistent timer for controlling events at multiple processing stations|
|US5764996 *||Nov 27, 1995||Jun 9, 1998||Digital Equipment Corporation||Method and apparatus for optimizing PCI interrupt binding and associated latency in extended/bridged PCI busses|
|US5781549 *||Feb 23, 1996||Jul 14, 1998||Allied Telesyn International Corp.||Method and apparatus for switching data packets in a data network|
|US5784003 *||Mar 25, 1996||Jul 21, 1998||I-Cube, Inc.||Network switch with broadcast support|
|US5784373 *||Feb 20, 1996||Jul 21, 1998||Matsushita Electric Works, Ltd.||Switching device for LAN|
|U.S. Classification||709/238, 370/392, 370/401|
|International Classification||H04L12/18, H04L12/931, H04L12/937, H04L12/947, G06F15/173, H04L12/28|
|Cooperative Classification||H04L49/351, H04L49/201, H04L49/254, H04L49/25|
|May 1, 2003||AS||Assignment|
Free format text: CHANGE OF NAME;ASSIGNOR:GALILEO TECHNOLOGY LTD.;REEL/FRAME:014015/0846
Owner name: MARVELL SEMICONDUCTOR ISRAEL LTD., ISRAEL
Effective date: 20021215
|May 18, 2010||AS||Assignment|
Effective date: 20080414
Free format text: CHANGE OF NAME;ASSIGNOR:MARVELL SEMICONDUCTOR ISRAEL LTD.;REEL/FRAME:024399/0635
Owner name: MARVELL ISRAEL (M.I.S.L) LTD., ISRAEL
|Jun 7, 2011||FPAY||Fee payment|
Year of fee payment: 12