|Publication number||USRE41523 E1|
|Application number||US 11/441,465|
|Publication date||Aug 17, 2010|
|Filing date||May 25, 2006|
|Priority date||Jan 20, 2003|
|Also published as||US6741257|
|Publication number||11441465, 441465, US RE41523 E1, US RE41523E1, US-E1-RE41523, USRE41523 E1, USRE41523E1|
|Inventors||John Y. Retika|
|Original Assignee||Retika John Y|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (23), Classifications (24), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to graphics systems, and more particularly to addressing of programmable registers.
Personal computers (PCs) and other computer systems have a variety of controller integrated circuits (ICs) or chips that control subsystems such as for graphics, disks, and general system logic. Such controller chips are usually programmable. For example, the graphics controller can be programmed with the display resolution, such as the number of pixels in a horizontal line, or the number of lines on a screen. Memory-controller chips can be programmed with numbers of clock cycles for memory accesses, so that the timing signals generated by the controller chip can be adjusted for faster memory chips or faster bus clocks.
Advanced graphics systems often employ specialized engines, such as a bit-block-transfer BitBlt engine. Graphics data and commands can be written to a command first-in-first-out (FIFO) by a host processor, allowing the BitBlt engine to read and process graphics data and commands at its own pace.
The host microprocessor's address space is typically partitioned into memory and input/output (I/O) address spaces. While a large memory address space such as 4 GigaBytes (32 address bits) is provided, the I/O address space is typically much smaller, perhaps only 64 Kbytes (16 address bits). I/O addresses are used for accessing peripheral devices such as I/O ports, disk drives, modems, mouse and keyboard, and the controller chips. Often certain ranges of I/O addresses are reserved for certain types of peripherals, such as graphics, disks, and parallel ports. Thus the number of I/O addresses available to a peripheral controller chips is often limited.
Some of the programmable registers may be assigned addresses in the memory space rather than the I/O space. Since memory accesses are often faster than I/O accesses, memory-mapped registers can be accessed more quickly, improving performance. Frequently-accessed registers are often memory-mapped rather than I/O.
Bus 11 connects CPU 12 and graphics controller 10, and includes an address bus and a data bus. Bus 11 may be divided into separate sections by buffer chips. Often a high-speed bus such as a PCI (Peripheral Component Interconnect) or AGP (Accelerated Graphics Port) bus is used to connect to graphics controller 10.
Graphics controller 10 includes programmable registers 20 that control various features. For example, power-saving modes, display characteristics, timing, and shading can be controlled by CPU 12 writing to programmable registers 20. Registers are frequently written during 3D rendering or bitblt operations.
In the second bus cycle, the CPU writes a data value to the bus. The data written by the CPU is written through selector 34 to the register in programmable registers 20 that was selected by the address in decoder 31. The CPU may also read the selected register rather than write the selected register since selector 34 provides a bi-directional data path, depending on the read/write control signal from the CPU. For the PCI bus, address decoding takes 1, 2, or 3 clock cycles and data is written on the fourth clock cycle. A two-cycle idle time is necessary. Thus each PCI bus transaction requires 6 clock cycles.
The values written to programmable registers 20 are used to control features of the controller chip. For example, programmable registers 20 can output a number of pixels per horizontal line, and a number of lines in a screen, to counters 38 in a graphics controller. When the number of pixels written to the display matches the value of pixels/line from programmable registers 20, then a horizontal sync HSYNC pulse is generated. When the number of lines counted matches the total number of lines from programmable registers 20, then the vertical sync VSYNC is generated. Controls for windows within a screen can likewise come from programmable registers 20, such as for a movie window as described in Transparent Blocking of CRT Refresh Fetches During Video Overlay Using Dummy Fetches, U.S. Pat. No. 5,754,170 by Ranganathan et al., and assigned to NeoMagic Corp.
A second data value is written to a second programmable register during the third and fourth bus cycles. Address A2 is output during the third bus cycle while data D2 is output during the fourth bus cycle. The controller chip writes data D2 to the register identified by address A2. A third data value is written to another programmable register in the fifth and sixth bus cycles. Data D5 is written to the controller chip's register for address A5.
Each programmable register written requires a 2-bus-cycle access where the address is followed by the data. The programmable registers can be written in any order, but the correct address must precede the data value in each pair of bus cycles. Data may be read rather than written to the programmable registers by not asserting a write signal from the CPU.
High-speed busses often support higher data bandwidth using a burst access, ring a burst-access cycle, the address input in the first bus cycle is followed by several data values input over several bus cycles. A predefined burst order is used to determine the addresses of the data values in the burst sequence.
During the next 3 bus cycles, data values are received without addresses. The addresses of these three data values are implied by the burst rules. The burst rules define the address order during burst cycles. For purely sequential burst rules, the implied addresses of the next 3 data values are A1+1, A1+2, and A1+3. Often the burst addresses are interleaved so the addresses are somewhat mixed in order: A1+2, A1+1, then A1+3. The burst order is usually a fixed order defined by the architecture. Although a purely sequential burst is used as the example, other semi-sequential or interleaved burst orders may be substituted. The burst sequence is usually for sequential addresses (1,2,3,4), or semi-sequential addresses (1,3,2,4, or 1,4,2,3, or others) in some predefined sequence.
During the third bus cycle, burst decoder 33 causes selector 34 to route the second data value D2 to the next data register (A2) in programmable registers 20. Then in the fourth bus cycle, burst decoder 33 causes selector 34 to route the third data value D3 to the third data register (A3) in programmable registers 20. Finally, in the fifth bus cycle, burst decoder 33 causes selector 34 to route the fourth data value D4 to the fourth data register (A4) in programmable registers 20.
Only the starting address A1 was written to the controller chip. The other addresses A2, A3, A4, A5 were not sent across the bus from the CPU to the controller chip. These addresses are implied by the burst rules.
Since only one address is sent for four or more data values, more of the bus bandwidth is used for data transfers than for address transfers. This improves the efficiency of the bus, allowing data to be written to the controller chip more quickly. Higher performance results.
The data values burst in must exactly follow the burst sequence defined by the burst rules. Data cannot be written out of order without stopping the burst and inputting a new address.
Non-Sequential Register Access Using Command FIFO
For example, the first pair in command FIFO 21 is the pair or entries A1, D1. Data D1 is to be written to the register at address A1. In the example of
In the first and second bus cycles address A1 and data D1 are sent to the controller chip to program register A1 with data D1. A bus-idle period may follow as shown in this example.
Register A2 is programmed with data D2 in the next bus cycles, while register A4 is programmed with data D4 in other bus cycles. Finally register A6 is programmed with data D6 in the last bus cycles.
While command FIFO 21 improves efficiency of host-to-register transfers, a large FIFO may be required. Since a register address is stored with each data entry, two entries in command FIFO 21 are needed for each register programmed. One address could be shared over many register accesses using a burst access if all registers in a sequence were accessed, but often registers are not programmed in the sequential burst order. Sometimes only a relatively few registers are written. When even one register in the burst sequence is not written, then burst access may not be possible.
What is desired is more efficient use of a command FIFO to access programmable registers. It is desired to access programmable registers through a command FIFO without storing separate addresses for each register. It is desired to access registers that are not in a sequential burst-sequence order. It is desired to program only a subset of the registers in a sequence while still sharing register address entries in the command FIFO. A more efficient method to access non-sequential programmable registers is desired.
The present invention relates to an improvement in using a command FIFO to program registers. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
The inventor has realized that the memory efficiency of a command FIFO can be increased even when non-sequential programmable registers are programmed. When the first entry is for a special index register, the following data entries do not need their own address entries. The first data value sent in the sequence is an index that the controller chip or bitblt engine decodes to determine which registers to write. The controller chip then writes these registers with the remaining data values in the sequence stored in the command FIFO.
The software driver usually knows in advance which registers are going to be programmed, so a list of these registers is generated by the software driver. This list is translated to register fields in the index. Then the software driver writes to the command FIFO at the first address with the index, followed by the data values to written to the programmable registers.
In the third bus cycle, the CPU writes the data value D1. The data value D2 is written to the command FIFO in the fourth bus cycle, and in the fifth bus cycle, data value D4 is written to the FIFO. During the sixth bus cycle, data value D6 is written.
When the controller chip reads the command FIFO, it assumes that the first data value is the index for the special index register. The controller chip then reads the first data value and decodes it as the index.
The controller chip then routes the next D1 data to the A1 data register, since the index indicated that registers A1, A2, A4, and A6 will be programmed by the burst. The controller chip writes the D2 data to the A2 register. Data value D4 is written to the A4 register, while data value D6 is written to the A6 register in the controller chip.
A total of 6 bus cycles and 6 entries in the command FIFO are required for the non-sequential burst. In comparison with
After the last data value is read, the next entry in the command FIFO is another index. The process or decoding the mapping fields in this next index can be repeated to program additional registers. Read and write pointers can be kept. Once the read pointer reaches the write pointer, the controller chip has read all values from the command FIFO and can stop reading.
A total of eight mapping fields are contained in the index. Each mapping field can enable writing of one programmable register. Thus up to eight programmable registers can be written using one mapping index.
Each mapping field in the index is four bits wide. The four bits are decoded to indicate which register to access. For example, the four least-significant-bits (LSBs) are 0000 and are decoded to indicate access of register 0 (address A1 is 0). The next four LSB's are 0001 and are decoded to indicate access of register 1 (address A2 is 1).
Decoding other mapping fields for A3, A4, and A5 reveal that registers 4, 5, and C (hex) are to be accessed. Thus registers 0, 1, 4, 5, C are to be accessed.
When the four bits in a mapping field are all ones, the mapping field does not indicate access of any register. Instead, the register access is disabled. In this example, the last 3 mapping fields (the MSB's) are each 1111, indicating that the last 3 register accesses are disabled. Only five registers are accessed in this example.
In the example of
The registers are accessed in the order determined by the mapping fields. After the index is read, data values D0, D1, D4, D5, DC are sent to the programmable registers in the next 5 bus cycles. These data values are written to programmable registers 0, 1, 4, 5, C by the controller chip.
Once the first address is sent during the first bus cycle in a burst, the addresses of the other data values in the burst are irrelevant. The registers accessed by data written into the command FIFO are determined by the mapping fields in the index.
The mapping index is copied to index register 32. Selector 34 selects one of the mapping fields in index register 32 for decoding by decoder 36. For example, the LSB mapping field can be decoded first, then the next LSB field, etc.
Decoder 36 sends control signals to bus/switch 38, which selects the first data entry after the mapping index from entries 28. This first data entry is routed over internal buses to the selected register in programmable registers 30. The data entry can be routed to several or all registers and the individual register enabled by a control, select, write, or enable signal from decoder 36. One or more buses may be used.
As successive mapping fields from index register 32 are selected by selector 34, successive data entries in entries 28 are written to selected registers in programmable registers 30. For example, data D0 is written to register 0, data D1 is written to register 1, data D5 is written to register 5, and data DC is written to register C. Not all registers have to be written, and the order registers are written may be non-sequential. For example, register 5 could be written before register 1.
When the upper 28 bits of the index are not all ones, AND gate 71 examines the upper 24 bits. When these upper 24 bits are all ones, AND gate 71 outputs a one to priority encoder 80, which causes mux 82 to output 0x1, indicating that 2 registers are to be programmed.
AND gates 72-76 similarly examine smaller numbers of 4-bit mapping fields of the index. The first (most-significant) zero is thus encoded by priority encoder 80 and mux 82 to indicate the number of registers to be programmed. When all mapping fields contain a zero, then all 8 registers are to be programmed. Priority encoder 80 causes mux 82 to output 0x7 to indicate a data count of 8.
When the first entry is read from the command FIFO, the first entry contains the index. The first data entry is latched into index register 54 through mux/shifter 52. The lowest four bits of the index from index register 54 are extracted and decoded by decoder 56 to enable one of the 15 register-enable signals REG[E:0]13 EN. Thus the first mapping field is decoded to select the first register to be accessed. The next data entry read from the command FIFO is latched into data registers 58 and written to the selected register.
The mapping index is then shifted down by one mapping field. The mapping index from index register 54 is fed back to mux/shifter 52, which shifts the index down by four bits so that the second mapping field occupies the lowest four bits. These new lowest four bits are then decoded by decoder 56 to generate the next register-enable signal REG[E:0]_EN for the second mapping field. The next data entry read from the command FIFO is latched into data registers 58 and written to the selected register.
Mux/shifter 52 then shifts the index from index register 54 down by another four bits, allowing the third mapping field to be decoded by decoder 56. The third register is then written or read. This process of shifting the mapping index and accessing the register indicated by the shifted mapping field continues until all registers have been programmed. The end of programming can be detected by decoder 56 finding a mapping field containing all ones, or by the data count being reached by state machine 60.
Data registers 58 can be eliminated when no pipelining is used, or additional levels of pipeline registers can be used. Data registers 58 could be replaced with a data FIFO. The decoder and register-enables could also be pipelined.
Several other embodiments are contemplated by the inventor. For example, several different mapping index words may be used, each with a different starting address or different command FIFOs for a different bank of registers. The second mapping index word may refer to the next set of registers that are offset by an additional 15 registers or some other offset. When all mapping indexes in the first index are 0xF, then no registers in the first bank are programmed. Alternately, another bank field may be added to the index to indicate which bank is to be programmed. This bank field can be decoded to select one bank from among several banks. The bank field could be located in a programmable register rather than in the index, or some other means such as an I/O pin could be used to select banks. Byte, word, double-word, or other addressing may be used. Additional restrictions may be placed on the mapping index word, such as requiring that the disabled mapping fields be the MSB's or that at least one mapping field be enabled.
The address and the data may be input on separate busses rather than a shared bus, or on shared or separate signal lines. The address may arrive slightly before the data but with some overlap. Then a separate bus cycle may not be needed to latch the address.
Different register and addressing sizes can be used. The smallest addressable unit may be a byte, but some systems may address only 16-bit, 32-bit, or 64-bit words as the smallest writeable unit. The index register may be 32 bits, while the data register also 32 bits. A 64-bit read can also be used to read two data registers in one bus cycle. Sixteen-bit programmable registers are also possible as are other sizes.
Burst cycles could be used by the controller chip when reading the command FIFO, depending on the bus used between the FIFO and registers in the controller chip. The controller chip or bitblt engine can have logic to decode the mapping index and write or read the indicated registers, so addresses are not needed for each register access. The controller chip may be a graphics engine such as a BitBlt engine, a 2D or 3D graphics accelerator, an MPEG engine, or other kinds of engines.
Registers may be accessed by reading rather than writing using additional logic. The CPU has been described as using burst cycles to send data to the command FIFO. When the CPU does not use burst cycles to write the command FIFO, the CPU sends the index as the data with the first address, which is the address to the write pointer in the command FIFO. Then the CPU sends the first data value in another cycle, but increments the write pointer and writes to the following entry in the command FIFO. Subsequent writes are to subsequent address locations in the command FIFO.
The command FIFO may be a software buffer located anywhere in memory that is written by the host CPU and read by the controller chip. The read pointer address can be advanced by the controller chip while the write pointer addresses is advanced by the host CPU as each index and data value is written into the FIFO. Boundary addresses for the command FIFO can also be kept and referenced to determine when to wrap pointers around at the end of the buffer. The command FIFO could also be a hardware FIFO that uses hardware-based pointers or even shift registers. Then the host can write all index and data values to the same address, the address of the top of the FIFO.
The index register does not have to be the same width as the data registers. For example, a 32-bit index register with 4-bit mapping fields can be used to program up to eight of fifteen 64-bit data registers. A 64-bit index register can program up to 10 data registers in a bank of 63 registers using 6-bit mapping fields, and those data registers can be any size. Multiple index registers can be separately addressed, each controlling a different bank or set of data registers. The encoding of the index word may be varied with binary, gray-code, or other encodings that identify which of the programmable registers are to be written. The programmable registers could span several chips.
Many different I/O addresses can be used for the index and data registers. An indexing scheme may be used where the address is first written to an index or control register, then the data is written to a single data register and routed to the correct data register identified by the index. The mapping index word could point to non-consecutive data registers that are normally accessed by a 2-step indexing scheme, thus bypassing the index. The invention may be applied in a highly-integrated chip, such as a graphics controller integrated together with a systems-logic controller that includes the command FIFO.
The abstract of the disclosure is provided to comply with the rules requiring an abstract, which will allow a searcher to quickly ascertain the subject matter of the technical disclosure of any patent issued from this disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 C.F.R. § 1.72(b). Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC § 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claims elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word means are not intended to fall under 35 USC § 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
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|U.S. Classification||345/558, 712/E09.042, 712/E09.067, 345/559, 712/E09.024|
|International Classification||G06F3/14, G06F9/355, G06F9/38, G06F9/30, G09G5/36|
|Cooperative Classification||G06F9/30101, G09G5/363, G06F9/3879, G06F9/345, G06F9/355, G06F3/14, G06F9/30043|
|European Classification||G06F9/30A2L, G06F9/355, G06F9/38S1, G06F9/345, G09G5/36C, G06F9/30R2, G06F3/14|
|Nov 22, 2006||AS||Assignment|
Owner name: FAUST COMMUNICATIONS, LLC, NEVADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NEOMAGIC CORPORATION;REEL/FRAME:018639/0471
Effective date: 20050406
|Apr 20, 2010||AS||Assignment|
Owner name: NEOMAGIC CORP., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RETIKA, JOHN Y.;REEL/FRAME:024257/0914
Effective date: 20030312
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|Sep 21, 2015||AS||Assignment|
Owner name: XYLON LLC, NEVADA
Free format text: MERGER;ASSIGNOR:FAUST COMMUNICATIONS LLC;REEL/FRAME:036641/0051
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