|Publication number||USRE41559 E1|
|Application number||US 11/514,327|
|Publication date||Aug 24, 2010|
|Filing date||Aug 31, 2006|
|Priority date||Oct 10, 2001|
|Also published as||CN1311548C, CN1568541A, US6784540, US20030067071, WO2003032388A1|
|Publication number||11514327, 514327, US RE41559 E1, US RE41559E1, US-E1-RE41559, USRE41559 E1, USRE41559E1|
|Inventors||Charles S. Cardwell|
|Original Assignee||International Rectifier Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (72), Non-Patent Citations (3), Referenced by (4), Classifications (75), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit and priority of U.S. Provisional Application No. 60/328,362 filed Oct. 10, 2001 entitled SEMICONDUCTOR DEVICE PACKAGE WITH IMPROVED COOLING and which is incorporated herein by reference.
This invention relates to semiconductor device packages and more specifically relates to a novel semiconductor device package with a finned heat sink for improved cooling.
This invention relates to semiconductor devices and more specifically relates to a process for the low cost manufacture of a novel semiconductor device.
In prior art semiconductor devices, the housing area is frequently a large multiple of the area of the semiconductor die contained therein. Further, in many known semiconductor device, heat is taken out only from one side of the die, usually the bottom surface. In addition, the process for the manufacturing of prior art semiconductor devices is costly, specially when single device handling techniques are used.
In the presently known semiconductor die, particularly power MOSgated die, the top electrode (the source) is generally an aluminum contact containing about 1.0% silicon (hereafter an aluminum contact). The aluminum contact is used because it is well adapted to the wafer manufacturing process. However, it is difficult to form electrical connections to such aluminum contacts so a wire bond process is usually used in which a wire is ultrasonically bonded to the underlying aluminum contact. These wire-bond connections have a limited area and are thus a source of electrical resistance (RDSON) and of heat generation during operation. However, the bottom drain contact of a conventional MOSgated die is frequently a trimetal which is easily solderable or otherwise electrically connectable to a wide area contact surface without wire bonding as shown, for example, in U.S. Pat. No. 5,451,544. Thus, heat is primarily removed from the silicon die at the back contact surface, even though most heat is generated at the junction in the top surface and at the wire bonds. It would be desirable to remove heat from such a bottom drain in an improved manner.
It is known that solderable top contacts can be made to the top surface of a die, as shown in U.S. Pat. No. 5,047,833. However, the packages used for such solderable top contact structures have had very large “footprints” in comparison to the die area.
It would be desirable to produce a semiconductor device and a process for its manufacture which would occupy a smaller area on a circuit and would exhibit a lower RDSON than the known semiconductor devices.
It would be further desirable to produce such devices in a process which permits batch handling with reduced equipment on the production line and lower costs.
Devices are known in which the source side of a MOSgated device wafer is covered with a passivation layer, preferably a photosensitive liquid epoxy, or a silicon nitride layer, or the like. To form the passivation layer, the wafer is coated by spinning, screening, or otherwise depositing the liquid epoxy onto the wafer surface. The material is then dried and the coated wafer is exposed using standard photolithographic and masking techniques to form openings in the passivation layer to produce a plurality of spaced exposed surface areas of the underlying source metal and a similar opening to expose the underlying gate electrode of each die on the wafer. Thus, the passivation layer acts as a conventional passivation layer, but further acts as a plating resist (if required) and as a solder mask, designating and shaping the solder areas. The openings in the novel passivation layer can be made through to a conventional underlying solderable top metal such as a titanium/tungsten/nickel/silver metal. Alternatively, if the underlying metal is the more conventional aluminum metal the exposed aluminum can be plated with nickel and gold flash or other series of metals, resulting in a solderable surface, using the passivation as a plating resist. The tops of the plated metal segments are easily solderable, or otherwise contacted with low resistance, as compared to the high resistance connection of the usual wire bond to an aluminum electrode.
The source contact areas may have various geometries and can even constitute a single layer area region.
The wafer is then sawn or otherwise singulated into individual die. The individual die are then placed source-side down and a U-shaped, an L-shaped or a cup shaped, partially plated drain clip is connected to the solderable drain side of the die, using a conductive epoxy or solder, or the like to bond the drain clip to the bottom drain electrode of the die. The bottoms of the posts of the drain clip may be coplanar with the source-side surface (that is the tops of the contact projections) of the die, or the source-side surface may be offset inwardly with respect to the bottoms of the post to improve reliability. The outer surface of the die is then overmolded in a mold tray. A large number of die with such drain clips can be simultaneously molded in the mold tray.
The bonding material may be protected with a fillet of passivation material or by overmolding all, or a part of the assembly. The parts can be made in production by using a lead frame, a continuous strip, or by molding devices in a single block and singulating devices from that block.
After molding, the devices are tested and laser marked and are again sawn into individual devices.
Devices of this kind are shown in a copending application Ser. No. 09/819,774, filed Mar. 28, 2001 entitled CHIP SCALE SURFACE MOUNTED DEVICE AND PROCESS OF MANUFACTURE, the disclosure of which is incorporated herein by reference.
In accordance with the invention the bottom of a die, that is, the upward facing drain or other power contact of a semiconductor die, is at least thermally connected to a conductive heat sink with a finned structure. Such a structure is particularly useful in applications which employ forced air cooling such as servers, in which the heat sink may be several millimeters thick; or in lap top or other applications, in which the heat sink may have a thickness of only ½ millimeter. The heat sink may be connected to the die as by a conductive solder, or a conductive adhesive such as a silver filled epoxy. The heat sink itself may be made of any suitable conductive material such as aluminum or metal-matrix polymer/epoxy and can be extruded, formed or molded.
The present invention provides a novel package for semiconductor die of the kind having power or other electrodes on opposite surfaces of the die and makes it possible, with low cost manufacturing techniques, to make both electrodes available for surface mounting on a common support surface, for example the metallized pattern on a printed circuit board with improved cooling. While the invention is described with reference to a vertical conduction power MOSFET having the gate and source electrode on one surface and a drain electrode on the opposite surface, the invention is equally applicable to IGBTs, thyristors, diodes and the like of various topologies.
Thus, as will be seen, a novel die clip surrounds and contacts at least a portion of the back side electrode (a drain electrode in a MOSFET) and at least one post of the clip extends over an edge of the die and terminates in a plane which is coplanar with, but insulated from the front surface contacts (gate and source in a MOSFET) and the die clip acts as a good heat sink by virtue. The device may then be overmolded around the back and sides of the die and clip to present flat, coplanar solderable contact surfaces for all die electrodes to a mounting surface.
All top contact surfaces are formed, using a novel solder mask to form easily solderable contact surfaces on the die top surface, while the die are in the wafer stage. Drain clips are then attached to the die after die singulation and are overmolded in a batch molding process.
As will be later described, a plurality of easily solderable contact posts 36 are secured to (formed on) the source electrode 32 and a contact post 37 is secured to the gate electrode 33 as shown in
The pattern of contacts 36 can take different forms such as those shown in
In forming the package with die prepared as shown in
Clip 45 has a general “U-shape” with shallow posts 46 of a length slightly greater than the thickness of die 31 as measured from the surface 47 to the free surfaces of columns 36, 37, plus the thickness of an adhesive used to connect the drain to the plated interior surface 47 of the flat thin web 48 of the clip. For example, the clip may have a total thickness along the full length of posts 45 of 0.7 mm and a length from surface 47 to the free end of posts 46 of about 0.39 mm. The distance between the posts 46 depends on the size of the die, and a distance of 5.6 mm has been used for a size 4.6 die of International Rectifier Corporation, with a total width of about 1.5 mm for each of posts 46.
Mold lock openings 48 and 49 may also be formed in the clip 45 as shown in FIG. 10.
The solderable bottom drain electrode 34 of the die 30 is electrically connected to and secured to the plated interior of drain clip 45 as by a conductive adhesive 60 as shown in
In the embodiment shown, the structure is dimensioned so that the free surfaces of posts 46 (the drain connector) and posts 36 and 37 are coplanar. In a preferred embodiment, the source electrode of the die may be offset inwardly in relation to free surfaces of posts 46 in order to improve the reliability of the device.
Thereafter and as shown in
The top surface of solderable contact 40 is coplanar with drain clip projection surfaces 105. Thus, all of contacts 105, 40 and 27 will align with contact traces on a printed circuit board. The drain contacts may take any suitable form and could comprise a single contact or side, if desired.
As shown in
The wafer is then sawn to separate the die at lines 112 and 113 for example, and the die are singulated. The typical die 30 has the appearance shown in
The singulated die are then placed drain source-side down, into conductive clips which are plated on their interior with silver or some other conductive coating. The die is bonded to the clip, using conventional bond material such as a conductive epoxy as previously described. The clips/cans can be presented in the form of a lead frame and the devices can be later singulated from the lead frame.
According to the present invention, the clip 45 (or 80 or 100) can be modified to improve the dissipation of heat that is generated by the die 30. Referring to
Referring now to
The gate and source 32, 33 and drain 46 are separated within the die/board 210 bondline using a passivation process, similar to that used in the previously described manufacturing process.
A device according to the present invention is not restricted to clips having fins for dissipating the generated heat; other heat dissipating structures may be utilized. For example, as shown by
In order to improve the solderability of the clips to contacts on a circuit board, the clips may be coated with a material that can be easily soldered such as, for example, nickel, nickel-gold, nickel-palladium or silver. In addition, the clips according to the present invention may be coated with a highly emissive coating to improve heat dissipation by radiation.
Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention be limited not by the specific disclosure herein, but only by the appended claims.
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|U.S. Classification||257/706, 257/726, 257/713, 257/722, 257/702, 257/727, 257/718, 257/719, 257/E23.103, 257/707, 257/720, 257/E23.086, 257/E23.101, 257/E23.075, 257/705, 257/703, 257/711, 257/E23.051|
|International Classification||H01L23/367, H01L23/492, H01L23/373, H01L23/433, H01L23/34, H01L23/31, H01L23/10|
|Cooperative Classification||H01L2224/0401, H01L2924/12042, H01L2924/181, H01L2924/1305, H01L2924/1301, H01L2924/1306, H01L2224/32245, H01L23/492, H01L2924/3011, H01L24/32, H01L23/4334, H01L2924/01057, H01L23/3675, H01L2924/01006, H01L23/3114, H01L24/13, H01L2924/01029, H01L2924/167, H01L24/16, H01L2924/01047, H01L2924/16152, H01L2924/0105, H01L24/33, H01L2924/01082, H01L23/3185, H01L2924/01078, H01L2924/01033, H01L23/3733, H01L2924/01005, H01L2924/01023, H01L2924/01046, H01L24/29, H01L2924/13091, H01L2224/73253, H01L2924/01013, H01L24/05, H01L2924/13055, H01L2224/73153, H01L2924/01004, H01L2924/01074, H01L2224/29339, H01L2924/01079, H01L2924/12044, H01L2924/10253|
|European Classification||H01L24/32, H01L24/33, H01L23/433E, H01L23/31H1, H01L23/492, H01L23/367H|
|Feb 28, 2012||FPAY||Fee payment|
Year of fee payment: 8
|Feb 29, 2016||FPAY||Fee payment|
Year of fee payment: 12