|Publication number||USRE41561 E1|
|Application number||US 12/110,205|
|Publication date||Aug 24, 2010|
|Priority date||Jun 15, 2001|
|Also published as||US7038489, US20020194449|
|Publication number||110205, 12110205, US RE41561 E1, US RE41561E1, US-E1-RE41561, USRE41561 E1, USRE41561E1|
|Original Assignee||Ankur Bal|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Classifications (10), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to the field of electronic circuits, and, more particularly, to a system for reducing the number of programmable architecture elements in a look-up table for implementing Boolean functions or operations. In other words, the invention relates to sharing configuration data for higher logic density on a chip.
The present invention relates to programmable logic devices, particularly field programmable gate arrays (FPGAs). Lookup tables are highly configurable combinatorial logic devices. Their programming flexibility makes them desirable for use as basic building blocks in programmable logic devices (PLDs). Referring to
A particular data bit 1b is coupled to the look-up table output terminal 1c by decoding multiplexer circuitry 1 that is controlled by the lookup table input signals. The inputs 1b and outputs 1c of the look-up table usually connect to the routing resources of the CPLD/FPGA. In many cases, the output 1c is also coupled to a sequential element (flip-flop, latch, etc.). The inputs 1b and outputs 1c can, of course, be connected to other devices.
A generic look-up table is used to implement any function that can be bounded within the inputs and outputs of the LUT. Larger functions are broken down into smaller functions tailored to fit into the LUTs. The device routing resources connect these LUTs. Typically, in a circuit netlist mapped into LUTs, multiple LUTs are used to implement identical or similar functionality. An example of this would be an adder implementation in which the number of LUTs programmed to perform addition is directly proportional to the number of bits being added. It follows that a plurality of LUTs would be programmed with the same set of configuration bits. As will be discussed further below, numerous such scenarios exist.
An object of the invention is to provide a look-up table architecture that reduces the number of LUTs required to implement identical and/or logically equivalent functions.
The present invention therefore provides a system for reducing the number of programmable architecture elements in a look-up table that are required for implementing Boolean functions or operations that are identical or logically equivalent. More particularly, the system may include a single set of storage elements connected to inputs of multiple decoders, where the storage elements are concurrently accessed by the decoders to provide simultaneous multiple outputs.
A controlled inverter or XOR gate may also be inserted before the output of any of the decoders to increase the number of derivative functions. The controlled inverter may be either static or dynamic. Further, buffers may be introduced at the output of the storage elements of the look-up table for driving the inputs of the decoders when the number of decoders exceeds the driving capacity of the storage elements.
In addition, a programmable switch network may selectively connect the outputs of the storage elements of the look-up table to the inputs of the decoders. The connections may be made to any location in the device regardless of its distance from the storage elements of the look-up table SRAM or other suitable memory architecture may be used as the storage elements of the look-up table.
A method aspect of the invention is for reducing the number of programmable architecture elements in a look-up table that are required for implementing Boolean functions or operations which are identical or logically equivalent. The method may include connecting a single set of storage elements to the inputs of multiple decoders, and providing concurrent access to the storage elements by the decoders to generate simultaneous multiple outputs.
The method may further include performing controlled inversion of the output of any of the decoders to increase the number of derivative functions, where the controlled inversion may be either static or dynamic. The method may also include buffering the output of the storage elements of the look-up table for driving the inputs of the decoders when the number of decoders exceeds the driving capacity of the storage elements. Further, the outputs of the storage elements may be programmably connected to the inputs of the decoders.
The invention will now be described with reference to the accompanying drawings, in which:
Programmable look-up tables (LUTs) are the main logic resources of the CPLD/FPGA and are typically spread across the device. As noted above with respect to
Referring now to
As will be appreciated by those skilled in the art, designs including repetitive LUT bit patterns can be readily accommodated in the latch-multiplexer arrangement illustrated in FIG. 2. Most common designs with these patterns are adders, subtractors, multipliers and counters. In a circuit netlist, a similarity in the terms of logical equivalence exists among the many Boolean functions mapped into LUTs. Two or more Boolean functions are said to be logically equivalent if they can be implemented in look-up tables with identical configuration bits. Considering a four-input, single-output look-up table of the preferred embodiment, examples of logical equivalent functions include:
It should be noted that the functions will have the same set of configuration bits. The four-variable function is the parent function, and the rest are its derivatives or children. The children have lesser numbers of variables. Thus, some of the LUT pins will remain unused or will have to be pulled up/down while implementing the children functions. It might also be possible that the children functions have the same number of variables as their parent functions. Such children and many more functions can be derived from the parent function if one or more inputs to the multiplexer select lines are connected through controlled inverters. Still more are possible if the multiplexer's output is also invertible.
Turning now to
As will be appreciated by those skilled in the art, the lines conveying latch signals to the decoding multiplexers need not be optimized for delays if the CPLD/FPGA is not intended to be used as an extremely rapid reconfigurable device. Thus, in nearly all cases the latch data bus 4, which is sixteen bits wide here, may be minimum-width with minimum spacing and can follow any circuitous or meandering path to the decoding multiplexers. Therefore, routing the latches to the decoding multiplexers is not a critical design issue and may be given least priority while designing the device.
Another alternate embodiment of the invention is illustrated in FIG. 4. Here, the latch data busses 4 extend across the device. Programmable switches 4b are inserted to distribute and route the latch data buses 4 originating from various LUT SRAM latches 2. These latch data buses may be routed to nearby or remote regions of the device using a programmable bus routing network 4. The routing network 4 in no way introduces any extra delays in the final circuit implementation, as static logic data resides on these latch data lines. Thus, the latch data buses 4 can traverse long distances and use any number of programmable switches 4b and 4c without affecting circuit performance. As all the nets in a bus are being routed at a time, configuration latch count is also low.
It is, of course, possible to alter the multiplexer connectivity to the latch data bus and even include flexibility at the decoding multiplexer inputs 1a (sixteen here). Inputs to the multiplexer 1x delineate such possibilities. To include more flexibility, programmable switches 4c are inserted to couple latch data bus 4 to the multiplexer inputs 1a as desired.
The present invention thus provides a look-up table with a plurality of read ports capable of performing functions that are identical or logically equivalent with other variants. The area saved by using this approach is appreciable and without significant delay overhead. In conclusion, the concept of sharing SRAM latches of LUTs reduces the number of SRAM latches and improves chip density.
While exemplary embodiments of the present invention have been described above, it is possible to use various alternatives, modifications and equivalents thereof. For example, a memory architecture other than SRAM may be used as the configuration host. These embodiments and others that will be apparent to those of skill in the art in light of the above disclosure are intended to fall within the scope of the present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5352940||May 27, 1993||Oct 4, 1994||Altera Corporation||Ram convertible look-up table based macrocell for PLDs|
|US5889413||Nov 22, 1996||Mar 30, 1999||Xilinx, Inc.||Lookup tables which double as shift registers|
|US6181164||May 13, 1999||Jan 30, 2001||Xilinx, Inc.||Linear feedback shift register in a programmable gate array|
|US6388466||Apr 27, 2001||May 14, 2002||Xilinx, Inc.||FPGA logic element with variable-length shift register capability|
|US6523146||Nov 26, 1999||Feb 18, 2003||Matsushita Electric Industrial Co., Ltd.||Operation processing apparatus and operation processing method|
|U.S. Classification||326/41, 326/37, 326/39, 326/40, 326/38, 326/46|
|International Classification||H03K19/177, H01L25/00|
|Nov 30, 2010||CC||Certificate of correction|
|Apr 12, 2011||AS||Assignment|
Owner name: SICRONIC REMOTE KG, LLC, DELAWARE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:STMICROELECTRONICS, N.V.;REEL/FRAME:026111/0774
Effective date: 20071228
|Oct 11, 2013||FPAY||Fee payment|
Year of fee payment: 8
|Nov 2, 2015||AS||Assignment|
Owner name: MINERAL LASSEN LLC, NEVADA
Free format text: MERGER;ASSIGNOR:SICRONIC REMOTE KG, LLC;REEL/FRAME:036940/0693
Effective date: 20150811