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Publication numberUSRE41598 E1
Publication typeGrant
Application numberUS 11/108,886
Publication dateAug 31, 2010
Filing dateApr 19, 2005
Priority dateMar 13, 2001
Fee statusPaid
Also published asUS6552565, US20020171450
Publication number108886, 11108886, US RE41598 E1, US RE41598E1, US-E1-RE41598, USRE41598 E1, USRE41598E1
InventorsHorng-Der Chang, Chao-Cheng Lee
Original AssigneeRealtek Semiconductor Corp.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Impedance matching circuit
US RE41598 E1
Abstract
The present invention discloses an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission comprising: a first transistor, a second transistor, a resistor, a negative feedback control circuit, a multiplexer and a reference voltage generator. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.
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Claims(26)
1. An impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission, said impedance matching circuit comprises comprising:
a first transistor, including a power supply terminal, a control terminal and a load terminal, wherein said power supply terminal of said first transistor is connected to a voltage supply, and said load terminal of said first transistor is connected to an input terminal of said receiver;
a second transistor, including a power supply terminal, a control terminal and a load terminal, wherein said power supply terminal of said second transistor is connected to said voltage supply, and said control terminal of said second transistor is connected to said control terminal of said first transistor;
a resistor, wherein one terminal of said resistor is connected to said load terminal of said second transistor and the other terminal is connected to the ground; and
a negative feedback control circuit, wherein an inverting input terminal of said negative feedback control circuit receives an adjustable reference voltage, a non-inverting input terminal of said negative feedback control circuit is connected to said load terminal of said second transistor, and an output terminal of said negative feedback control circuit is connected to said control terminal of said second transistor;
wherein the equivalent resistance of said impedance matching circuit is kept equal to the resistance of the varied characteristic impedance of said cable by adjusting said reference voltage.
2. The impedance matching circuit as recited in claim 1, wherein said first transistor is a p-channel MOSFET.
3. The impedance matching circuit as recited in claim 1, wherein said second transistor is a p-channel MOSFET.
4. The impedance matching circuit as recited in claim 1, further comprising: a multiplexer, including a select terminal and a signal output terminal; wherein said multiplexer receives a plurality of voltage signals having different magnitudes, selects one from said plurality of voltage signals according to a select signal received by said select terminal, and then outputs said voltage signal as said reference voltage into said inverting input terminal of said negative feedback control circuit.
5. The impedance matching circuit as recited in claim 4, further comprising: a reference voltage generator for generating said voltage signals to be output to said multiplexer.
6. The impedance matching circuit as recited in claim 4, wherein said negative feedback control circuit is implemented by using one of an operational amplifier, a differential amplifier, and an inverter amplifier.
7. An impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission, said impedance matching circuit comprises comprising:
a first transistor, including a power supply terminal, a control terminal and a load terminal, wherein said power supply terminal of said first transistor is connected to an input terminal of said receiver, and said load terminal of said first transistor is connected to the ground;
a resistor, wherein one terminal of said resistor is connected to a voltage source;
a second transistor, including a power supply terminal, a control terminal and a load terminal, wherein said power supply terminal of said second transistor is connected to the other terminal of said resistor, and said control terminal of said second transistor is connected to said control terminal of said first transistor; and
a negative feedback control circuit, wherein an inverting input terminal of said negative feedback control circuit receives an adjustable reference voltage, a non-inverting input terminal of said negative feedback control circuit is connected to said power supply terminal of said second transistor, and an output terminal of said negative feedback control circuit is connected to said control terminal of said second transistor;
wherein the equivalent resistance of said impedance matching circuit is kept equal to the resistance of the varied characteristic impedance of said cable by adjusting said reference voltage.
8. The impedance matching circuit as recited in claim 7, wherein said first transistor is an n-channel MOSFET.
9. The impedance matching circuit as recited in claim 7, wherein said second transistor is an n-channel MOSFET.
10. The impedance matching circuit as recited in claim 7, further comprising: a multiplexer, including a select terminal and a signal output terminal; wherein said multiplexer receives a plurality of voltage signals having different magnitudes, selects one from said plurality of voltage signals according to a select signal received by said select terminal, and then outputs said voltage signal as said reference voltage into said inverting input terminal of said negative feedback control circuit.
11. The impedance matching circuit as recited in claim 10, further comprising: a reference voltage generator for generating said voltage signals to be output to said multiplexer.
12. The impedance matching circuit as recited in claim 7, wherein said negative feedback control circuit is implemented by using one of an operational amplifier, a differential amplifier, and an inverter amplifier.
13. An apparatus for impedance matching at the input terminal of a receiver, comprising:
a first controlled impedance unit utilized to provide an equivalent resistance of the input terminal according to a first control signal;
a resistor; and
an impedance control circuit, coupled to the first controlled impedance unit and to the resistor, utilized to receive an reference signal and generate the first control signal according to the reference signal and a resistance of the resistor;
wherein the reference signal is adjusted such that the equivalent resistance of the input terminal is adjusted.
14. The apparatus of claim 13, wherein the impedance control circuit comprises:
a second controlled impedance unit, coupled to the resistor, utilized for providing an equivalent resistance of the input terminal according to the first control signal;
wherein the first controlled impedance unit is corresponding to the second controlled impedance unit.
15. The apparatus of claim 14, wherein the impedance control circuit further comprises a feedback control unit which includes an inverting input terminal, a non-inverting input terminal, and an output terminal, wherein the inverting input terminal receives the reference signal, and the non-inverting input terminal is coupled to the resistor.
16. The apparatus of claim 14, wherein the impedance control circuit further comprises a feedback control unit which is implemented by using one of an operational amplifier, a differential amplifier, and an inverter amplifier.
17. The apparatus of claim 14, wherein the first controlled impedance unit is a first transistor.
18. The apparatus of claim 17, wherein the second controlled impedance unit is a second transistor.
19. The apparatus of claim 13, wherein the impedance control circuit comprises a second controlled impedance unit, and the first controlled impedance unit is corresponding to the second controlled impedance unit.
20. The apparatus of claim 21, wherein the reference signal is adjusted such that the equivalent resistance of the input terminal is adjusted.
21. An apparatus for impedance matching at the input terminal of a receiver, comprising:
a first controlled impedance unit utilized to provide an equivalent resistance of the input terminal according to a first control signal;
a resistor;
an impedance control circuit, coupled to the first controlled impedance unit and to the resistor, utilized to receive an reference signal and generate the first control signal according to the reference signal and a resistance of the resistor; and
a multiplexer, coupled to the impedance control circuit, utilized to receive a digital control signal and a plurality of reference signals, and output the reference signal according to the digital control signal.
22. A method for impedance matching in a receiver, comprising:
providing a controlled impedance unit;
generating a reference signal according to a digital control signal;
generating a control signal according to the reference signal and a resistance of a resistor;
providing an equivalent resistance of the controlled impedance unit according to the control signal; and
adjusting the equivalent resistance of the controlled impedance unit when the reference signal is adjusted.
23. A method for impedance matching in a receiver, comprising:
providing a controlled impedance unit;
generating a reference signal according to a digital control signal;
generating a control signal according to the reference signal and a resistance of a resistor; and
providing an equivalent resistance of the controlled impedance unit according to the control signal;
wherein the step of generating the reference signal comprises:
selecting one of a plurality of reference signals according to the digital control signal to generate the reference signal.
24. The method of claim 23, wherein the reference signal is adjusted such that the equivalent resistance of the controlled impedance unit is adjusted.
25. An apparatus for impedance matching at the input terminal of a receiver, comprising:
a first controlled impedance unit utilized to provide an equivalent resistance of the input terminal according to a first control signal; and
an impedance control circuit, coupled to the first controlled impedance unit, utilized to couple to a resistor, receive an reference signal and generate the first control signal according to the reference signal and a resistance of the resistor;
wherein the reference signal is adjusted such that the equivalent resistance of the input terminal is adjusted.
26. The apparatus of claim 26, further comprising:
a multiplexer, coupled to the impedance control circuit, utilized to receive a digital control signal and a plurality of reference signals, and output the reference signal according to the digital control signal.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission and, more particularly, to an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of the cable and the input impedance at the input terminal of a receiver for data transmission even when the characteristic impedance of the cable varies.

2. Description of the Prior Art

FIG. 1 is a schematic diagram showing a data transmission system. In FIG. 1, the data transmission system comprises two portions: a transceiver TX 10 and a receiver RX 12, where a cable 14 is interposed between the transceiver TX 10 and the receiver RX 12 for communication. In general, a cable has a characteristic impedance ZΦ. If the input impedance Zin, at the input terminal of the receiver RX 12 does not match the characteristic impedance Z101 of the cable 14, signal reflection may occur which may distort signals. Therefore, the input impedance Zin of the receiver RX 12 must be properly adjusted to match the characteristic impedance Z101 of the cable 14, so as to reduce signal reflection and prevent signals from distortion.

FIG. 2A to FIG. 2D are schematic diagrams showing various conventional impedance matching circuits in accordance with the prior art. In FIG. 2A, Z101 denotes the characteristic impedance of a cable 202, Zin denotes the input impedance 206 viewed at the input terminal of the receiver RX 208, and R101 denotes a stable resistor 204 interposed between the input terminal of the receiver RX 208 and a voltage source Vdd. Generally, the input impedance Zin 206 at the input terminal of the receiver RX 208 is relatively large. More particularly, the resistance of the input impedance Zin 206 is much larger than that of the stable resistor R101 204. Hence, the parallel connection of the stable resistor R101 204 and the input impedance Zin 206 results in a resistance value approximately equal to that of the stable resistor R101 204. When the resistance of the stable resistor R101 204 is determined to be equal to that of the characteristic impedance Z101 of the cable 202, impedance matching can be achieved.

In FIG. 2B, Z101 denotes the characteristic impedance of the cable 212, Zin denotes the input impedance 216 viewed at the input terminal of the receiver RX 218, and R101 denotes the stable resistor 214 interposed between the input terminal of the receiver RX 218 and the ground. Generally, the input impedance Zin 216 at the input terminal of the receiver RX 218 is relatively large. More particularly, the resistance of the input impedance Zin 216 is much larger than that of the stable resistor R101 214. Hence, the parallel connection of the stable resistor R101 214 and the input impedance Zin 216 results in a resistance value approximately equal to that of the stable resistor R101 214. When the resistance of the stable resistor R101 204 is determined to be equal to that of the characteristic impedance Z101 of the cable 212, impedance matching can be achieved.

In FIG. 2C, Z101 denotes the characteristic impedance of a cable 222, and Zin denotes the input impedance 226 viewed at the input terminal of the receiver RX 228. The input terminal of the receiver RX 228 is connected to the drain of a p-channel MOSFET (abbreviated as “PMOS” hereinafter) 224. The source of the PMOS 224 is connected to a voltage source Vdd, while the gate of the PMOS 224 is connected to the control terminal of a feedback control circuit 225. A precise resistor Rext 227 is interposed between the signal terminal of the feedback control circuit 225 and the voltage source Vdd. Reff denotes the equivalent resistance viewed at the drain of the PMOS 224, therefore the resistance of the precise resistor Rext 227 is expressed as Rext=αReff, where the value of α is controlled by the feedback control circuit 225. Generally, the input impedance Zin 226 at the input terminal of the receiver RX 228 is relatively large. More particularly, the resistance of the input impedance Zin 226 is much larger than the equivalent resistance Reff viewed at the drain of the PMOS 224. Hence, the parallel connection of the equivalent resistance Reff and the input impedance Zin 226 results in a resistance value approximately equal to the equivalent resistance Reff When the equivalent resistance Reff is determined to be equal to that of the characteristic impedance Z101 of the cable 222, impedance matching can be achieved.

In FIG. 2D, Z101 denotes the characteristic impedance of a cable 232, and Zin denotes the input impedance 236 viewed at the input terminal of the receiver RX 238. The input terminal of the receiver RX 238 is connected to the drain of an n-channel MOSFET (abbreviated as “NMOS” hereinafter) 234. The source of the NMOS 234 is connected to the ground, while the gate of the NMOS 234 is connected to the control terminal of a feedback control circuit 235. A precise resistor Rext 237 is interposed between the signal terminal of the feedback control circuit 235 and the ground. Reff denotes the equivalent resistance viewed at the drain of the NMOS 234, therefore the resistance of the precise resistor Rext 237 is expressed as Rext=βReff where the value of β is controlled by the feedback control circuit 235. Generally, the input impedance Zin 236 at the input terminal of the receiver RX 238 is relatively large. More particularly, the resistance of the input impedance Zin 236 is much larger than the equivalent resistance Reff viewed at the drain of the NMOS 234. Hence, the parallel connection of the equivalent resistance Reff and the input impedance Zin 236 results in a resistance value approximately equal to the equivalent resistance Reff. When the equivalent resistance Reff is determined to be equal to that of the characteristic impedance Z101 of the cable 232, impedance matching can be achieved.

From FIG. 2A to FIG. 2D, the stable resistor R101 and the precise resistor Rext have to change as the characteristic impedance Z101 of the cable varies. When there are a considerable number of cables, the number of the stable resistors increases as the number of cables increases, resulting in increased fabrication cost and complexity of the impedance matching circuit.

FIG. 3 is a schematic diagram showing another conventional impedance matching circuit in the prior art. In FIG. 3, Rcur denotes a built-in/external bias resistor 302 for providing the transistor mib 304 with the current Ibias. A current mirror circuit is composed of the transistor mdrz 306, the transistor mb7 308, the transistor mdlz 310, the transistor mdri 312, the transistor ma7 314, the transistor mdli 316 and the transistor mib 304. Since all the gates of the above transistors are connected together, the current in the current mirror is proportional to the bias current Ibias according to the W/L ratio of the transistors.

The gate voltage Vref of both the transistor muri 318 and the transistor mulz 320 is a reference voltage, the potential level of which is ΔV lower than that of the voltage source Vdd. The transistor muli 322, the transistor muri 318, the transistor mulz 320 and the transistor murz 324 are used for level-shifting, that is, making the gate voltage Vref of the transistors decrease to a voltage value approximately equal to the threshold voltage and then outputting an output voltage (i.e., as a source follower).

An operational amplifier with an output voltage Voa is composed of the transistor mal 326, the transistor ma2 328, the transistor ma3 330, the transistor ma4 332, and the transistor ma5 334. The gate voltage Vref is level-shifted by the transistor muri 318 and then applied to the gate of the transistor ma2 328 through the node ka2. For the output voltage Voa, a negative feedback circuit (where the capacitor mca 340 serves as a frequency compensation capacitor for stabilizing the operational amplifier) is formed of the transistor mna2 336, the transistor mna1 338, the gate voltage Vref, and the node ka1. Hence, the voltage at the node ka1 is equal to that at the node ka2, where the former is a voltage obtained by level shifting the voltage Vext and the latter is a voltage obtained by level shifting the voltage Vref Therefore, the voltage Vext is equal to voltage Vref.

Another operational amplifier with an output voltage Vob is composed of the transistor mb1 342, the transistor mb2 344, the transistor mb3 346, the transistor mb4 348, and the transistor mb5 350. The gate voltage Vref is level-shifted by the transistor mulz 320 and then applied to the gate of the transistor mb2 344 through the node kb2. For the output voltage Vob, a negative feedback circuit (where the capacitor mcb 354 serves as a frequency compensation capacitor for stabilizing the operational amplifier) is formed of the transistor mz0 352, the voltage Vxx, the transistor murz 324, and the node kb1. Hence, the voltage at the node kb1 is equal to that at the node kb2, where the former is a voltage obtained by level shifting the voltage Vxx and the latter is a voltage obtained by level shifting the voltage Vref. Therefore, the voltage Vxx is equal to voltage Vref.

The gate of the transistor mna2 336 is connected to the gate of the transistor mnb2 356. Therefore, the current flowing through the transistor mna2 336 is equal to the current flowing through the transistor mnb2 356, and the current flowing through the resistor Rext 358 is equal to the current flowing through the transistor mz0 352, which means that the resistance value of the resistor Rext 358 is equal to the equivalent resistance of the transistor mz0 352.

The circuit as shown in FIG. 3 is characterized in that Vext=Vref=Vxx and that the current flowing through the resistor Rext 358 is equal to the current flowing through the transistor mz0 352. Therefore, the equivalent resistance of the transistor mz0 352 can be regarded equal to the resistance value of the resistor Rext 358, even though it takes two operational amplifiers to meet the above conditions.

Let us assume that the width of the transistor mz0 352 is equal to Wp, the width of the transistor mlp1 360 is equal to 10Wp, the width of the transistor mlp2 362 is equal to Wp, the width of the transistor mnb2 356 is equal to Ws, the width of the transistor mnx 364 is equal to 11Ws and the gate of the transistor mnb2 356 is connected to the gate of the transistor mnx 364. As a result, the current flowing through the transistor mnx 364 is 11 times the current flowing through the transistor mnb2 356, and the current flowing through the transistor mlp1 360 is 10 times the current flowing through the transistor mz0 352. In addition, the current flowing through the transistor mlp2 362 is equal to the current flowing through the transistor mz0 352 (because the gate of the transistor mlp1 360, the gate of the transistor mlp2 362 and the gate of the transistor mz0 352 are connected). Therefore, the equivalent resistance viewed at the node datab towards the voltage source Vdd is one tenth of the equivalent resistance of the transistor mz0 352 and the equivalent resistance viewed towards the ground approaches infinity. Accordingly, the equivalent resistance at the node datab is equal to ( 1/10)*Rext//infinity=( 1/10)*Rext. (wherein the term “//” means parallel)

However, there are still some problems related to the prior art impedance matching circuit in that: (1) the resistance for impedance matching of the impedance matching circuit as well as the resistor Rext should change when the characteristic impedance of the cable varies; (2) two operational amplifiers are required to complete a negative feedback circuit so that the fabrication cost as well as the complexity may increase; and (3) the resistance value for impedance matching of the impedance matching circuit can not be changed by simply changing the voltage Vref of the impedance matching circuit.

SUMMARY OF THE INVENTION

Accordingly, it is the primary object of the present invention to provide an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission even when the characteristic impedance of the cable varies.

In order to achieve the foregoing objects, the present invention provides an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission. The impedance matching circuit comprises: a first transistor, a second transistor, a resistor and a negative feedback control circuit. The first transistor includes a power supply terminal, a control terminal and a load terminal, wherein the power supply terminal of the first transistor is connected to a voltage supply, and the load terminal of the first transistor is connected to an input terminal of the receiver. The second transistor includes a power supply terminal, a control terminal and a load terminal, wherein the power supply terminal of the second transistor is connected to a voltage supply, and the control terminal of the second transistor is connected to the control terminal of the first transistor. One terminal of the resistor is connected to the load terminal of the second transistor, while the other terminal is connected to the ground. An inverting input terminal of the negative feedback control circuit receives an adjustable reference voltage, a non-inverting input terminal of the negative feedback control circuit is connected to the load terminal of the second transistor, and an output terminal of the negative feedback control circuit is connected to the control terminal of the second transistor. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.

It is preferable that the negative feedback control circuit can be implemented by using one of an operational amplifier, a differential amplifier, and an inverter amplifier.

It is preferable that the impedance matching circuit further comprises: a multiplexer. The multiplexer includes a select terminal and a signal output terminal, wherein the multiplexer receives a plurality of voltage signals having different magnitudes, selects one from the plurality of voltage signals according to a select signal received by the select terminal, and then outputs the voltage signal as the reference voltage into the inverting input terminal of the negative feedback control circuit.

It is preferable that the negative feedback control circuit further comprises a reference voltage generator for generating the voltage signals to be output to the multiplexer.

It is preferable that the first transistor is a p-channel MOSFET and the second transistor is a p-channel MOSFET.

In order to achieve the foregoing objects, the present invention provides an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission. The impedance matching circuit comprises: a first transistor, a second transistor, a resistor and a negative feedback control circuit. The first transistor includes a power supply terminal, a control terminal and a load terminal, wherein the power supply terminal of the first transistor is connected to an input terminal of the receiver, and the load terminal of the first transistor is connected to the ground. One terminal of the resistor is connected to a voltage source. The second transistor includes a power supply terminal, a control terminal and a load terminal, wherein the power supply terminal of the second transistor is connected to another terminal of the resistor, the control terminal of the second transistor is connected to the control terminal of the first transistor, and the load terminal of the second transistor is connected to the ground. An inverting input terminal of the negative feedback control circuit receives an adjustable reference voltage, a non-inverting input terminal of the negative feedback control circuit is connected to the power supply terminal of the second transistor, and an output terminal of the negative feedback control circuit is connected to the control terminal of the second transistor. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.

It is preferable that the negative feedback control circuit can be implemented by using one of an operational amplifier, a differential amplifier, and an inverter amplifier.

It is preferable that the impedance matching circuit further comprises: a multiplexer. The multiplexer includes a select terminal and a signal output terminal, wherein the multiplexer receives a plurality of voltage signals having different magnitudes, selects one from the plurality of voltage signals according to a select signal received by the select terminal, and then outputs the voltage signal as the reference voltage into the inverting input terminal of the negative feedback control circuit.

It is preferable that the negative feedback control circuit further comprises a reference voltage generator for generating the voltage signals to be output to the multiplexer.

It is preferable that the first transistor is an n-channel MOSFET and the second transistor is an n-channel MOSFET.

Other and further features, advantages and benefits of the invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings are incorporated in and constitute a part of this application and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, spirits and advantages of the preferred embodiments of the present invention will be readily understood by the accompanying drawings and detailed descriptions, wherein:

FIG. 1 is a schematic diagram showing a data transmission system;

FIG. 2A to FIG. 2D are schematic diagrams showing various conventional impedance matching circuits in accordance with the prior art;

FIG. 3 is a schematic diagram showing another conventional impedance matching circuit in the prior art;

FIG. 4 is a schematic diagram showing an impedance matching circuit in accordance with one embodiment of the present invention; and

FIG. 5 is a schematic diagram showing an impedance matching circuit in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention providing an impedance matching circuit can be exemplified by the preferred embodiments as described hereinafter.

Embodiment I

Please refer to FIG. 4, which is a schematic diagram showing an impedance matching circuit in accordance with one embodiment of the present invention. In FIG. 4, an impedance matching circuit 400 with adjustable resistance is used for facilitating impedance matching between the characteristic impedance of a cable 402 and the input impedance at the input terminal of a receiver 404 for data transmission. The impedance matching circuit 400 is described hereinafter.

The source of the p-channel MOSFET (abbreviated as “PMOS” hereinafter) 406 is connected to the voltage source Vdd and the drain of the PMOS 406 is connected to an input terminal of the receiver 404. The source of the PMOS 408 is connected to the voltage source Vdd and the gate of the PMOS 408 is connected to the gate of the PMOS 406. One terminal of the resistor Rext 410 is connected to the drain of the PMOS 408 and the other terminal of the resistor Rext 410 is connected to the ground. The inverting input terminal of the operational amplifier 412 receives a reference voltage Vref, the non-inverting input terminal of the operational amplifier 412 is connected to the drain of the PMOS 408, and the output terminal of the operational amplifier 412 is connected to the gate of the PMOS 408. The select terminal of the multiplexer 414 receives a select signal SEL, and the signal output terminal outputs the reference voltage Vref to the inverting input terminal of the operational amplifier 412. Moreover, The reference voltage generator 416 includes a plurality of voltage output terminals for outputting the reference voltage Vref to the signal input terminal of the multiplexer 414.

In FIG. 4, the reference voltage at the inverting input terminal of the operational amplifier 412 is expressed as Vref=αVdd, where 0<α≦1. A negative feedback circuit is formed of the PMOS 406, the PMOS 408, and the resistor Rext 410. According to the virtual short circuit theory, we obtain Vref=αVdd=Vext, where Vext is the voltage across the drain of the PMOS 408 and the resistor Rext 410. Assuming that the equivalent resistance viewed at the drain of the PMOS 408 is Req, we obtain the voltage V ext = R ext R ext + R eq V dd .
That is α = R ext R ext + R eq
and the equivalent resistance R eq = 1 - α α R ext .

Let us assume that the aspect ratio of the PMOS 406 is ( W L ) P1 ,
the aspect ratio of the PMOS 408 is ( W L ) P2 ,
and the ratio between ( W L ) P1
and ( W L ) P2
is x, then ( W L ) P1 = x ( W L ) P2 .
Let us assume that R101 denotes the equivalent resistance viewed at the drain of the PMOS 406, where R Φ = 1 μ P C ox ( W L ) P1 ( V sg1 - V tP ) R eq = 1 μ P C ox ( W L ) P2 ( V sg2 - V tP ) V sg1 = V sg2 R Φ = 1 x R eq R Φ = 1 x 1 - α α R ext
where, μp is the carrier mobility, Cox is the electric capacitance per unit area at the gate, Vsg1 and Vsg2 are the voltage drops across the source and the gate, and |Vtp| is the threshold voltage.

Therefore, when the input impedance Zin 418 at the input terminal of the receiver 404 is relatively large, the parallel connection of the equivalent resistance R101 of the impedance matching circuit 400 and the input impedance Zin 418 results in a resistance value approximately equal to equivalent resistance R101 of the impedance matching circuit 400. When the resistance of equivalent resistance R101 of the impedance matching circuit 400 is determined to be equal to that of the characteristic impedance Z101 of the cable 402, impedance matching can be achieved.

When the characteristic impedance Z101 of the cable 402 varies, the multiplexer 414 of the impedance matching circuit 400 outputs a reference voltage Vref with a different magnitude to the inverting input terminal of the operational amplifier 412. As the Vref at the inverting input terminal of the operational amplifier 412 is adjusted, the value of α as well as the value of Req is also adjusted. Accordingly, the value of the equivalent resistance R101 is adjusted to match the varied characteristic impedance Z101 of the cable 402. Therefore, when the characteristic impedance Z101 of the cable 402 varies, the multiplexer 414 selects a suitable reference voltage Vref from the reference voltage generator 416 to change the equivalent resistance R101 of the impedance matching circuit 400 such that the equivalent resistance R101 is equal to the resistance value of the characteristic impedance Z101 of the cable 402. Therefore, impedance matching is achieved.

Embodiment II

FIG. 5 is a schematic diagram showing an impedance matching circuit in accordance with another embodiment of the present invention. In FIG. 5, an impedance matching circuit 500 with adjustable resistance is used for facilitating impedance matching between the characteristic impedance of a cable 502 and the input impedance at the input terminal of a receiver 504 for data transmission. The impedance matching circuit 500 is described hereinafter.

The source of the n-channel MOSFET (abbreviated as “NMOS” hereinafter) 506 is connected to the ground and the drain of the NMOS 506 is connected to an input terminal of the receiver 504. The source of the NMOS 508 is connected to the ground and the gate of the NMOS 508 is connected to the gate of the NMOS 506. One terminal of the resistor Rext 510 is connected to the drain of the NMOS 508 and the other terminal of the resistor Rext 510 is connected to the voltage source Vdd. The inverting input terminal of the operational amplifier 512 receives a reference voltage Vref the non-inverting input terminal of the operational amplifier 512 is connected to the drain of the NMOS 508, and the output terminal of the operational amplifier 512 is connected to the gate of the NMOS 508. The select terminal of the multiplexer 514 receives a select signal SEL, and the signal output terminal outputs the reference voltage Vref to the inverting input terminal of the operational amplifier 512. Moreover, The reference voltage generator 516 includes a plurality of voltage output terminals for outputting the reference voltage Vref to the signal input terminal of the multiplexer 514.

In FIG. 5, the reference voltage at the inverting input terminal of the operational amplifier 512 is expressed as Vref=βVdd, where 0<β≦1. A negative feedback circuit is formed of the NMOS 506, the NMOS 508, and the resistor Rext 510. According to the virtual short circuit theory, we obtain Vref=βVdd=Vext, where Vext is the voltage across the drain of the NMOS 508 and the resistor Rext 510. Assuming that the equivalent resistance viewed at the drain of the NMOS 508 is Req. we obtain the voltage V ext = R ext R ext + R eq V dd .
That is, β = R ext R ext + R eq
and the equivalent resistance R eq = 1 - β β R ext .

Let us assume that the aspect ratio of the NMOS 506 is ( W L ) n1 ,
the aspect ratio of the NMOS 508 is ( W L ) n2 ,
and the ratio between ( W L ) n1
and ( W L ) n2
is y, then ( W L ) n1 = y ( W L ) n2 .
Let us assume that R101 denotes the equivalent resistance viewed at the drain of the NMOS 506, where R Φ = 1 μ n C ox ( W L ) n1 ( V gs1 - V tn ) R eq = 1 μ n C ox ( W L ) n2 ( V gs2 - V tn ) V sg1 = V sg2 R Φ = 1 y R eq R Φ = 1 y 1 - β β R ext
where, μn is the carrier mobility, Cox is the electric capacitance per unit area at the gate, Vgs1 and VgS2 are the voltage drops across the source and the gate, and |Vin| is the threshold voltage.

Therefore, when the input impedance Zin 518 at the input terminal of the receiver 504 is relatively large, the parallel connection of the equivalent resistance R101 of the impedance matching circuit 500 and the input impedance Zin 518 results in a resistance value approximately equal to equivalent resistance R101 of the impedance matching circuit 500. When the resistance of equivalent resistance R101 of the impedance matching circuit 500 is determined to be equal to that of the characteristic impedance Z101 of the cable 502, impedance matching can be achieved.

When the characteristic impedance Z101 of the cable 502 varies, the multiplexer 514 of the impedance matching circuit 500 outputs a reference voltage Vref with a different magnitude to the inverting input terminal of the operational amplifier 512. As the Vref at the inverting input terminal of the operational amplifier 512 is adjusted, the value of β as well as the value of Req is also adjusted. Accordingly, the value of the equivalent resistance R101 is adjusted to match the varied characteristic impedance Z101 of the cable 502. Therefore, when the characteristic impedance Z101 of the cable 502 varies, the multiplexer 514 selects a suitable reference voltage Vref from the reference voltage generator 516 to change the equivalent resistance R101 of the impedance matching circuit 500 such that the equivalent resistance R101 is equal to the resistance value of the characteristic impedance Z101 of the cable 502. Therefore, impedance matching is achieved.

According to the above discussion, the present invention discloses an impedance matching circuit with adjustable resistance for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission even when the characteristic impedance of the cable varies. Therefore, the present invention has been examined to be progressive, advantageous and applicable to the industry.

Although this invention has been disclosed and illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other embodiments that will be apparent to persons skilled in the art. This invention is, therefore, to be limited only as indicated by the scope of the appended claims.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US9264038 *Feb 26, 2014Feb 16, 2016Texas Instruments IncorporatedLine receiver circuit with active termination
US20150244363 *Feb 26, 2014Aug 27, 2015Texas Instruments, Inc.Line receiver circuit with active termination
Classifications
U.S. Classification326/30, 326/83
International ClassificationH04L25/02, H03K19/003
Cooperative ClassificationH04L25/0278
European ClassificationH04L25/02K5
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