|Publication number||USRE41670 E1|
|Application number||US 09/488,686|
|Publication date||Sep 14, 2010|
|Filing date||Jan 20, 2000|
|Priority date||Dec 17, 1993|
|Also published as||US5395785, US5710461|
|Publication number||09488686, 488686, US RE41670 E1, US RE41670E1, US-E1-RE41670, USRE41670 E1, USRE41670E1|
|Inventors||Loi Nguyen, Ravishankar Sundaresan|
|Original Assignee||Stmicroelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (42), Non-Patent Citations (4), Classifications (30)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of application No. 08/328,736, filed Oct. 25, 1995, which was abandoned upon the filing herein which is a divisional of 08/49,338, filed Dec. 17, 1993, now U.S. Pat. No. 5,395,785.
The present invention relates to integrated circuit fabrication methods and structures, and particularly to integrated circuits with minimum linewidths below one-half micron.
As the degree of integration has advanced, it has become increasingly apparently that it is desirable to minimize the topographical excursion of the surface at each level, especially the upper levels. To accomplish this, various planarization schemes have been used to planarize the inter-level dielectric. Some of these include Chemical-Mechanical-Polishing (CMP), use of Permanent Spin-on-glass (left in place in the final chip), and Sacrificial Etchback Spin-on-glass (SOG).
Spin-on glass deposition is an example of a “sol-gel” process, which has been used in the semiconductor industry for many years. The unprocessed spin-on glass material (available in numerous formulations) is a fluid material (actually a gel). After the liquid material is coated onto the face of a wafer, the wafer is rotated at high speed to throw off the excess material. The surface tension and adhesion of the material provides a flat (planarized) surface with a controlled thickness. The liquid material is then baked, to drive off solvents and provide a stable solid silicate glass. See generally, e.g., Dauksher et al., “Three ‘low Dt’ options for planarizing the pre-metal dielectric on an advanced double poly BiCMOS process,” 139 J.ELECTROCHEM.SOC. 532-536 (1992), which is hereby incorporated by reference.
Background: SRAM Cell Operation
One of the two most common types of SRAM cell is the “4-T” cell, which uses resistive loads.
In such a memory cell, the resistors R1 and R2 must pass enough current to offset the leakage currents which tend to discharge the high node of the latch. These resistors are conventionally made from nearly intrinsic polysilicon, and therefore tend to have very high resistance values (which may range from many gigaohms up to teraohms). Unfortunately, the resistivity of such polysilicon is fairly variable, and an excessive value for the resistors may cause the cell to lose data under high-temperature conditions. An excessively low value for the polysilicon resistor may lead to excess static power consumption. Thus, precise control of the resistor values would be highly desirable.
Innovative SRAM Structure and Process
This disclosure describes an improved method of four transistor SRAM cell fabrication, wherein planarization is performed before metal formation (and actually before resistor formation). The pre-metal planarization utilizes a sandwich structure comprising permanent SOG, undoped glass, and permanent SOG. The undoped glass is used as a buffer layer between two layers of spin-on-glass to prevent SOG cracks. The double SOG spin enhances the degree of planarization.
The disclosed inventions thus provide the advantages of reduced topography at the poly-2 level, and hence more accurate patterning of the poly resistors, and hence a reduced poly-R resistance value by shortening resistor length (less surface contour due to better planarity). This provides more precise manufacturing control which can be used to set speed and power more reliably.
The present invention will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:
The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.
After completion of CMOS transistor formation (and local interconnect formation in the poly-2 layer, if desired), a standard process flow (as shown in
In the innovative process embodiments described, fabrication of the lower poly level(s) is instead followed by:
The disclosed inventions thus provide the advantages of reduced topography at the top poly level, and hence more accurate patterning of the poly resistors. A comparison of
The disclosed inventions also provide the advantages of reduced poly-R resistance value by shortening the effective resistor length (since the reduced surface contour leads to better planarity). A comparison of
A second layer of polysilicon 230 (which, in the presently preferred embodiment, is also clad with a respective tantalum silicide layer 232) provides local interconnect within the cell. (This composite layer 230/232 is referred to herein as the “poly-2” layer.) A permanent SOG layer 150, overlaid by an undoped oxide layer 160, provides some planarization over the poly-2 layer. (An additional layer of undoped oxide, which is omitted from this drawing for simplicity, underlies the permanent SOG layer 150.) A shared contact, in the presently preferred embodiment, provides contacts from poly-1 and poly-2 to active.
A third polysilicon layer 330, made of substantially intrinsic polysilicon, provides the polysilicon resistors. (This layer 330 is referred to herein as the “poly-R” layer.) Another shared contact is used to provide contact from this layer to the poly-2 (and poly-1) layers.
This results in a structure wherein the topographic excursion H2 of the more planar poly-R layer 330′0 provided by the disclosed innovations is much less than the topographic excursion H1 of the poly-R layer 330 of the more conventional structure shown in FIG. 1.
The disclosed inventions also provide the advantages of reduced topographical excursion for the contact and metal-1 layer, and hence reduced requirements for planarization after the poly-2 layer.
The resistors R1 and R2 are preferably laid out to have a target resistance value of about 1TΩ, but of course this value can be adjusted, by appropriate layout changes, to adjust for speed and power requirements as needed. However, the disclosed innovations permit the resistor value to be specified with greater precision.
Further Modifications and Variations
It will be recognized by those skilled in the art that the innovative concepts disclosed in the present application can be applied in a wide variety of contexts. Moreover, the preferred implementation can be modified in a tremendous variety of ways. Accordingly, it should be understood that the modifications and variations suggested below and above are merely illustrative. These examples may help to show some of the scope of the inventive concepts, but these examples do not nearly exhaust the full scope of variations in the disclosed novel concepts.
While the inventions have been described with primary reference to a 4-T SRAM cell, it will be readily recognized that these inventions can also be applied to other integrated circuits which use resistive loads. Note, however, that the disclosed innovations would not be as applicable to processes which include floating-gate memory cells or poly-to-poly capacitors in the top poly level, since the planarization provided by the disclosed inventions would require additional process complexity to achieve the close coupling from the top poly level to the next lower poly level.
Although the presently preferred embodiment actually uses a triple-poly cell layout, it will be readily recognized that the disclosed ideas can also be adapted for use in a double-poly resistive-load SRAM cell.
Although the resistors are formed from intrinsic polysilicon in the presently preferred embodiment, it will be recognized that a slight amount of doping may be desirable to stabilize the characteristics of this material. For example, this material may be doped with chlorine, or may be SIPOS (containing a large fraction of oxygen).
As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given.
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|U.S. Classification||257/754, 257/752, 257/903, 257/E21.243, 257/760, 257/640, 257/385, 257/904, 257/381, 257/740, 257/380, 257/E21.661, 257/350, 257/758, 257/E21.578|
|International Classification||H01L21/768, H01L21/8244, H01L23/48, H01L23/522, H01L21/02, H01L21/70, H01L29/34, H01L21/3105|
|Cooperative Classification||Y10S257/903, Y10S257/904, H01L27/11, H01L27/1112, H01L21/76819|
|European Classification||H01L27/11, H01L21/768B4|