|Publication number||USRE41728 E1|
|Application number||US 11/030,731|
|Publication date||Sep 21, 2010|
|Filing date||Jan 6, 2005|
|Priority date||Aug 14, 2001|
|Also published as||EP1284504A2, EP1284504A3, US6504416|
|Publication number||030731, 11030731, US RE41728 E1, US RE41728E1, US-E1-RE41728, USRE41728 E1, USRE41728E1|
|Original Assignee||Stmicroelectronics, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Non-Patent Citations (7), Classifications (6), Legal Events (1)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention is directed, in general, to voltage controlled resistors and, more specifically, to voltage controlled resistors with high resistance-to-voltage linearity for use in tuning circuits and the like.
Voltage controlled resistors, having a resistance which varies with an applied voltage, have use in a wide variety of applications, including, for example, tuning circuits. Metal oxide semiconductor (MOS) transistors may function as voltage controlled resistors if operated in the ohmic region, with the gate-source voltage controlling the resistance.
Within the signal path of a signal processing circuit, however, the resistance of an MOS transistor employed to provide voltage controlled resistance also changes with the source-drain voltage. If the gate voltage is held constant, the resistance of the transistor changes with the source voltage, introducing high non-linearity in the resistive behavior of the transistor. This non-linearity becomes higher as the overdrive voltage applied to the transistor—the gate-source voltage minus the threshold voltage (Vgs−Vt)—decreases. As the voltage supply becomes lower, providing a good overdrive of the transistor becomes increasingly difficult, particularly if the source (assuming an n-channel transistor) cannot be connected to ground.
There is, therefore, a need in the art for a voltage controlled resistor having a high linearity of resistance per unit change in applied voltage.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide, for use in an integrated circuit, a voltage-controlled resistance structure formed from a number of voltage-controlled resistance cells, each including a transistor with a biasing capacitor connected between the gate and source and an associated controller coupled to the capacitor to maintain a steady charge on the biasing capacitor and keep the gate-source voltage at a control voltage corresponding to a desired resistance. The gate voltage applied to each transistor is able to “float” together with the source voltage in order to keep the gate-source voltage constant, and the resistance structure exhibits improved voltage-dependent resistance linearity together with a larger range of biasing while lowering needed refresh frequencies to avoid noise injection.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art will appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words or phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, whether such a device is implemented in hardware, firmware, software or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, and those of ordinary skill in the art will understand that such definitions apply in many, if not most, instances to prior as well as future uses of such defined words and phrases.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, wherein like numbers designate like objects, and in which:
Controller 300 is employed with each resistance cell 101n in order to maintain a constant charge on capacitor cgate within voltage controlled resistor 200. Controller 300 includes two transistors MWG1 and MWG2 connected in series between the gate (node g) of transistor M0 and the input for control voltage Vg. Transistors MWG1 and MWG2 are an n-channel transistor and a p-channel transistor, respectively, in the exemplary embodiment, having their sources connected together with the drain of transistor MWG1 connected to the control voltage input Vg and the drain of transistor MWG2 connected to the gate of transistor MO. The gate-source voltage Vgs which is to be “translated” into a resistance is applied to the control voltage input Vg.
Controller 300 also includes a capacitor cvreg connected in parallel with the capacitor cgate by transistor MWG2, which connects one terminal of capacitor cvreg to a terminal (node n1) of capacitor cgate and to the gate of transistor M0 (node g), and by transistor MSWS, an n-channel transistor in the exemplary embodiment which connects the other terminal (node n2) of capacitor cvreg to both the second terminal of capacitor cgate and the source of transistor M0 (node s). The gate of transistor MWG2 is connected to the control input WG2 while the gate of transistor MSWS is connected to the control input WS.
Transistor MSWS is connected at the source to capacitor cgate and the source of transistor M0 (node s) and at the drain to capacitor cvreg and the drain of transistor MWC (node n2). Transistor MWC, an n-channel transistor in the exemplary embodiment, is connected at the source to a ground voltage level gnd and a the gate to both the gate of transistor MWG1 and the control input WC.
In operation, when control input WS is high and control inputs WG2 and WC are both low, transistors MWG2 and MSWS are on, shorting capacitors cvreg and cgate together, while transistors MWG1 and MWc are both off. Both capacitors cvreg and cgate are therefore allowed to “follow” the voltage at the source of transistor M0 (node s). When control input WS goes low and control input WG2 goes high (while control input WC remains low), transistors MWG2 and MSWS are off, thus disconnecting capacitor cvreg from capacitor cgate, although capacitor cgate is still allowed to “float” and follow the voltage at the source of transistor M0 (node s). Once disconnected from capacitor cgate, capacitor cvreg is ready to be recharged by the input voltage Vg, which is enabled by control input WC going high and turning on transistors MWG1 and MWC.
The voltage controlled resistance structure of the present invention has several advantages over other voltage controlled resistance structures: Power dissipation is very small, since only a small amount of charge is needed to compensate the losses on the capacitors (leakage currents) once the circuit has reached rest biasing. By connecting a number of resistance cells of the type disclosed in series, the variation of each source-drain voltage (Vds) is smaller, so that the resistance is much more linear over the Vds variation, which is now reduced.
The improved voltage-dependent resistance linearity of the voltage-controlled resistance structure of the present invention is possible because the gate-source voltage Vgs applied to each transistor is able to “float”, together with the source voltage, which also allows a larger range of biasing since if the voltage at the sources (node s) of each transistor M0 grows, the voltage at the gate (node g) also grows and may even become higher than the supply voltage if necessary (and not harmful to the circuit). The improved voltage-dependent resistance linearity within the voltage-controlled resistance structure of the present invention also allows the frequency of the refreshing signals (control inputs WC, WS and WG2) to be relatively low, limiting problems due to noise injection on nodes sensitive to such problems.
Although the present invention has been described in detail, those skilled in the art will understand that various changes, substitutions, and alterations herein may be made without departing from the spirit and scope of the invention in its broadest form.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5640123 *||May 24, 1995||Jun 17, 1997||Fujitsu Limited||Substrate voltage control circuit for a flash memory|
|US6472948 *||Jul 10, 2000||Oct 29, 2002||Rockwell Collins, Inc.||High-power precision 1 dB step attenuator|
|1||*||"A Wide Range Linear Variable Resistor by Buried Channel MOS/SIMOX," Masahiro Akiya, Sadao Nakashima and Kotaro Kato, IEEE Journal of Solid-State Circuits, vol. SC-19, No. 4, Aug. 1984.|
|2||*||"Continuous-time MOSFET-C Filters in VLSI," Yannis Tsividis, Mihai Banu and John Khoury, IEEE Journal of Solid-State Circuits, vol. SC-21, No. 1, Feb. 1986.|
|3||*||"Six-Terminal MOSFET's: Modeling and Applicatioms in Highly Linear, Electronically Tunable Resistors," Kostas VVavelidis, Yannis P. Tsividis, Frank op't Eynde and Yannis Papananos, IEEE Journal of Solid-State Circuits, vol. 32, No. 1, Jan. 1997.|
|4||*||"Six—Terminal MOSFET's: Modeling and Applicatioms in Highly Linear, Electronically Tunable Resistors," Kostas VVavelidis, Yannis P. Tsividis, Frank op't Eynde and Yannis Papananos, IEEE Journal of Solid-State Circuits, vol. 32, No. 1, Jan. 1997.|
|5||Allen and Holberg, "CMOS Analog Circuit Design", 1987, p. 506.|
|6||Geiger, Randall L., Allen, Phillip and Ngo, Dinh Tai, "Switched-Resistor Filters-A Continuous Time Approach to Monolithic MOS Filter Design", IEEE Transactions on Circuits and Systems, vol. CAS-29, No. 5, May 1982 pp. 306-315.|
|7||Geiger, Randall L., Allen, Phillip and Ngo, Dinh Tai, "Switched-Resistor Filters—A Continuous Time Approach to Monolithic MOS Filter Design", IEEE Transactions on Circuits and Systems, vol. CAS-29, No. 5, May 1982 pp. 306-315.|
|International Classification||H03F1/00, H03H11/24, H03L5/00|