US RE41730 E1
An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available.
1. An analog-to-digital (A/D) converter, comprising:
an input, for receiving a series of analog signals;
an output, for outputting a series of digital signals respectively corresponding to said series of analog signals;
a plurality of A/D cells, each of said A/D cells for converting one of said series of analog signals to a corresponding one of said series of digital signals; and
a control circuit, coupled to said input, said output, and said plurality of A/D cells;
wherein said control circuit operates said input, said output, and said plurality of A/D cells so that each successive A/D cell is assigned, at a different time, to convert a different one of each successive analog signal from said series of analog signals to a corresponding digital signal in said series of digital signals.
2. The analog-to-digital converter of
3. The analog-to-digital converter of
4. The analog-to-digital converter of
5. The analog-to-digital converter of
6. The analog-to-digital converter of
7. The analog-to-digital converter of
8. The analog-to-digital converter of
9. The analog-to-digital converter of
10. A method for converting a series of analog signals to a corresponding series of digital signals, comprising:
receiving over a period of time, a series of analog signals;
assigning each analog signal from said series of analog signals as they are received to an available A/D cell for analog-to-digital conversion to a corresponding digital signal; and
outputting a different digital signal corresponding to a respective analog signal from said series of analog signals as each A/D cell finishes its analog-to-digital conversion;
wherein at least two A/D cells are performing respective analog-to-digital conversions while another A/D cell outputs one of said digital signals.
11. The method of
calibrating each A/D cell so that an analog-to-digital conversion performed on a same analog signal by any A/D cell results in a same digital signal.
12. The method of
13. The method of
14. The method of
15. A method comprising:
forming an image from the light onto an array of photoreceptors of a CMOS active pixel sensor;
translating the image into a plurality of successive analog signals; and
converting each of the plurality of successive analog signals to a respective each of a plurality of successive digital signals during time periods that are offset and partially overlapping, wherein the converting comprises the use of a plurality of successive approximation analog to digital converter cells.
16. The method of
17. A method comprising:
enabling an image to be provided to an array of photoreceptors of a CMOS active pixel sensor;
converting at least a portion of the image into first, second, and third successive analog signals;
providing the first, second, and third successive analog signals to an input of an analog to digital (A/D) converter, operating in a pipelined fashion, at first, second, and third times, respectively, wherein the first, second, and third times are offset in time from one another; and
providing at least a respective first bit of respective first, second, and third successive digital signals corresponding to the first, second, and third analog signals, respectively, at fourth, fifth, and sixth times, respectively, wherein the fourth, fifth, and sixth times are offset in time from one another and occur after the first, second, and third times.
18. The method of
19. The method of
20. The method of
21. The method of
22. The method of
This application is a continuation of application Ser. No. 10/061,938, filed Oct. 25, 2001 (scheduled to issue as 11/812,785, filed Jun. 21, 2007, which is a reissue application of U.S. Pat. No. 6,909,392, which issued on Jun. 21, 2005, which is a continuation of U.S. Pat. No. 6,646,583, which issued on Nov. 11, 2003) , which claims priority from provisional Application No. 60/243,324 filed Oct. 25, 2000. The subject matter of applications Ser. Nos. 10/061,938 and 60/243,324 are hereby incorporated by reference.
The basic operation of a CMOS active pixel sensor is described in U.S. Pat. No. 5,471,215. This kind of image sensor, and other similar image sensors, often operate by using an array of photoreceptors to convert light forming an image, into signals indicative of the light, e.g. charge based signals. Those signals are often analog, and may be converted to digital by an A/D converter. Image sensors which have greater numbers of elements in the image sensor array may produce more signals. In order to handle these signals, either more A/D converters must be provided, or the existing A/D converters need to digitize the data from these image sensors at higher signal rates. For example, a high precision CMOS active pixel sensor may require an A/D converter which is capable of 10 bits of resolution at 20 Megasamples per second.
Image sensors of this type are often limited by the available area or “real estate” on the chip, a and the available power for driving the chip. An advantage of using CMOS circuitry is that power consumption of such a circuit may be minimized. Therefore, the power consumption of such a circuit remains an important criteria. Also, since real estate on the chip may be limited, the number of A/D converters and their size should be minimized.
A/D converters with this kind of resolution, in the prior art, may have a power consumption of about 25 mw using a 3.3 volt power supply.
The present application describes a system, and a special A/D converter using individual successive approximation A/D converter cells which operate in a pipelined fashion.
These and other aspects will now be described in detail with reference to the accompanying drawings, wherein:
According to the present system, a plurality of successive approximation A/D converter cells are provided. The embodiment recognizes that the pixel analog data is arriving at a relatively high rate, e.g. 20 Mhz. A plurality of A/D converters are provided, here twelve A/D converters are provided, each running at 1.6 megasamples per second. The timing of these A/D converters are staggered so that each A/D converter is ready for its pixel analog input at precisely the right time. The power consumption of such cells is relatively low; and therefore the power may be reduced.
In the embodiment, an A/D converter with 10 bits of resolution and 20 megasamples per second is provided that has a power consumption on the order of 1 mW. Twelve individual successive approximation A/D converter cells are provided. Each requires 600 ns to make each conversion. Since twelve stages are necessary, the total data throughput equals twelve/600 ns=20 megasamples per second. Each successive approximation A/D converter requires 12 complete clock cycles to convert the 10 bit data. The first clock cycle samples the input data, then 10 clock cycles are used to convert each of the bits. A single clock cycle is used for data readout.
A block diagram is shown in FIG. 1.
This system may adaptively assign the channels to A/D converters in a different way than conventional. Conventional methods of removing fixed patterned noise, therefore, might not be as effective. Therefore, it becomes important that these A/D converters have consistent characteristics. In this embodiment, calibration may be used to compensate for offsets between the comparators of the system.
Successive approximation A/D converters as used herein may have built-in calibration shown as elements 320. Any type of internal calibration system maybe used.
The inventors also realize that comparator kickback noise may become a problem within this system. That comparator itself may produce noise which may affect the signal being processed. In this embodiment, a single preamplifier, here shown as a follower 330, is introduced between the signal and the comparator.
This system also requires generation of multiple timing and control signals to maintain the synchronization. Each successive approximation A/D converter requires about 20 control signals. The timing is offset for each of the twelve different A/D converters. Therefore, digital logic is used to replicate control signals after a delay.
In one embodiment, shown in
Each cycle of the A/D converter may require finer timing than can be offered by a usual clock. Hence, the clock input 410 may be a divided higher speed clock.
Two D type flip-flops are required to delay each signal. Any signal which is only half a clock cycle in length may require falling edge flip-flops, in addition to the rising edge flip-flops, and may also require additional logic.
Although only a few embodiments have been disclosed in detail above, other modifications are possible. For example, different logic techniques may be used herein. In addition, while the above describes specific numbers of bits, the same techniques are applicable to other numbers of elements. For example, this system may be used with as few as three elements, with the three successive approximation devices staggered to receive one out of every three inputs.
The above has described matched unit cell capacitors, but it should also be understood that other capacitors could be used. Conventional capacitors which are not matched in this way can be used. In addition, the capacitors can be scaled relative to one another by some amount, e.g. in powers of two.
All such modifications are intended to be used within the following claims.