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Publication numberUSRE41764 E1
Publication typeGrant
Application numberUS 11/318,397
Publication dateSep 28, 2010
Filing dateJun 5, 2000
Priority dateJun 11, 1999
Fee statusPaid
Also published asEP1186051A1, EP1186051B1, US6667513, WO2000077856A1
Publication number11318397, 318397, US RE41764 E1, US RE41764E1, US-E1-RE41764, USRE41764 E1, USRE41764E1
InventorsThomas Skotnicki, Romain Gwoziecki
Original AssigneeThomas Skotnicki, Romain Gwoziecki
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device with compensated threshold voltage and method for making same
US RE41764 E1
Abstract
A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity type. At least one second pocket may be formed adjacent to each of the junctions and stacked against each of the first pockets. The second pocket may be doped with a dopant of a second conductivity type such that the dopant concentration in the second pocket is less than the dopant concentration in the first pockets. The second pocket may reduce a local substrate concentration without changing the conductivity type of the channel region.
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Claims(49)
1. A semiconductor device, comprising:
a semiconductor substrate having a predetermined concentration, Ns, of a dopant of a first conductivity type;
a source region and a drain region doped with a dopant of a second conductivity type;
junctions, wherein the junctions delimit a channel region of a predetermined length, LN, in the substrate, wherein the junctions are defined by the source region and the drain region;
first pockets located adjacent to each of the junctions, wherein the pockets have a predetermined length, Lp, wherein the first pockets are doped with a dopant of the first conductivity type with a dopant concentration, Np, which locally increases a net concentration in the substrate above Ns;
second pockets located adjacent to each of the junctions and stacked against each of the first pockets, wherein the second pockets have a length, Ln, such that Ln is greater than Lp, and wherein the second pockets are doped with a dopant of the second conductivity type with a dopant concentration, Nn, such that Nn is less than Np, which locally decreases a net concentration without changing a conductivity type, and wherein Nn is less than Ns; and
wherein an overall length of the first pockets and the second pockets is less than the length, LN, of the channel region.
2. The semiconductor device of claim 1, wherein the second pockets comprise a plurality of elementary pockets stacked against each other.
3. The semiconductor device of claim 1, wherein the second pockets comprise a plurality of elementary pockets stacked against each other, wherein each elementary pocket comprises a rank, i, and a predetermined length, Lni, wherein a predetermined concentration, Nni, of a dopant of the second conductivity type satisfies the relationships:
Ln1>Lp;
Lni−1<Lni<Lni+1;
Nni−1>Nni>Nni+1; and
wherein the sum, ΣNni, of the concentrations of the dopant in the elementary pockets satisfies the relationship, ΣNni<Ns.
4. The semiconductor device of claim 1, wherein the second pockets comprise a plurality of elementary pockets stacked against each other, and wherein the plurality of elementary pockets comprises three elementary pockets.
5. The semiconductor device of claim 1, wherein the semiconductor device comprises an MOS transistor.
6. The semiconductor device of claim 1, wherein the first conductivity type comprises p-type conductivity.
7. The semiconductor device of claim 1, wherein the second conductivity type comprises n-type conductivity.
8. A method for fabricating a semiconductor device, comprising:
forming a semiconductor substrate with a predetermined concentration, Ns, of a dopant of a first conductivity type;
forming a source region and a drain region by doping the source and drain regions with a dopant of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type, wherein the source and drain regions form junctions that delimit a channel region between them, and wherein the channel region comprises a predetermined length, LN;
forming first pockets adjacent to each of the junctions in the channel region, wherein the first pockets are formed by doping each of the first pockets with a predetermined concentration, Np, of a dopant of the first conductivity type, which locally increases a net concentration in the substrate above Ns, and wherein each of the first pockets comprises a predetermined length, Lp; and
implanting in the channel region a dopant of the second conductivity type under a set of conditions such that second pockets are formed in the channel region, wherein the second pockets are stacked against each of the first pockets, wherein the second pockets have a length, Ln, such that Ln is greater than Lp, wherein the second pockets have a concentration, Nn, of the dopant of the second conductivity type such that Nn is less than Np, which locally decreases a net concentration without changing a conductivity type, wherein Nn is less than Ns, and wherein the overall length of the first pockets and the second pockets is less than the nominal length, LN, of the channel region.
9. The method of claim 8, wherein implanting in the channel region comprises a series of successive implanting steps such that the second pockets comprise a plurality of elementary pockets.
10. The method of claim 8, wherein implanting in the channel region comprises a series of successive implantion implantation steps such that the second pockets comprise comprises a plurality of elementary pockets, wherein each elementary pocket comprises a rank, i, and a predetermined length, Lni, and wherein a predetermined concentration, Nni, of a dopant of the second conductivity type satisfies the relationships:
Ln1>Lp;
Lni−1<Lni<Lni+1;
Nni−1>Nni>Nni+1; and
wherein the sum, ΣNni of the concentrations of the dopant in the elementary pockets satisfies the relationship, ΣNni<Ns.
11. The method of claim 10, further comprising increasing an implantation angle of incidence with respect to the normal angle to the substrate with each successive implantion implantation step and decreasing an implantation dose with each successive implantion implantation step.
12. The method of claim 10, wherein the successive implanting steps comprise implanting the dopant of the second conductivity type using a same angle of incidence with respect to the normal angle to the substrate, a same implantation dose, and a same implantation energy in each successive implantion implantation step, the method further comprising annealing the device in an annealing step after each successive implantion implantation step, wherein each annealing step is different.
13. The method of claim 8, wherein the set of conditions comprises an implantation angle of incidence with respect to the normal angle to the substrate, an implantation dose, and an implantation energy.
14. The method of claim 8, wherein the set of conditions comprises an implantation angle of incidence with respect to the normal angle to the substrate.
15. The method of claim 8, wherein the set of conditions comprises an implantation dose.
16. The method of claim 8, wherein the set of conditions comprises an implantation energy.
17. The method of claim 8, further comprising forming an MOS transistor with the semiconductor device.
18. The method of claim 8, wherein the first conductivity type comprises p-type conductivity.
19. The method of claim 8, wherein the second conductivity type comprises n-type conductivity.
20. A semiconductor device, comprising:
a semiconductor substrate having a concentration, Ns, of a dopant of a first conductivity type;
a source region and a drain region doped with a dopant of a second conductivity type;
junctions that define a channel region of a length, LN, in the substrate, wherein the junctions are defined by the source region and the drain region;
first pockets located adjacent to each of the junctions, wherein the first pockets have a length, Lp, and wherein the first pockets are doped with a dopant of the first conductivity type with a dopant concentration, Np;
second pockets stacked against each of the first pockets, wherein the second pockets have a length, Ln, such that Ln is greater than Lp, wherein the second pockets are doped with a dopant of the second conductivity type with a dopant concentration, Nn, such that Nn is less than Np; and
wherein an overall length of the first pockets and the second pockets is less than the length, LN, of the channel region.
21. A semiconductor device, comprising:
a semiconductor substrate having a concentration, Ns, of a dopant of a first conductivity type;
a source region and a drain region doped with a dopant of a second conductivity type;
junctions that define a channel region of a length, L N , in the substrate, wherein the junctions are defined by the source region and the drain region;
first pockets including a pocket located adjacent to each of the junctions, wherein each of the first pockets is doped with a dopant of the first conductivity type with a dopant concentration, Np;
second pockets including one pocket stacked against each of the first pockets, wherein each of the second pockets is doped with a dopant of the second conductivity type with a dopant concentration, Nn; and
wherein an overall length of the first pockets and the second pockets is less than the length, L N , of the channel region.
22. The semiconductor device of claim 21, wherein the first pockets each have a length, Lp, and the second pockets each have a length, Ln, and wherein Ln is greater than Lp.
23. The semiconductor device of claim 21, wherein Nn is less than Np.
24. The semiconductor device of claim 21, wherein each of the second pockets comprise a plurality of elementary pockets stacked against each other.
25. The semiconductor device of claim 21, wherein each of the second pockets comprises a plurality of elementary pockets stacked against each other, wherein each elementary pocket in one of the second pockets has a rank, i, a length, Lni , and a concentration, Nn i , of a dopant of the second conductivity type satisfying the relationships:
Ln 1 >Lp;
Ln i−1 <Ln i <Ln i+1;
Nn i−1 >Nn i >Nn i+1 ; and
wherein the sum, ΣNn i , of the concentrations of the dopant in the elementary pockets in one of the second pockets satisfies the relationship, ΣNn i <Ns.
26. The semiconductor device of claim 21, wherein each of the second pockets comprises a plurality of elementary pockets stacked against each other, and wherein the plurality of elementary pockets comprises three elementary pockets.
27. The semiconductor device of claim 21, wherein the semiconductor device comprises an MOS transistor.
28. The semiconductor device of claim 21, wherein the first conductivity type is p-type conductivity.
29. The semiconductor device of claim 21, wherein the second conductivity type is n-type conductivity.
30. A method for fabricating a semiconductor device, comprising:
forming a semiconductor substrate with a concentration, Ns, of a dopant of a first conductivity type;
forming a source region and a drain region by doping the source and drain regions with a dopant of a second conductivity type, wherein the second conductivity type is opposite the first conductivity type, wherein the source and drain regions form junctions that delimit a channel region between them, and wherein the channel region comprises a length, L N;
forming first pockets including a pocket adjacent to each of the junctions in the channel region, wherein each of the first pockets is formed by doping each of the first pockets with a concentration, Np, of a dopant of the first conductivity type; and
implanting in the channel region a dopant of the second conductivity type under a set of conditions such that second pockets are formed in the channel region, wherein the second pockets include a pocket stacked against each of the first pockets, wherein the second pockets have a concentration, Nn, of the dopant of the second conductivity type, and wherein the overall length of the first pockets and the second pockets is less than the length, L N , of the channel region.
31. The method of claim 30, wherein forming the first pockets with the concentration, Np, locally increases a net concentration in the substrate above Ns.
32. The method of claim 30, wherein each of the first pockets has a length, Lp, and each of the second pockets have a length, Ln, and wherein Ln is greater than Lp.
33. The method of claim 30, wherein Nn is less than Np which locally decreases a net concentration without changing a conductivity type.
34. The method of claim 30, wherein Nn is less than Ns.
35. The method of claim 30, wherein implanting in the channel region comprises a series of successive implanting steps such that each of the second pockets comprises a plurality of elementary pockets.
36. The method of claim 30, wherein implanting in the channel region comprises a series of successive implantation steps such that each of the second pockets comprises a plurality of elementary pockets, wherein each elementary pocket has a rank, i, a length, Lni , and a concentration, Nn i , of a dopant of the second conductivity type satisfying the relationships:
Ln 1 >Lp;
Ln i−1 <Ln i <Ln i+1;
Nn i−1 >Nn i >Nn i+1 ; and
wherein the sum, ΣNn i , of the concentrations of the dopant in the elementary pockets in each of the second pockets satisfies the relationship, ΣNn i <Ns.
37. The method of claim 36, further comprising increasing an implantation angle of incidence with respect to the normal angle to the substrate with each successive implantation step and decreasing an implantation dose with each successive implantation step.
38. The method of claim 36, wherein the successive implanting steps comprise implanting the dopant of the second conductivity type using a same angle of incidence with respect to the normal angle to the substrate, a same implantation dose, and a same implantation energy in each successive implantation step, the method further comprising annealing the device in an annealing step after each successive implantation step, wherein each annealing step is different.
39. The method of claim 30, wherein the set of conditions comprises an implantation angle of incidence with respect to the normal angle to the substrate.
40. The method of claim 30, wherein the set of conditions relates to an implantation dose.
41. The method of claim 30, wherein the set of conditions relates to an implantation energy.
42. The method of claim 30, further comprising forming a MOS transistor with the semiconductor device.
43. The method of claim 30, wherein the first conductivity type is p-type conductivity.
44. The method of claim 43, wherein the second conductivity type is n-type conductivity.
45. A semiconductor device, comprising:
a semiconductor substrate having a concentration, Ns, of a dopant of a first conductivity type;
a source region and a drain region doped with a dopant of a second conductivity type;
first and second junctions that define a channel region of a length, L N , in the substrate, wherein the first and seocnd junctions are defined by the source region and the drain region, respectively;
a first set of pockets that includes a first pocket and a second pocket, wherein the first and second pockets are located adjacent to the first and second junctions, respectively, and wherein each of the first set of pockets is doped with a dopant of the first conductivity type with a dopant concentration, Np;
a second set of pockets that includes at least one pocket in the channel region adjacent to the first pocket, and at least one pocket in the channel region adjacent to the second pocket, wherein each of the second set of pockets is doped with a dopant of the second conductivity type with a dopant concentration, Nn; and
wherein an overall length of the first set of pockets and the second set of pockets is less than the length, L N , of the channel region.
46. The semiconductor device of claim 45, wherein each of the first set of pockets has a length, Lp, and each of the second set of pockets has a length, Ln, and wherein Ln is greater than Lp.
47. The semiconductor device of claim 45, wherein Nn is less than Np.
48. The semiconductor device of claim 45, wherein the second set of pockets includes:
a first group of at least two pockets located adjacent to the first pocket in the channel region, wherein the first group of at least two pockets are stacked against one another;
a second group of at least two pockets located adjacent to the second pocket in the channel region, wherein the second group of at least two pockets are stacked against one andother;
49. The semiconductor device of claim 45, wherein the second set of pockets includes at least two pockets stacked against each of the first set of pockets, wherein each of the at least two pockets stacked against each of the first set of pockets has a rank, i, and a length, Lni , and a concentration, Nn i , of a dopant of the second conductivity type that satisfy the relationship:
Ln 1 >Lp;
Ln i−1 <Ln i <Ln i+1 ;
Nn i−1 >Nn i >Nn i+1 ; and
wherein the sum, ΣNn i , of the concentrations of the dopant in the second set of pockets satisfies the relationship, ΣNn i <Ns.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to a semiconductor device, such as an MOS transistor, in which there is compensation for the drop in the threshold voltage (Vth) due to the short-channel effects, and to a process for fabrication of such a semiconductor device.

2. Description of the Related Art

For a given nominal channel length (L) of a transistor, the threshold voltage (Vth) drops suddenly, in particular for short-channel transistors (i.e., those having a channel length of less than 0.25 μm and typically a channel length, L, of about 0.18 μm).

The threshold voltage of a semiconductor device such as an MOS transistor, in particular a short-channel device, is a critical parameter of the device. This is because the leakage current of the device (for example, of the transistor) depends strongly on the threshold voltage. Taking into consideration current supply voltages and those envisaged in the future (from 0.9 to 1.8 volts) for such devices and the permitted leakage currents (Ioff of approximately 1 nA/μm), the threshold voltage Vth must have values of approximately 0.2 to 0.25 volts.

The sudden voltage drop (or roll-off) in the zones of the channel region of the semiconductor device results in dispersion of the electrical characteristics of the device and makes it difficult to obtain the desired threshold voltages.

To remedy this threshold voltage roll-off in semiconductor devices such as MOS transistors, it has been proposed, as described in the article “Self-Aligned Control of Threshold Voltages in Sub-0.02-μm MOSFETs” by Hajima Kurata and Toshihiro Sugii, IEEE Transactions on Electron Devices, Vol. 45, No. Oct. 10, 1998, to form, in the channel region, pockets adjacent to the source and drain region junctions that have a conductivity of the same type as the substrate; but in which, the dopant concentration is greater than that of the substrate.

Although this solution reduces the threshold voltage roll-off gradient in the channel region, the short-channel effects lead to a more rapid roll-off of the threshold voltage, Vth, than the increase in the threshold voltage that can be obtained by incorporating the compensation pockets of the prior art.

Consequently, although these compensation pockets allow partial local compensation for the roll-off of the threshold voltage, Vth, it is not possible to obtain complete compensation for the roll-off over the entire channel region range desired.

Therefore a semiconductor device, such as an MOS transistor, that remedies the drawbacks of the devices of the prior art may be desired.

More particularly, a semiconductor device, such as an MOS transistor, whose voltage threshold roll-off due to the short-channel effects is almost fully compensated for may be desired. This makes it possible to achieve channel lengths which are arbitrarily small but non-zero.

Also a semiconductor device, such as an MOS transistor, may have a constant threshold voltage, Vth, when the channel length, L, decreases down to very small effective channel lengths, for example, 0.025 μm or less.

A process for fabricating a semiconductor device may apply to devices having channels of arbitrarily small length, these being, moreover, technologically realizable.

DESCRIPTION OF THE INVENTION

A semiconductor device is described that may have a semiconductor substrate with a predetermined concentration, Ns, of a dopant of a first conductivity type. The device may have source and drain regions which are doped with a dopant of a second conductivity type, which is opposite of the first conductivity type. Junctions delimiting a channel region of predetermined nominal length, LN, may be defined in the substrate. A first pocket adjacent to each of the junctions and having a predetermined length, Lp, may be defined. The first pockets may be doped with a dopant of the first conductivity type but with a local concentration, Np, which locally increases the net concentration in the substrate. The device may include at least one second pocket located adjacent to each of the junctions and stacked against each of the first pockets. These second pockets may have a length, Ln, such that Ln>Lp. The second pockets may be doped with a dopant of the second conductivity type and have a concentration, Nn, such that Nn<Np. This may locally decrease the net concentration of the substrate without changing the conductivity type.

In an embodiment, the second pockets include a plurality of elementary pockets stacked against one another. Each elementary pocket of a given rank, i, may have a predetermined length, Lni, and a predetermined concentration, Nni, of a dopant of the second conductivity type satisfying the following relationships:

    • Ln1>Lp,
    • Lni−1<Lni<Lni+1,
    • Nni−1>Nni>Nni+1, and
    • the sum, ΣNni, of the concentrations of the dopant of the second conductivity type in the elementary pockets may be such that:
    • ΣNni<Ns.

In other words, the second pockets decrease the net concentration of dopant of the first conductivity type both in the first pockets and in the channel region. However, they do not change the conductivity type of the first pockets nor of the channel region.

A process for fabricating a semiconductor device as defined above is described. The process may include the formation of a source region and of a drain region in a semiconductor substrate having a predetermined concentration, Ns, of a dopant of a first conductivity type. The source region and the drain region may be doped with a dopant of a second conductivity type, which is opposite of the first conductivity type. The source and drain regions may form one or more junctions in the substrate such that the junctions delimit between them a channel region. The channel region may have a predetermined nominal length, LN. In the channel region in a zone adjacent to each of the junctions, one or more first pockets may be formed having a predetermined length, Lp, and a predetermined concentration, Np. This may locally increase the net concentration in the substrate above Ns. The process may furthermore include the implantation, in the channel region, of a dopant of the second conductivity type, which is opposite of the first conductivity type. This may be done under a set of conditions such that at least one second pocket is formed in the channel region. Each second pocket may be stacked against each of the first pockets, respectively. The second pocket may have a length, Ln, such that Ln>Lp, and a concentration, Nn, of a dopant of the first type such that Nn<Np. This may locally decrease the net concentration in the substrate, without changing the conductivity type.

In a preferred embodiment, the implantation of the dopant of the second conductivity type consists of a series of successive implantations under a set of conditions such that the second pockets formed each consist of a plurality of elementary pockets stacked against one another. Each elementary pocket of a given rank, i, may have a length, Lni, and a concentration, Nni, of a dopant of the second conductivity type satisfying the relationships:

    • Ln1>Lp,
    • Lni−1<Lni<Lni+1,
    • Nni−1>Nni>Nni+1, and
    • the sun sum, ΣNni, of the concentrations of the dopant of the second conductivity type in the elementary pockets being such that:
    • ΣNni<Ns.

The lengths Lp and Ln of the pockets are taken from the junctions.

Implantation of a dopant in a semiconductor substrate is a known process and it is possible, in the present process, to use any implantation process conventionally used in the technology of semiconductors.

As is known, the formation of doped pockets in a semiconductor substrate depends on the angle of incidence of the implantation with respect to the normal to the substrate, on the implantation dose, and on the implantation energy of the dopant. Thus, by varying the angle of incidence and the dopant dose, it is possible to increase the length of the implanted pocket and to vary the dopant concentration.

As a variant, in order to vary the length of the second implanted pockets and their dopant concentration, successive implantation steps may be carried out with the same angle of incidence with respect to the normal, the same dose, and the same implantation energy. However, subjecting the device to a different annealing heat treatment step after each successive implantation step may make the dopant implanted in the substrate diffuse differently for each implanted pocket.

BRIEF DESCRIPTION OF THE DRAWINGS

The remainder of the description refers to the appended figures, which show respectively:

FIG. 1, a first embodiment of a semiconductor device, such as an MOS transistor;

FIG. 2, a second embodiment of a semiconductor device; and

FIG. 3, a graph of the threshold voltage (Vth) for various semiconductor devices as a function of the effective channel length.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a first embodiment of a semiconductor device, such as an MOS transistor. The semiconductor device may include a semiconductor substrate 1, which may be, for example, a silicon substrate doped with a dopant of a first conductivity type (for example, p-type conductivity). Source 2 and drain 3 regions may be formed in the substrate 1 and doped with a dopant of a second conductivity type, which is opposite of the first conductivity type (for example, an n-type dopant). The source and drain regions may, in the substrate, define junctions 4, 5 delimiting between them a channel region 6.

The channel region 6 may be covered with a gate oxide layer 11 (for example, a thin silicon oxide layer), which is itself surmounted by a gate 12 (for example, a gate made of silicon). The gate 12 may be flanked on two opposed sides by spacers 13, 14 made of a suitable dielectric.

To reduce the rate of roll-off of the threshold voltage, Vth, in the channel region 6, two first pockets 7, 8 are formed in the channel region. Each pocket may be adjacent to one of the junctions 4, 5, respectively. These pockets are doped by means of a dopant of the first conductivity type, p, but with a concentration, Np, of dopant which locally increases the concentration in the substrate to above Ns and has a length, Lp, as short as possible.

Two second pockets 9, 10 are formed in the channel region 6. The second pockets are each stacked against one of the first pockets, but with a length, Ln, greater than the length, Lp, of the first pockets. The second pockets are doped with a dopant of the second conductivity type. For example, the dopant may be an n-type dopant with a concentration, Nn, such that Nn is less than the concentration Np of dopant of the first conductivity type in the substrate.

Thus, in the zones of the second pockets, the net concentration of dopant of the first conductivity type (for example, the p-type dopant) is decreased but the nature of the conductivity in the channel region is not changed. The channel may still remain a region of p-type conductivity.

FIG. 2, in which the same reference numbers denote the same elements as previously, shows another embodiment of a semiconductor device. FIG. 2 shows that the second pockets 9, 10 may include pluralities of elementary pockets stacked against one another. For example, pluralities of elementary pockets may include three elementary pockets as shown in the embodiment of FIG. 2.

Each elementary pocket of a given rank, i, has a length, Lni, and a concentration, Nni, of dopant of the second conductivity type which satisfy the following relationships:

    • Lp<Lni,
    • Lni−1<Lni<Lni+1,
    • Nni−1<Nni<Nni+1, and
    • the sum ΣNni of the concentrations of the dopant of the second conductivity type in the elementary pockets being such that:
    • ΣNni<Ns.

In other words, the elementary pockets stacked against the first pockets 7 and 8 are also stacked against one another. However, they have increasing lengths and, concurrently, concentrations of dopant of the first conductivity type which decrease as their lengths increase.

Moreover, the sum of the concentrations, ΣNni, of the stacked elementary pockets is such that it remains less than the concentration, Ns, of dopant of the first conductivity type in the substrate so that the conductivity type of the channel region 6 is not modified.

Thus, in the case shown in FIG. 2, in which the second pockets consist of three elementary pockets. The lengths and dopant concentrations of the elementary pockets satisfy the relationships:

    • Lp<Ln1,
    • Ln1<Ln2<Ln3,
    • Nn1>Nn2>Nn3, and
    • Nn1+Nn2+Nn3<Ns.

FIG. 3 shows simulated graphs of the threshold voltage, Vth, for transistors having a gate oxide layer 4 nm in thickness and for a drain/source voltage of 1.5 volts as a function of the effective channel length. The lengths, Lp, and the concentrations, Np, of the first pockets doped with a dopant of the same type as the substrate correspond to the minimum channel length to be obtained and the highest doping.

Curve A corresponds to the stacking of a single second pocket and shows that a flat Vth is obtained for a channel length down to 0.15 μm.

Curve B corresponds to the stacking of two second pockets and shows that a flat Vth is obtained for a channel length down to 0.07 μm.

Finally, curve C corresponds to the stacking of seven second pockets and shows that a flat Vth can be obtained for a channel length down to 0.025 μm.

Thus, the above curves show that the necessary doping levels remain reasonable and make it possible to obtain flat curves of Vth as a function of the effective channel length down to effective lengths of 25 nm. This may be so even with gate oxide thicknesses of 4 nm.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4154626Feb 24, 1978May 15, 1979International Business Machines CorporationProcess of making field effect transistor having improved threshold stability by ion-implantation
US4276095Mar 12, 1979Jun 30, 1981International Business Machines CorporationMethod of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations
US4636822Aug 27, 1984Jan 13, 1987International Business Machines CorporationGaAs short channel lightly doped drain MESFET structure and fabrication
US4683485Dec 27, 1985Jul 28, 1987Harris CorporationTechnique for increasing gate-drain breakdown voltage of ion-implanted JFET
US4801555Jan 14, 1987Jan 31, 1989Motorola, Inc.Two step-low dosage then high dosage dopants
US4851360Mar 9, 1988Jul 25, 1989Texas Instruments IncorporatedNMOS source/drain doping with both P and As
US4966859Jan 3, 1989Oct 30, 1990Siemens AktiengesellschaftVoltage-stable sub-μm MOS transistor for VLSI circuits
US4968639Dec 14, 1988Nov 6, 1990Sgs-Thomson Microelectronics S.R.L.Semiconductors
US4987088Jul 18, 1989Jan 22, 1991Sgs-Thomson Microelectronics S.R.L.Fabrication of CMOS devices with reduced gate length
US5006477Nov 25, 1988Apr 9, 1991Hughes Aircraft CompanyIntegrated circuits
US5021851Dec 13, 1989Jun 4, 1991Texas Instruments IncorporatedNMOS source/drain doping with both P and As
US5045898Aug 30, 1988Sep 3, 1991At&T Bell LaboratoriesCMOS integrated circuit having improved isolation
US5132753Mar 23, 1990Jul 21, 1992Siliconix IncorporatedOptimization of BV and RDS-on by graded doping in LDD and other high voltage ICs
US5143857Jul 30, 1990Sep 1, 1992Triquint Semiconductor, Inc.Method of fabricating an electronic device with reduced susceptiblity to backgating effects
US5270235Jan 3, 1989Dec 14, 1993Seiko Epson CorporationSemiconductor device fabrication
US5371394Nov 15, 1993Dec 6, 1994Motorola, Inc.Double implanted laterally diffused MOS device and method thereof
US5409848Mar 31, 1994Apr 25, 1995Vlsi Technology, Inc.Angled lateral pocket implants on p-type semiconductor devices
US5422510Oct 30, 1992Jun 6, 1995Analog Devices, IncorporatedMOS transistor with non-uniform channel dopant profile
US5449937Feb 21, 1995Sep 12, 1995Sharp Kabushiki KaishaField effect transistor with short channel and manufacturing method therefor
US5548148Sep 29, 1995Aug 20, 1996International Business Machines CorporationMOS channel device with counterdoping of ion implant for reduced substrate sensitivity
US5675166Jul 7, 1995Oct 7, 1997Motorola, Inc.FET with stable threshold voltage and method of manufacturing the same
US5716861Jun 7, 1995Feb 10, 1998Texas Instruments IncorporatedInsulated-gate field-effect transistor structure and method
US5731611Jan 30, 1996Mar 24, 1998Megamos CorporationMOSFET transistor cell manufactured with selectively implanted punch through prevent and threshold reductoin zones
US5759901Aug 1, 1997Jun 2, 1998Vlsi Technology, Inc.Graded source and drain impurity regions comprise a relatively linear continuum of doped regions, ranging from lightly doped, to moderately doped to heavily doped regions
US5767557May 24, 1996Jun 16, 1998Lucent Technologies Inc.PMOSFETS having indium or gallium doped buried channels and n+polysilicon gates and CMOS devices fabricated therefrom
US5770880Sep 3, 1996Jun 23, 1998Harris CorporationP-collector H.V. PMOS switch VT adjusted source/drain
US5827763Jan 30, 1997Oct 27, 1998Advanced Micro Devices, Inc.Method of forming a multiple transistor channel doping using a dual resist fabrication sequence
US5858827May 27, 1997Jan 12, 1999Sony CorporationMethod of manufacturing MOS transistor device with improved threshold value control and reduced reverse short channel effect
US5874329Dec 5, 1996Feb 23, 1999Lsi Logic CorporationMethod for artificially-inducing reverse short-channel effects in deep sub-micron CMOS devices
US5949105 *Mar 1, 1993Sep 7, 1999Texas Instruments IncorporatedInsulated-gate field-effect transistor structure and method
US6017798Jun 2, 1997Jan 25, 2000Motorola, Inc.FET with stable threshold voltage and method of manufacturing the same
US6020244Dec 30, 1996Feb 1, 2000Intel CorporationChannel dopant implantation with automatic compensation for variations in critical dimension
US6091111Sep 19, 1996Jul 18, 2000National Semiconductor CorporationHigh voltage mos device having an extended drain region with different dopant species
US6150200Apr 3, 1998Nov 21, 2000Motorola, Inc.Semiconductor device and method of making
US6172406Aug 26, 1998Jan 9, 2001Texas Instruments IncorporatedBreakdown drain extended NMOS
US6284579Oct 14, 1999Sep 4, 2001Taiwan Semiconductor Manufacturing CompanyDrain leakage reduction by indium transient enchanced diffusion (TED) for low power applications
US6352912Mar 30, 2000Mar 5, 2002International Business Machines CorporationPrior to formation of gate, blanket implanting neutral dopant into semiconductor substrate at energy dose sufficient to implant dopant at depth greater than that of diffusion regions, forming peak concentration at specified depth
US6387763Nov 18, 1999May 14, 2002Stmicroelectronics S.R.L.Field-effect transistor and corresponding manufacturing method
US6410393Aug 17, 2000Jun 25, 2002Advanced Micro Devices, Inc.Semiconductor device with asymmetric channel dopant profile
US6465332Apr 14, 1998Oct 15, 2002Stmicroelectronics S.A.Method of making MOS transistor with high doping gradient under the gate
US6486510Nov 12, 2001Nov 26, 2002International Business Machines CorporationReduction of reverse short channel effects by implantation of neutral dopants
US6507058Oct 17, 2000Jan 14, 2003Semiconductor Components Industries LlcLow threshold compact MOS device with channel region formed by outdiffusion of two regions and method of making same
US6559019May 17, 2000May 6, 2003Texas Instruments IncorporatedBreakdown drain extended NMOS
US6593623 *Sep 20, 1999Jul 15, 2003Advanced Micro Devices, Inc.Reduced channel length lightly doped drain transistor using a sub-amorphous large tilt angle implant to provide enhanced lateral diffusion
US6667513Jun 5, 2000Dec 23, 2003FRANCE TéLéCOMSemiconductor device with compensated threshold voltage and method for making same
US6700160Oct 17, 2000Mar 2, 2004Texas Instruments IncorporatedDouble-diffused MOS (DMOS) power transistor with a channel compensating implant
US6737715Mar 4, 2002May 18, 2004Stmicroelectronics S.R.L.Field-effect transistor and corresponding manufacturing method
US6960499Jun 14, 2004Nov 1, 2005Texas Instruments IncorporatedDual-counterdoped channel field effect transistor and method
US7112501Oct 20, 2003Sep 26, 2006Oki Electric Industry Co., Ltd.Method of fabrication a silicon-on-insulator device with a channel stop
US20020039819Jun 18, 2001Apr 4, 2002Guiseppe CurelloMethod for manufacturing a field effect transistor
US20040061187Sep 30, 2002Apr 1, 2004Weber Cory E.Indium-boron dual halo MOSFET
US20040132260Nov 14, 2003Jul 8, 2004Stmicroelectronics SaProcess for fabricating a short-gate-length MOS transistor and integrated circuit comprising such a transistor
US20050151174Dec 28, 2004Jul 14, 2005Kim Tae W.Semiconductor device and fabricating method thereof
EP0763855A2Sep 12, 1996Mar 19, 1997Texas Instruments IncorporatedAsymmetrical FET and method of fabrication
JPH06318698A Title not available
Non-Patent Citations
Reference
1Hajime Kurata et al: "Self-Aligned Control of Threshold Voltages in Sub-0.2-mum MOSFET's" IEEE Transactions on Electron Devices, vol. 45, No. 10, US, New-York, NY: Oct. 1998, pp. 2161-2166, XP000786856 ISBN: 0018-9383.
2Hajime Kurata et al: "Self-Aligned Control of Threshold Voltages in Sub-0.2-μm MOSFET's" IEEE Transactions on Electron Devices, vol. 45, No. 10, US, New-York, NY: Oct. 1998, pp. 2161-2166, XP000786856 ISBN: 0018-9383.
3Yoshinori Okumura et al.: "Source-to Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Controllability" IEEE Transactions on Electron Devices, vol. 39, No. 11, US, New-York, NY: IEEE, Nov. 1992, pp. 2541-2552, XP000321695 ISBN: 0018-9383.
4Yoshinori Okumura et al.: "Source—to Drain Nonuniformly Doped Channel (NUDC) MOSFET Structures for High Current Drivability and Threshold Controllability" IEEE Transactions on Electron Devices, vol. 39, No. 11, US, New-York, NY: IEEE, Nov. 1992, pp. 2541-2552, XP000321695 ISBN: 0018-9383.
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Classifications
U.S. Classification257/335, 438/194, 257/344, 257/E29.278, 438/174, 257/336
International ClassificationH01L21/265, H01L21/336, H01L21/225, H01L29/10, H01L31/062, H01L31/113, H01L31/119, H01L29/76, H01L29/94
Cooperative ClassificationH01L21/26586, H01L29/1041, H01L29/66575, H01L21/2253
European ClassificationH01L29/10D2B2, H01L21/265F, H01L21/225A2D, H01L29/66M6T6F11B
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