|Publication number||USRE41801 E1|
|Application number||US 10/404,144|
|Publication date||Oct 5, 2010|
|Filing date||Mar 31, 1998|
|Priority date||Mar 31, 1997|
|Also published as||US6300150, WO1998044562A1|
|Publication number||10404144, 404144, PCT/1998/6150, PCT/US/1998/006150, PCT/US/1998/06150, PCT/US/98/006150, PCT/US/98/06150, PCT/US1998/006150, PCT/US1998/06150, PCT/US1998006150, PCT/US199806150, PCT/US98/006150, PCT/US98/06150, PCT/US98006150, PCT/US9806150, US RE41801 E1, US RE41801E1, US-E1-RE41801, USRE41801 E1, USRE41801E1|
|Original Assignee||Nextreme Thermal Solutions, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (28), Non-Patent Citations (11), Referenced by (5), Classifications (27), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims benefit of Provisional Appln No. 60/042,845 filed Mar. 31, 1997.
This invention was made with Government support under Contracts N00014-94-C-0088 and/or N00014-97-C-0088 awarded by the Office of Naval Research and Contract N00014-97-C-0211 awarded by the Defense Advanced Research Projects Agency. The Government has certain rights in the invention.
1. Field of the Invention
The present invention relates to thin-film thermoelectric devices and methods of manufacturing such devices, and particularly to thin-film thermoelectric devices with high utilization efficiency and high cooling/packing density and methods of manufacturing such devices.
Thermoelectric thin films have been used to form high-performance thermoelectric devices. Superlattice thermoelectric materials and quantum-well and quantum-dot structured materials have been proposed. However, there exists a need to produce thin-film thermoelectric devices with a good thermoelement aspect-ratio for em μm-thick thin-films, and a need to easily interconnect these thermoelements. The thin-film thermoelectric devices should also be scalable to a variety of heat loads and manufacturable in large volume (area). The methods used to manufacture the devices must be amenable to automation, compatible with cascading or multi-staging (leading to a smaller ΔT per stage for a higher coefficient of performance in a refrigerator or for higher efficiency in a power generator) and is equally applicable to both cooling and power generation. Further, the device technology would enable the insertion of high-ZT thin-films (i.e. films with a figure of merit ZT greater than one) into high performance cooling devices while keeping the current levels compatible with present-day coolers and similar power generation devices.
An object of the present invention is to provide a thin-film thermoelectric device and a method of manufacturing the device that achieves high material utilization efficiency.
Another object of the present invention is to provide a thin-film thermoelectric device and a method of manufacturing the device that achieves high cooling/packing density.
A further object of the present invention is to provide a thin-film thermoelectric device and a method of manufacturing the device that is scalable to a variety of heat loads.
A still further object of the present invention to provide and manufacture large area thin-film thermoelectric devices.
Still another object is provide a thermoelectric elements that can be used with low-cost power supplies.
These and other objects are achieved by a thermoelectric device having a plurality of thermoelectric elements (i.e. a plurality of thermoelements) formed using thin films in the range of microns to tens of microns. The elements may be arranged in a matrix pattern with adjacent rows having opposite conductivity type. The elements are disposed on a header with a pattern of conductive members. Pairs of adjacent elements of opposite conductivity type are disposed on and connected by the conductive members. A second header with a second pattern of conductive members is disposed on top of the elements. The conductive members of the second header connect adjacent pairs of connected elements so that the pairs are connected in series.
These and other objects are also achieved by a method of forming a thermoelectric device. In one embodiment, thin films having a thickness on the order of microns to tens of ductivity type may be formed on different substrates or one film may be formed and later selectively doped to provide regions of opposite conductivity. The film or films are disposed on the first header and the substrates removed. When films of opposite conductivity type are used, they are arranged in an alternating manner. The films are patterned to provide a plurality of thermoelectric elements in a matrix pattern. Pairs of elements, one of each conductivity type are disposed on respective conductive members on the first header. A second header is disposed on the top of the elements. Conductive members on the second header contact the pairs such that the pairs are connected in series.
The device and method according to the invention are scalable to a variety of heat loads and is manufacturable in volume. They are amenable to automation and are compatible with cascading or multistaging. Further, the device and method are applicable to both cooling and power generation.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Referring to the drawings, wherein like reference numerals designate corresponding elements throughout the several view, and more particularly to
The method of manufacturing the device according to the invention is shown in the figure. In
As shown in
The segments 20 and 21 are bonded onto a cooling header or a power header 30 with alternating conductivity in FIG. 3. The header can made of, for example, BeO. The bonding may be carried out using a conventional bonding method. Note that the substrates are facing upward and that the segments 20 and 21 have a finite separation, in this case of about 10 μm.
The bonding pattern of the header 30, for an exemplary 8×9 thermoelement matrix, upon which the segments are bonded is shown in FIG. 4. The surfaces of the cooling header/power header 30 that come in contact with the n- and p-type segments have to be metallized prior to assembly to provide the necessary low-resistance electrical connection between adjacent n- and p-type segments. The header includes a metallization for bonding an n-type segment of size a1, a metallization for bonding a p-type segment of size a2, and a metallization for series-connecting n- and p-type segments to form a couple, The metallizations have a width a3 and are separated in the in the length direction by a gap of size b2 and in the width direction by a gap of size c. Typical dimensions for a1, a2, b1, b2 and c are given in FIG. 4.
As shown in
Following the bonding of n- and p-type segments, the substrates from each of the p- and n-segments are removed selectively without affecting the films 11 and 12. This can typically be achieved by using selective etchants for substrates. Similar substrates, if used for both the n- and p-type segments 20 and 21, can be removed in a single substrate removal process. After this process the BASIC-TFTD device structure would look as shown in
As shown in
In the next processing step the segments 11 and 12 are patterned in the y-direction into sections 60 and 61. This step maybe carried out using photolithographic patterning followed by etching, or by laser ablation, for example. The device at this stage is shown in FIG. 6. Typical parameters of the sections, for two examples, are given as:
a1, a2 ˜1 mm
Area = a1 × a3 = 0.0005 cm2
a3 ˜50 mm
a1, a2 ˜5 mm
Area = a1 × a3 = 0.005 cm2
a3 ˜100 mm
The dimensions indicated for a3 and c can easily be achieved with conventional microelectronic processing/etching. Also, b, c<<a1, a2, and a3. The invention also provides several advantages. The material removed in etching is very small, leading to good material utilization efficiency high cooling/packing density can be achieved.
Low resistivity contact metallization is then evaporated on upper surface of the n- and p-type sections, as shown in FIG. 7. In this step, either the same metallization can be used for both of the n- and p-type section, or different metallizations can be used (separate evaporations), depending on the contact resistivity requirements.
A top, pre-patterned metallization header 90 is then attached to the metallized sections. Shown in
The two leads, A and B are shown. A positive voltage would be applied to lead A and a negative (or ground) voltage would be applied to lead B for cooling. The metallization pattern pads contacting ntype and ptype elements are shown by parentheses. The spacing of the patterns matches that of the sections.
Electrical shorts between pads are indicated by an “x” in the metallized header/heat-sink. These shorts serve to keep the current flow from the top of the n-type element to the bottom of the n-type element, and similarly from the bottom of the p-type element to the top of the prsype element. In a cooling device the top is defined as being located on the heat-sink side and the bottom is defined as being on the source side. Such an arrangement will also keep the alternating n- and p-type elements in series electrically. Thus, according to the invention all of the thermoelements are thermally in parallel (between heat-sink and heat-source) and electrically in series.
For this 8×9 matrix of thermoelements, four each of the n- and p-type elements (identified by “y”) do not participate in the current transport through the thickness of the film They only serve to provide the electrical connection and uniform mechanical strength in the arrange men t of the thermoelements.
In the case of an “m×n” matrix of thermoelements (m is horizontal and n is vertical) and n is odd, with n- and p-type elements alternating along the m direction, we can see that the utilization efficiency is:
This efficiency will nearly approach unity when n is large and m is large. For example, in the 8×9 matrix, −89% utilization of material is obtained. For a 25×23 element matrix, >96% utilization of material is achieved. Assuming ideal heat-spreading on the heat-sink side header and the source-side header, the heat spreading in the “non-useful” elements would be about the same as the “useful” elements. Thus, we can expect module efficiency≅(intrinsic couple efficiency×material utilization efficiency) discussed above. By choosing m>>n (if system constraints permit) a non-square geometry will minimize the difference between module and intrinsic couple efficiency. This, of course, assumes ideal heat spreading between the thermoelement and the headers. A completed device according to the invention, having a set of headers 30 and 90 (with the good head spreading characteristics) and n- and p-type elements interconnected employing an 8×9 matrix, is shown in FIG. 9.
While the sections 60 and 61 disclosed as being approximately square, the aspect ratios of the sections can be adjusted. For example, the aspect ratios can be selected to provide a desired geometry while satisfying the above m>>n condition. Also, the aspect ratios can be selected to insure low-current operation, allowing the use of low-cost power supplies for connection to the headers 30 and 90.
The material (superlattice or non-superlattice) for the n- and p-type elements can be different, as is usually the case in many conventional bulk materials. However, if the materials are the same for n- and p-type elements, and if one polarity can be typed-converted to another (p to n or n to p) by a technique, for example impurity-diffusion, without disordering the superlattice or introducing other detrimental effects, then a Bipolar Diffused, Series Interconnected, Thin-Film Thermoelectric Device (BDSIC-TFTD) can be constructed which does not require the assembly step shown in FIG. 3(i.e. by direct deposition). The type-conversion can be performed at a convenient stage in the manufacturing process, such as when the device has the structure shown in
The backside of an integrated circuit chip may be used as the cooling or power header. The backside, especially if it is electrically conducting, needs to be suitably modified to confine the electrical current to the thermoelectric element. One example of suitable preparation is p-n junction isolation in the backside of the chip whereby the current is made to flow through the intended thermoelectric electric elements, i.e. is confined to the elements, and is not shunted by the conducting backside of the chip. Other modifications of the backside are possible to achieve similar confinement of the current.
The backside of the chip should be of good thermal conductivity. The backside then may be used to extract heat which could be used for other purposes such as power generation. For example, the power generated using the heat could be used provide power to other circuits or to other cooling devices.
The BASIC-TFTD according to the invention is scalable to a variety of heat loads and is manufacturable in large volume (area). It is amenable to automation, is compatible with cascading or multi-staging (leading to a smaller ΔT per stage for a higher coefficient of performance in a refrigerator or for higher efficiency in a power generator) and is equally applicable to both cooling and power generation.
Obviously, numerous modifications and variations os the present invention are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
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|U.S. Classification||438/3, 257/E29.071, 438/666, 257/E23.067, 438/29, 438/54, 257/470, 257/930, 257/84, 257/94, 257/E23.082, 257/E29.103, 438/27, 257/E23.081|
|International Classification||H01L35/32, H01L35/08, H01L35/30, H01L21/44|
|Cooperative Classification||Y10S257/93, H01L35/08, B82Y10/00, H01L35/32, H01L35/30|
|European Classification||B82Y10/00, H01L35/32, H01L35/08, H01L35/30|
|Apr 20, 2005||AS||Assignment|
Owner name: NEXTREME THERMAL SOLUTIONS, INC., NORTH CAROLINA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RESEARCH TRIANGLE INSTITUTE;REEL/FRAME:016686/0166
Effective date: 20050323
|Mar 22, 2011||CC||Certificate of correction|
|May 16, 2013||SULP||Surcharge for late payment|
Year of fee payment: 11
|May 16, 2013||FPAY||Fee payment|
Year of fee payment: 12